Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main
diff --git a/verilog/dv/gpio_test/gpio_test.c b/verilog/dv/gpio_test/gpio_test.c
new file mode 100644
index 0000000..50ea61b
--- /dev/null
+++ b/verilog/dv/gpio_test/gpio_test.c
@@ -0,0 +1,65 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+/*
+ GPIO Test:
+ - Configures MPRJ pin 21 as outputs
+ - Observes gpio out value (in the testbench)
+*/
+
+void main()
+{
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+
+ */
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ // Configure IO pin 21 as user output
+ // Observe value in the testbench
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+}
+
diff --git a/verilog/dv/gpio_test/gpio_test_tb.v b/verilog/dv/gpio_test/gpio_test_tb.v
new file mode 100644
index 0000000..131b5ff
--- /dev/null
+++ b/verilog/dv/gpio_test/gpio_test_tb.v
@@ -0,0 +1,169 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module gpio_test_tb;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg power3, power4;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [7:0] mprj_io_0;
+
+ assign mprj_io_0 = mprj_io[7:0];
+ // assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ // assign mprj_io[3] = 1'b1;
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("gpio_test.vcd");
+ $dumpvars(0, gpio_test_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ // Observe Output pins [7:0]
+ wait(mprj_io_0 == 8'h01);
+ wait(mprj_io_0 == 8'h02);
+ wait(mprj_io_0 == 8'h03);
+ wait(mprj_io_0 == 8'h04);
+ wait(mprj_io_0 == 8'h05);
+ wait(mprj_io_0 == 8'h06);
+ wait(mprj_io_0 == 8'h07);
+ wait(mprj_io_0 == 8'h08);
+ wait(mprj_io_0 == 8'h09);
+ wait(mprj_io_0 == 8'h0A);
+ wait(mprj_io_0 == 8'hFF);
+ wait(mprj_io_0 == 8'h00);
+
+ `ifdef GL
+ $display("Monitor: Test 1 Mega-Project IO (GL) Passed");
+ `else
+ $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ power4 <= 1'b0;
+ #100;
+ power1 <= 1'b1;
+ #100;
+ power2 <= 1'b1;
+ #100;
+ power3 <= 1'b1;
+ #100;
+ power4 <= 1'b1;
+ end
+
+ always @(mprj_io) begin
+ #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire USER_VDD3V3 = power3;
+ wire USER_VDD1V8 = power4;
+ wire VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (USER_VDD3V3),
+ .vdda2 (USER_VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (USER_VDD1V8),
+ .vccd2 (USER_VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("gpio_test.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/openram_testchip_tb.v b/verilog/rtl/openram_testchip_tb.v
deleted file mode 100644
index 223af0b..0000000
--- a/verilog/rtl/openram_testchip_tb.v
+++ /dev/null
@@ -1,425 +0,0 @@
-`define assert(signal, value) \
-if (!(signal === value)) begin \
- $display("ASSERTION FAILED in %m: signal != value"); \
- $finish;\
-end
-
-`timescale 1ns/1ns
-
-`include "openram_testchip.v"
-`include "openram_defines.v"
-`include "sky130_sram_1kbyte_1rw1r_32x256_8.v"
-`include "sky130_sram_1kbyte_1rw1r_8x1024_8.v"
-`include "sky130_sram_2kbyte_1rw1r_32x512_8.v"
-`include "sky130_sram_4kbyte_1rw1r_32x1024_8.v"
-`include "sky130_sram_8kbyte_1rw1r_32x2048_8.v"
-`include "sram_1rw0r0w_32_256_sky130.v"
-`include "sram_1rw0r0w_32_512_sky130.v"
-`include "sram_1rw0r0w_32_1024_sky130.v"
-`include "sram_1rw0r0w_64_512_sky130.v"
-
-module test_chip_tb;
-
- reg reset;
- reg in_select;
- reg la_clk;
- reg la_in_load;
- reg la_sram_load;
- reg [`TOTAL_SIZE-1:0] la_data_in;
- reg gpio_clk;
- reg gpio_in;
- reg gpio_scan;
- reg gpio_sram_load;
-
- reg sram_clk;
-
- wire [`ADDR_SIZE-1:0] left_addr0;
- wire [`DATA_SIZE-1:0] left_din0;
- wire left_web0;
- wire [`WMASK_SIZE-1:0] left_wmask0;
- wire [`ADDR_SIZE-1:0] left_addr1;
- wire [`DATA_SIZE-1:0] left_din1;
- wire left_web1;
- wire [`WMASK_SIZE-1:0] left_wmask1;
- // One CSB for each SRAM
- wire [`MAX_CHIPS-1:0] left_csb0;
- wire [`MAX_CHIPS-1:0] left_csb1;
-
- wire [`ADDR_SIZE-1:0] right_addr0;
- wire [`DATA_SIZE-1:0] right_din0;
- wire right_web0;
- wire [`WMASK_SIZE-1:0] right_wmask0;
- wire [`MAX_CHIPS-1:0] right_csb0;
-
- wire [`DATA_SIZE-1:0] sram0_data0;
- wire [`DATA_SIZE-1:0] sram0_data1;
- wire [`DATA_SIZE-1:0] sram1_data0;
- wire [`DATA_SIZE-1:0] sram1_data1;
- wire [`DATA_SIZE-1:0] sram2_data0;
- wire [`DATA_SIZE-1:0] sram2_data1;
- wire [`DATA_SIZE-1:0] sram3_data0;
- wire [`DATA_SIZE-1:0] sram3_data1;
- wire [`DATA_SIZE-1:0] sram4_data0;
- wire [`DATA_SIZE-1:0] sram4_data1;
- wire [`DATA_SIZE-1:0] sram5_data0;
- wire [`DATA_SIZE-1:0] sram5_data1;
- wire [`DATA_SIZE-1:0] sram6_data0;
- wire [`DATA_SIZE-1:0] sram6_data1;
- wire [`DATA_SIZE-1:0] sram7_data0;
- wire [`DATA_SIZE-1:0] sram7_data1;
- wire [`DATA_SIZE-1:0] sram8_data0;
- wire [`DATA_SIZE-1:0] sram8_data1;
- wire [`DATA_SIZE-1:0] sram9_data0;
- wire [`DATA_SIZE-1:0] sram9_data1;
- wire [`DATA_SIZE-1:0] sram10_data0;
- wire [`DATA_SIZE-1:0] sram10_data1;
- wire [`DATA_SIZE-1:0] sram11_data0;
- wire [`DATA_SIZE-1:0] sram11_data1;
- wire [`DATA_SIZE-1:0] sram12_data0;
- wire [`DATA_SIZE-1:0] sram12_data1;
- wire [`DATA_SIZE-1:0] sram13_data0;
- wire [`DATA_SIZE-1:0] sram13_data1;
- wire [`DATA_SIZE-1:0] sram14_data0;
- wire [`DATA_SIZE-1:0] sram14_data1;
- wire [`DATA_SIZE-1:0] sram15_data0;
- wire [`DATA_SIZE-1:0] sram15_data1;
-
-
- wire [`TOTAL_SIZE-1:0] la_data_out;
-openram_testchip CONTROL_LOGIC(
- .reset(reset),
- .in_select(in_select),
- .la_clk(la_clk),
- .la_in_load(la_in_load),
- .la_data_in(la_data_in),
- .la_sram_load(la_sram_load),
- .gpio_clk(gpio_clk),
- .gpio_in(gpio_in),
- .gpio_scan(gpio_scan),
- .gpio_sram_load(gpio_sram_load),
- .sram0_data0(sram0_data0),
- .sram0_data1(sram0_data1),
- .sram1_data0(sram1_data0),
- .sram1_data1(sram1_data1),
- .sram2_data0(sram2_data0),
- .sram2_data1(sram2_data1),
- .sram3_data0(sram3_data0),
- .sram3_data1(sram3_data1),
- .sram4_data0(sram4_data0),
- .sram4_data1(sram4_data1),
- .sram5_data0(sram5_data0),
- .sram5_data1(sram5_data1),
- .sram6_data0(sram6_data0),
- .sram6_data1(sram6_data1),
- .sram7_data0(sram7_data0),
- .sram7_data1(sram7_data1),
- .sram8_data0(sram8_data0),
- .sram8_data1(sram8_data1),
- .sram9_data0(sram9_data0),
- .sram9_data1(sram9_data1),
- .sram10_data0(sram10_data0),
- .sram10_data1(sram10_data1),
- .sram11_data0(sram11_data0),
- .sram11_data1(sram11_data1),
- .sram12_data0(sram12_data0),
- .sram12_data1(sram12_data1),
- .sram13_data0(sram13_data0),
- .sram13_data1(sram13_data1),
- .sram14_data0(sram14_data0),
- .sram14_data1(sram14_data1),
- .sram15_data0(sram15_data0),
- .sram15_data1(sram15_data1),
- .left_addr0(left_addr0),
- .left_din0(left_din0),
- .left_web0(left_web0),
- .left_wmask0(left_wmask0),
- .left_addr1(left_addr1),
- .left_din1(left_din1),
- .left_web1(left_web1),
- .left_wmask1(left_wmask1),
- .left_csb0(left_csb0),
- .left_csb1(left_csb1),
- .right_addr0(right_addr0),
- .right_din0(right_din0),
- .right_web0(right_web0),
- .right_wmask0(right_wmask0),
- .right_csb0(right_csb0),
- .la_data_out(la_data_out),
- .gpio_out(gpio_out)
-);
-
-sky130_sram_1kbyte_1rw1r_8x1024_8 SRAM0
- (
- `ifdef USE_POWER_PINS
- .vccd1(vccd1),
- .vssd1(vssd1),
- `endif
- .clk0 (sram_clk),
- .csb0 (left_csb0[0]),
- .web0 (left_web0),
- .wmask0 (left_wmask0[0]),
- .addr0 (left_addr0[9:0]),
- .din0 (left_din0[7:0]),
- .dout0 (sram0_data0[7:0]),
- .clk1 (sram_clk),
- .csb1 (left_csb1[0]),
- .addr1 (left_addr1[9:0]),
- .dout1 (sram0_data1[7:0])
- );
-assign sram0_data0[`DATA_SIZE-1:8] = 0;
-assign sram0_data1[`DATA_SIZE-1:8] = 0;
-
-sky130_sram_1kbyte_1rw1r_32x256_8 SRAM1
- (
- `ifdef USE_POWER_PINS
- .vccd1(vccd1),
- .vssd1(vssd1),
- `endif
- .clk0 (sram_clk),
- .csb0 (left_csb0[1]),
- .web0 (left_web0),
- .wmask0 (left_wmask0),
- .addr0 (left_addr0[7:0]),
- .din0 (left_din0),
- .dout0 (sram1_data0),
- .clk1 (sram_clk),
- .csb1 (left_csb1[1]),
- .addr1 (left_addr1[7:0]),
- .dout1 (sram1_data1)
- );
-
-sky130_sram_2kbyte_1rw1r_32x512_8 SRAM2
- (
- `ifdef USE_POWER_PINS
- .vccd1(vccd1),
- .vssd1(vssd1),
- `endif
- .clk0 (sram_clk),
- .csb0 (left_csb0[2]),
- .web0 (left_web0),
- .wmask0 (left_wmask0),
- .addr0 (left_addr0[8:0]),
- .din0 (left_din0),
- .dout0 (sram2_data0),
- .clk1 (sram_clk),
- .csb1 (left_csb1[2]),
- .addr1 (left_addr1[8:0]),
- .dout1 (sram2_data1)
- );
-
-sky130_sram_4kbyte_1rw1r_32x1024_8 SRAM3
- (
- `ifdef USE_POWER_PINS
- .vccd1(vccd1),
- .vssd1(vssd1),
- `endif
- .clk0 (sram_clk),
- .csb0 (left_csb0[3]),
- .web0 (left_web0),
- .wmask0 (left_wmask0),
- .addr0 (left_addr0[9:0]),
- .din0 (left_din0),
- .dout0 (sram3_data0),
- .clk1 (sram_clk),
- .csb1 (left_csb1[3]),
- .addr1 (left_addr1[9:0]),
- .dout1 (sram3_data1)
- );
-
-sky130_sram_8kbyte_1rw1r_32x2048_8 SRAM4
- (
- `ifdef USE_POWER_PINS
- .vccd1(vccd1),
- .vssd1(vssd1),
- `endif
- .clk0 (sram_clk),
- .csb0 (left_csb0[4]),
- .web0 (left_web0),
- .wmask0 (left_wmask0),
- .addr0 (left_addr0[10:0]),
- .din0 (left_din0),
- .dout0 (sram4_data0),
- .clk1 (sram_clk),
- .csb1 (left_csb1[4]),
- .addr1 (left_addr1[10:0]),
- .dout1 (sram4_data1)
- );
-
-// Not working yet
-// sky130_sram_16kbyte_1rw1r_32x4096_8 SRAM6
-// (
-// `ifdef USE_POWER_PINS
-// .vccd1(vccd1),
-// .vssd1(vssd1),
-// `endif
-// .clk0 (sram_clk),
-// .csb0 (csb0[6]),
-// .web0 (web0),
-// .wmask0 (wmask0),
-// .addr0 (addr0),
-// .din0 (din0),
-// .dout0 (sram6_data0),
-// .clk1 (sram_clk),
-// .csb1 (csb1[6]),
-// .addr1 (addr1),
-// .dout1 (sram6_data1)
-// );
-
-
-
-// Single port memories
-sram_1rw0r0w_32_256_sky130 SRAM8
- (
- `ifdef USE_POWER_PINS
- .vccd1(vccd1),
- .vssd1(vssd1),
- `endif
- .clk0 (sram_clk),
- .csb0 (right_csb0[8]),
- .web0 (right_web0),
- .wmask0 (right_wmask0),
- .addr0 (right_addr0[7:0]),
- .din0 (right_din0),
- .dout0 (sram8_data0)
- );
-assign sram8_data1 = 0;
-
-sram_1rw0r0w_32_512_sky130 SRAM9
- (
- `ifdef USE_POWER_PINS
- .vccd1(vccd1),
- .vssd1(vssd1),
- `endif
- .clk0 (sram_clk),
- .csb0 (right_csb0[9]),
- .web0 (right_web0),
- .wmask0 (right_wmask0),
- .addr0 (right_addr0[8:0]),
- .din0 (right_din0),
- .dout0 (sram9_data0)
- );
-assign sram9_data1 = 0;
-
-sram_1rw0r0w_32_1024_sky130 SRAM10
- (
- `ifdef USE_POWER_PINS
- .vccd1(vccd1),
- .vssd1(vssd1),
- `endif
- .clk0 (sram_clk),
- .csb0 (right_csb0[10]),
- .web0 (right_web0),
- .wmask0 (right_wmask0),
- .addr0 (right_addr0[9:0]),
- .din0 (right_din0),
- .dout0 (sram10_data0)
- );
-assign sram10_data1 = 0;
-
-wire [63:0] temp_sram11_data0;
-sram_1rw0r0w_64_512_sky130 SRAM11
- (
- `ifdef USE_POWER_PINS
- .vccd1(vccd1),
- .vssd1(vssd1),
- `endif
- .clk0 (sram_clk),
- .csb0 (right_csb0[11]),
- .web0 (right_web0),
- .wmask0 ({4'd0, right_wmask0}),
- .addr0 (right_addr0[8:0]),
- .din0 ({right_din0[31:16], 32'd0, right_din0[15:0]}),
- .dout0 (temp_sram11_data0)
- );
-
-assign sram11_data1 = 0;
-assign sram11_data0 = {temp_sram11_data0[64:49], temp_sram11_data0[15:0]};
-
-integer i, j;
-reg [3:0] sel;
-reg [111:0] in_data;
-reg [111:0] out_data;
-
-initial begin
- $dumpfile("testchip_tb.vcd");
- $dumpvars(0, test_chip_tb);
- gpio_clk = 1;
- la_clk = 0;
- la_in_load = 0;
- la_sram_load = 0;
- la_data_in = 0;
- sram_clk = 0;
- reset = 0;
-
- //Testing 32B Dual Port Memories
- for(i = 0; i < 1; i = i + 1) begin
- sel = i;
-
- //Write 1 to addr1 using GPIO Pins
- in_select = 1;
- gpio_scan = 1;
- gpio_sram_load = 0;
- in_data = {sel, 16'd1, 32'd1, 1'b0, 1'b0, 4'd15, 16'd0, 32'd0, 1'b1, 1'b1, 4'd0};
-
- for(j = 0; j < 112; j = j + 1) begin
- gpio_in = in_data[111 - j];
- #10;
- end
-
- gpio_scan = 0;
- gpio_sram_load = 1;
- sram_clk = 1;
- #5;
- sram_clk = 0;
- #5;
-
- //Write 2 to addr2 using GPIO Pins
- gpio_scan = 1;
- gpio_sram_load = 0;
- in_data = {sel, 16'd2, 32'd2, 1'b0, 1'b0, 4'd15, 16'd0, 32'd0, 1'b1, 1'b1, 4'd0};
-
- for(j = 0; j < 112; j = j + 1) begin
- gpio_in = in_data[111 - j];
- #10;
- end
-
- gpio_scan = 0;
- gpio_sram_load = 1;
- sram_clk = 1;
- #5;
- sram_clk = 0;
- #5;
-
- //Read addr1 and addr2
- gpio_scan = 1;
- gpio_sram_load = 0;
- in_data = {sel, 16'd1, 32'd0, 1'b0, 1'b1, 4'd0, 16'd2, 32'd0, 1'b0, 1'b1, 4'd0};
-
- for(j = 0; j < 112; j = j + 1) begin
- gpio_in = in_data[111 - j];
- #10;
- end
-
- gpio_scan = 0;
- gpio_sram_load = 1;
- sram_clk = 1;
- #5;
- sram_clk = 0;
- #5;
-
- gpio_scan = 1;
- for(j = 0; j < 112; j = j + 1) begin
- out_data[111 - j] = gpio_out;
- #10;
- end
- //#10;
- //`assert(la_data_out, {sel, 16'd1, 32'd1, 1'b0, 1'b1, 4'd0, 16'd2, 32'd2, 1'b0, 1'b1, 4'd0});
- end
-
-
- #10;$finish;
-end
-
-always
- #5 gpio_clk = !gpio_clk;
-endmodule
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..d678690 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -24,5 +24,14 @@
`include "gl/user_proj_example.v"
`else
`include "user_project_wrapper.v"
- `include "user_proj_example.v"
+ `include "openram_testchip.v"
+ `include "sky130_sram_1kbyte_1rw1r_8x1024_8.v"
+ `include "sky130_sram_1kbyte_1rw1r_32x256_8.v"
+ `include "sky130_sram_2kbyte_1rw1r_32x512_8.v"
+ `include "sky130_sram_4kbyte_1rw1r_32x1024_8.v"
+ `include "sky130_sram_8kbyte_1rw1r_32x2048_8.v"
+ `include "sram_1rw0r0w_32_256_sky130.v"
+ `include "sram_1rw0r0w_32_512_sky130.v"
+ `include "sram_1rw0r0w_32_1024_sky130.v"
+ `include "sram_1rw0r0w_64_512_sky130.v"
`endif
\ No newline at end of file
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 40a8938..34628c5 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -94,37 +94,36 @@
-wire [31:0] sram0_dout0;
-wire [31:0] sram0_dout1;
-wire [31:0] sram1_dout0;
-wire [31:0] sram1_dout1;
-wire [31:0] sram2_dout0;
-wire [31:0] sram2_dout1;
-wire [31:0] sram3_dout0;
-wire [31:0] sram3_dout1;
-wire [31:0] sram4_dout0;
-wire [31:0] sram4_dout1;
-wire [31:0] sram5_dout0;
-wire [31:0] sram5_dout1;
-wire [31:0] sram6_dout0;
-wire [31:0] sram6_dout1;
-wire [31:0] sram7_dout0;
-wire [31:0] sram7_dout1;
-wire [31:0] sram8_dout0;
-wire [31:0] sram8_dout1;
-wire [31:0] sram9_dout0;
-wire [31:0] sram9_dout1;
-wire [31:0] sram10_dout0;
-wire [31:0] sram10_dout1;
-wire [31:0] sram11_dout0;
-wire [31:0] sram11_dout1;
-wire [31:0] sram12_dout0;
-wire [31:0] sram12_dout1;
-wire [31:0] sram13_dout0;
-wire [31:0] sram13_dout1;
-wire [31:0] sram14_dout0;
-wire [31:0] sram14_dout1;
-
+ wire [31:0] sram0_dout0;
+ wire [31:0] sram0_dout1;
+ wire [31:0] sram1_dout0;
+ wire [31:0] sram1_dout1;
+ wire [31:0] sram2_dout0;
+ wire [31:0] sram2_dout1;
+ wire [31:0] sram3_dout0;
+ wire [31:0] sram3_dout1;
+ wire [31:0] sram4_dout0;
+ wire [31:0] sram4_dout1;
+ wire [31:0] sram5_dout0;
+ wire [31:0] sram5_dout1;
+ wire [31:0] sram6_dout0;
+ wire [31:0] sram6_dout1;
+ wire [31:0] sram7_dout0;
+ wire [31:0] sram7_dout1;
+ wire [31:0] sram8_dout0;
+ wire [31:0] sram8_dout1;
+ wire [31:0] sram9_dout0;
+ wire [31:0] sram9_dout1;
+ wire [31:0] sram10_dout0;
+ wire [31:0] sram10_dout1;
+ wire [31:0] sram11_dout0;
+ wire [31:0] sram11_dout1;
+ wire [31:0] sram12_dout0;
+ wire [31:0] sram12_dout1;
+ wire [31:0] sram13_dout0;
+ wire [31:0] sram13_dout1;
+ wire [31:0] sram14_dout0;
+ wire [31:0] sram14_dout1;
wire in_select = io_in[16];
wire resetn = io_in[15];
@@ -455,43 +454,6 @@
assign sram11_dout0 = {temp_sram11_dout0[64:49], temp_sram11_dout0[15:0]};
-
-
-// Hold dout from SRAM
-// clocked by SRAM clk
- reg [`DATA_SIZE-1:0] sram0_data0;
- reg [`DATA_SIZE-1:0] sram0_data1;
- reg [`DATA_SIZE-1:0] sram1_data0;
- reg [`DATA_SIZE-1:0] sram1_data1;
- reg [`DATA_SIZE-1:0] sram2_data0;
- reg [`DATA_SIZE-1:0] sram2_data1;
- reg [`DATA_SIZE-1:0] sram3_data0;
- reg [`DATA_SIZE-1:0] sram3_data1;
- reg [`DATA_SIZE-1:0] sram4_data0;
- reg [`DATA_SIZE-1:0] sram4_data1;
- reg [`DATA_SIZE-1:0] sram5_data0;
- reg [`DATA_SIZE-1:0] sram5_data1;
- reg [`DATA_SIZE-1:0] sram6_data0;
- reg [`DATA_SIZE-1:0] sram6_data1;
- reg [`DATA_SIZE-1:0] sram7_data0;
- reg [`DATA_SIZE-1:0] sram7_data1;
- reg [`DATA_SIZE-1:0] sram8_data0;
- reg [`DATA_SIZE-1:0] sram8_data1;
- reg [`DATA_SIZE-1:0] sram9_data0;
- reg [`DATA_SIZE-1:0] sram9_data1;
- reg [`DATA_SIZE-1:0] sram10_data0;
- reg [`DATA_SIZE-1:0] sram10_data1;
- reg [`DATA_SIZE-1:0] sram11_data0;
- reg [`DATA_SIZE-1:0] sram11_data1;
- reg [`DATA_SIZE-1:0] sram12_data0;
- reg [`DATA_SIZE-1:0] sram12_data1;
- reg [`DATA_SIZE-1:0] sram13_data0;
- reg [`DATA_SIZE-1:0] sram13_data1;
- reg [`DATA_SIZE-1:0] sram14_data0;
- reg [`DATA_SIZE-1:0] sram14_data1;
- reg [`DATA_SIZE-1:0] sram15_data0;
- reg [`DATA_SIZE-1:0] sram15_data1;
-
always @(posedge sram_clk) begin
if (!resetn) begin
sram0_data0 <= 0;
@@ -518,14 +480,14 @@
sram10_data1 <= 0;
sram11_data0 <= 0;
sram11_data1 <= 0;
- sram12_data0 <= 0;
- sram12_data1 <= 0;
- sram13_data0 <= 0;
- sram13_data1 <= 0;
- sram14_data0 <= 0;
- sram14_data1 <= 0;
- sram15_data0 <= 0;
- sram15_data1 <= 0;
+ //sram12_data0 <= 0;
+ //sram12_data1 <= 0;
+ //sram13_data0 <= 0;
+ //sram13_data1 <= 0;
+ //sram14_data0 <= 0;
+ //sram14_data1 <= 0;
+ //sram15_data0 <= 0;
+ //sram15_data1 <= 0;
end
else begin
sram0_data0 <= sram0_dout0;
@@ -563,21 +525,20 @@
end // else: !if(in_reset)
end
- assign sram5_data0 = 0;
- assign sram5_data1 = 0;
- assign sram6_data0 = 0;
- assign sram6_data1 = 0;
- assign sram7_data0 = 0;
- assign sram7_data1 = 0;
- assign sram12_data0 = 0;
- assign sram12_data1 = 0;
- assign sram13_data0 = 0;
- assign sram13_data1 = 0;
- assign sram14_data0 = 0;
- assign sram14_data1 = 0;
- assign sram15_data0 = 0;
- assign sram15_data1 = 0;
-
+ wire [`DATA_SIZE-1:0] sram5_data0 = 0;
+ wire [`DATA_SIZE-1:0] sram5_data1 = 0;
+ wire [`DATA_SIZE-1:0] sram6_data0 = 0;
+ wire [`DATA_SIZE-1:0] sram6_data1 = 0;
+ wire [`DATA_SIZE-1:0] sram7_data0 = 0;
+ wire [`DATA_SIZE-1:0] sram7_data1 = 0;
+ wire [`DATA_SIZE-1:0] sram12_data0 = 0;
+ wire [`DATA_SIZE-1:0] sram12_data1 = 0;
+ wire [`DATA_SIZE-1:0] sram13_data0 = 0;
+ wire [`DATA_SIZE-1:0] sram13_data1 = 0;
+ wire [`DATA_SIZE-1:0] sram14_data0 = 0;
+ wire [`DATA_SIZE-1:0] sram14_data1 = 0;
+ wire [`DATA_SIZE-1:0] sram15_data0 = 0;
+ wire [`DATA_SIZE-1:0] sram15_data1 = 0;
endmodule // user_project_wrapper
