commit: 37e8d43a515cd3f5e5caa5f000a514012850e381
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 22:48:34 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 22:48:34 2021 -0700
tree: c33f2adf89d4206aff375774f377c80e7a23aed0
parent: 197c62f98cebda9ce717b9ea97d16670bcf0f1a5 [diff]

In scan and memory operations correct, do correct out scan of GPIO bits

verilog/rtl/openram_testchip_tb.v[diff]

1 file changed

tree: c33f2adf89d4206aff375774f377c80e7a23aed0

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.