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foss-eda-tools/third_party/shuttle/sky130/mpw-002/slot-009/2f90459f2165a7fa4bfa6e6dfa30be2d45ef6728^1..2f90459f2165a7fa4bfa6e6dfa30be2d45ef6728/.
commit
2f90459f2165a7fa4bfa6e6dfa30be2d45ef6728
[log] [tgz]
author
mrg <mrg@ucsc.edu>
Mon Jun 28 15:26:21 2021 -0700
committer
mrg <mrg@ucsc.edu>
Mon Jun 28 15:26:21 2021 -0700
tree
2a42486ea4ae3e98ed169a146f032dea2b12c79f
parent
91509504fd6bf679c81b930fe62b2f5701754fc6 [diff]
parent
201fac945ad43a38a2c925819151d54340d173a9 [diff]
Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main

diff --git a/verilog/dv/la_test/la_test.c b/verilog/dv/la_test/la_test.c
index f7e80af..f72d820 100644
--- a/verilog/dv/la_test/la_test.c
+++ b/verilog/dv/la_test/la_test.c

@@ -20,28 +20,11 @@
 #include "verilog/dv/caravel/stub.c"
 
 /*
-	IO Test:
-		- Configures MPRJ lower 8-IO pins as outputs
-		- Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
+	LA Test:
+		- Reads to and writes from each SRAM
+		- Uses Logic Analyzer interface for communication between SRAMs and CPU
 */
 
-
-   /* wire     la_clk = la_data_in[127]; */
-   /* wire     la_reset = la_data_in[126]; */
-   /* wire     la_in_load = la_data_in[125]; */
-   /* wire     la_sram_load = la_data_in[124]; */
-   /* wire     la_global_cs = la_data_in[123]; */
-/* * chip_select (4) */
-/* * addr0 (16) */
-/* * din0 (32) */
-/* * csb0 (1) */
-/* * web0 (1) */
-/* * wmask0 (1) */
-/* * addr1 (16) */
-/* * din1 (32) */
-/* * csb1 (1) */
-/* * web1 (1) */
-/* * wmask1 (4) */
 typedef struct bit_fields {
 
   unsigned int clk : 1;
@@ -84,488 +67,69 @@
 int clk = 0;
 int i;
 
-void main()
-{
-	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
-                                        // connect to housekeeping SPI
-
-	// This is to signal when the code is ready to the test bench
-	reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-	/* Apply configuration */
-	reg_mprj_xfer = 1;
-	while (reg_mprj_xfer == 1);
-
+void write_dp_sram(int sel) {
 	// Configure LA probes as outputs from the cpu
 	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]
 	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
 	reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
 	reg_la3_oenb = reg_la3_iena = 0x00000000;    // [127:96]
-	
-	// To start, set pin 0 to 1
-	reg_mprj_datal = 0x00000001;
-	/*
-	union packet p;
-	p.bf.rst = 1;
-	p.bf.clk = 1;
-	p.bf.in_load = 1;
-	p.bf.sram_load = 0;
-	p.bf.la_gcs = 0;
-	
-	p.bf.unused = 0;
 
-	p.bf.cs = 0;
-	p.bf.addr0 = 0;
-	p.bf.din0 = 1;
-	p.bf.csb0 = 0;
-	p.bf.web0 = 0;
-	p.bf.wmask0 = 15;
-
-	p.bf.addr1 = 0;
-	p.bf.din1 = 0;
-	p.bf.csb1 = 1;
-	p.bf.web1 = 1;
-	p.bf.wmask1 = 0;
-
-	//Send data
-	reg_la3_data = p.wf.word3;
-	reg_la2_data = p.wf.word2;
-	reg_la1_data = p.wf.word1;
-	reg_la0_data = p.wf.word0;
-	*/
-
-	/* DUAL PORT MEMORIES */
-
-	//SRAM 0
 	// Write 1 to address 1
 	// Send input packet
-	reg_la3_data = 0xA0000000;
+	reg_la3_data = 0xA0000000 | sel << 12;
 	reg_la2_data = 0x10000000;
 	reg_la1_data = 0x13C00000;
 	reg_la0_data = 0x00000030;
 
 	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20000000;
-	reg_la3_data = 0xA0000000;
+	reg_la3_data = 0x20000000 | sel << 12;
+	reg_la3_data = 0xA0000000 | sel << 12;
 	
 	// Toggle clock to write SRAM
-	reg_la3_data = 0x08000000;
-	reg_la3_data = 0x80000000;
+	reg_la3_data = 0x08000000 | sel << 12;
+	reg_la3_data = 0x80000000 | sel << 12;
 
 	// Write 2 to address 2
 	// Send input packet
-	reg_la3_data = 0xA0000000;
+	reg_la3_data = 0xA0000000 | sel << 12;
 	reg_la2_data = 0x20000000;
 	reg_la1_data = 0x23C00000;
 	reg_la0_data = 0x00000030;
 
 	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20000000;
-	reg_la3_data = 0xA0000000;
+	reg_la3_data = 0x20000000 | sel << 12;
+	reg_la3_data = 0xA0000000 | sel << 12;
 	
 	// Toggle clock to write SRAM
-	reg_la3_data = 0x08000000;
-	reg_la3_data = 0x80000000;
+	reg_la3_data = 0x08000000 | sel << 12;
+	reg_la3_data = 0x80000000 | sel << 12;
+}
 
+void read_dp_sram(int sel){
 	// Read back data
 	// Send input packet
-	reg_la3_data = 0xA0000000;
+	reg_la3_data = 0xA0000000 | sel << 12;
 	reg_la2_data = 0x20000000;
 	reg_la1_data = 0x04000040;
 	reg_la0_data = 0x00000010;
 
 	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20000000;
-	reg_la3_data = 0xA0000000;
+	reg_la3_data = 0x20000000 | sel << 12;
+	reg_la3_data = 0xA0000000 | sel << 12;
 	
 	// Toggle clock to read SRAM
-	reg_la3_data = 0x08000000;
-	reg_la3_data = 0x80000000;
+	reg_la3_data = 0x08000000 | sel << 12;
+	reg_la3_data = 0x80000000 | sel << 12;
 
 	// Toggle clock to store into dout FF
-	reg_la3_data = 0x00000000;
-	reg_la3_data = 0x80000000;
+	reg_la3_data = 0x00000000 | sel << 12;
+	reg_la3_data = 0x80000000 | sel << 12;
 
 	// Toggle clock to replace din with dout
-	reg_la3_data = 0x10000000;
-	reg_la3_data = 0x90000000;
+	reg_la3_data = 0x10000000 | sel << 12;
+	reg_la3_data = 0x90000000 | sel << 12;
 
-	//SRAM 1
-	// Write 1 to address 1
-	// Send input packet
-	reg_la3_data = 0xA0001000;
-	reg_la2_data = 0x10000000;
-	reg_la1_data = 0x13C00000;
-	reg_la0_data = 0x00000030;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20001000;
-	reg_la3_data = 0xA0001000;
-	
-	// Toggle clock to write SRAM
-	reg_la3_data = 0x08001000;
-	reg_la3_data = 0x80001000;
-
-	// Write 2 to address 2
-	// Send input packet
-	reg_la3_data = 0xA0001000;
-	reg_la2_data = 0x20000000;
-	reg_la1_data = 0x23C00000;
-	reg_la0_data = 0x00000030;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20001000;
-	reg_la3_data = 0xA0001000;
-	
-	// Toggle clock to write SRAM
-	reg_la3_data = 0x08001000;
-	reg_la3_data = 0x80001000;
-
-	// Read back data
-	// Send input packet
-	reg_la3_data = 0xA0001000;
-	reg_la2_data = 0x20000000;
-	reg_la1_data = 0x04000040;
-	reg_la0_data = 0x00000010;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20001000;
-	reg_la3_data = 0xA0001000;
-	
-	// Toggle clock to read SRAM
-	reg_la3_data = 0x08001000;
-	reg_la3_data = 0x80001000;
-
-	// Toggle clock to store into dout FF
-	reg_la3_data = 0x00001000;
-	reg_la3_data = 0x80001000;
-
-	// Toggle clock to replace din with dout
-	reg_la3_data = 0x100001000;
-	reg_la3_data = 0x900001000;
-
-	// SRAM 2
-	// Write 1 to address 1
-	// Send input packet
-	reg_la3_data = 0xA0002000;
-	reg_la2_data = 0x10000000;
-	reg_la1_data = 0x13C00000;
-	reg_la0_data = 0x00000030;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20002000;
-	reg_la3_data = 0xA0002000;
-	
-	// Toggle clock to write SRAM
-	reg_la3_data = 0x08002000;
-	reg_la3_data = 0x80002000;
-
-	// Write 2 to address 2
-	// Send input packet
-	reg_la3_data = 0xA0002000;
-	reg_la2_data = 0x20000000;
-	reg_la1_data = 0x23C00000;
-	reg_la0_data = 0x00000030;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20002000;
-	reg_la3_data = 0xA0002000;
-	
-	// Toggle clock to write SRAM
-	reg_la3_data = 0x08002000;
-	reg_la3_data = 0x80002000;
-
-	// Read back data
-	// Send input packet
-	reg_la3_data = 0xA0002000;
-	reg_la2_data = 0x20000000;
-	reg_la1_data = 0x04000040;
-	reg_la0_data = 0x00000010;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20002000;
-	reg_la3_data = 0xA0002000;
-	
-	// Toggle clock to read SRAM
-	reg_la3_data = 0x08002000;
-	reg_la3_data = 0x80002000;
-
-	// Toggle clock to store into dout FF
-	reg_la3_data = 0x00002000;
-	reg_la3_data = 0x80002000;
-
-	// Toggle clock to replace din with dout
-	reg_la3_data = 0x100002000;
-	reg_la3_data = 0x900002000;
-
-	// SRAM 3
-	// Write 1 to address 1
-	// Send input packet
-	reg_la3_data = 0xA0003000;
-	reg_la2_data = 0x10000000;
-	reg_la1_data = 0x13C00000;
-	reg_la0_data = 0x00000030;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20003000;
-	reg_la3_data = 0xA0003000;
-	
-	// Toggle clock to write SRAM
-	reg_la3_data = 0x08003000;
-	reg_la3_data = 0x80003000;
-
-	// Write 2 to address 2
-	// Send input packet
-	reg_la3_data = 0xA0003000;
-	reg_la2_data = 0x20000000;
-	reg_la1_data = 0x23C00000;
-	reg_la0_data = 0x00000030;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20003000;
-	reg_la3_data = 0xA0003000;
-	
-	// Toggle clock to write SRAM
-	reg_la3_data = 0x08003000;
-	reg_la3_data = 0x80003000;
-
-	// Read back data
-	// Send input packet
-	reg_la3_data = 0xA0003000;
-	reg_la2_data = 0x20000000;
-	reg_la1_data = 0x04000040;
-	reg_la0_data = 0x00000010;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20003000;
-	reg_la3_data = 0xA0003000;
-	
-	// Toggle clock to read SRAM
-	reg_la3_data = 0x08003000;
-	reg_la3_data = 0x80003000;
-
-	// Toggle clock to store into dout FF
-	reg_la3_data = 0x00003000;
-	reg_la3_data = 0x80003000;
-
-	// Toggle clock to replace din with dout
-	reg_la3_data = 0x100003000;
-	reg_la3_data = 0x900003000;
-
-	// SRAM 4
-	// Write 1 to address 1
-	// Send input packet
-	reg_la3_data = 0xA0004000;
-	reg_la2_data = 0x10000000;
-	reg_la1_data = 0x13C00000;
-	reg_la0_data = 0x00000030;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20004000;
-	reg_la3_data = 0xA0004000;
-	
-	// Toggle clock to write SRAM
-	reg_la3_data = 0x08004000;
-	reg_la3_data = 0x80004000;
-
-	// Write 2 to address 2
-	// Send input packet
-	reg_la3_data = 0xA0004000;
-	reg_la2_data = 0x20000000;
-	reg_la1_data = 0x23C00000;
-	reg_la0_data = 0x00000030;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20004000;
-	reg_la3_data = 0xA0004000;
-	
-	// Toggle clock to write SRAM
-	reg_la3_data = 0x08004000;
-	reg_la3_data = 0x80004000;
-
-	// Read back data
-	// Send input packet
-	reg_la3_data = 0xA0004000;
-	reg_la2_data = 0x20000000;
-	reg_la1_data = 0x04000040;
-	reg_la0_data = 0x00000010;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20004000;
-	reg_la3_data = 0xA0004000;
-	
-	// Toggle clock to read SRAM
-	reg_la3_data = 0x08004000;
-	reg_la3_data = 0x80004000;
-
-	// Toggle clock to store into dout FF
-	reg_la3_data = 0x00004000;
-	reg_la3_data = 0x80004000;
-
-	// Toggle clock to replace din with dout
-	reg_la3_data = 0x100004000;
-	reg_la3_data = 0x900004000;
-
-	/* SINGLE PORT MEMORIES */
-	
-	// SRAM 8
-	// Write DEADBEEF to address 1
-	// Send input packet
-	reg_la3_data = 0xA0008000;
-	reg_la2_data = 0x1DEADBEE;
-	reg_la1_data = 0xF3C00000;
-	reg_la0_data = 0x00000000;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20008000;
-	reg_la3_data = 0xA0008000;
-	
-	// Toggle clock to write SRAM
-	reg_la3_data = 0x08008000;
-	reg_la3_data = 0x80008000;
-
-	// Read back data
-	// Send input packet
-	reg_la3_data = 0xA0008000;
-	reg_la2_data = 0x10000000;
-	reg_la1_data = 0x04000000;
-	reg_la0_data = 0x00000000;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20008000;
-	reg_la3_data = 0xA0008000;
-	
-	// Toggle clock to read SRAM
-	reg_la3_data = 0x08008000;
-	reg_la3_data = 0x80008000;
-
-	// Toggle clock to store into dout FF
-	reg_la3_data = 0x00008000;
-	reg_la3_data = 0x80008000;
-
-	// Toggle clock to replace din with dout
-	reg_la3_data = 0x100008000;
-	reg_la3_data = 0x900008000;
-
-	// SRAM 9
-	// Write DEADBEEF to address 1
-	// Send input packet
-	reg_la3_data = 0xA0009000;
-	reg_la2_data = 0x1DEADBEE;
-	reg_la1_data = 0xF3C00000;
-	reg_la0_data = 0x00000000;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20009000;
-	reg_la3_data = 0xA0009000;
-	
-	// Toggle clock to write SRAM
-	reg_la3_data = 0x08009000;
-	reg_la3_data = 0x80009000;
-
-	// Read back data
-	// Send input packet
-	reg_la3_data = 0xA0009000;
-	reg_la2_data = 0x10000000;
-	reg_la1_data = 0x04000000;
-	reg_la0_data = 0x00000000;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x20009000;
-	reg_la3_data = 0xA0009000;
-	
-	// Toggle clock to read SRAM
-	reg_la3_data = 0x08009000;
-	reg_la3_data = 0x80009000;
-
-	// Toggle clock to store into dout FF
-	reg_la3_data = 0x00009000;
-	reg_la3_data = 0x80009000;
-
-	// Toggle clock to replace din with dout
-	reg_la3_data = 0x100009000;
-	reg_la3_data = 0x900009000;
-
-	// SRAM 10
-	// Write DEADBEEF to address 1
-	// Send input packet
-	reg_la3_data = 0xA000A000;
-	reg_la2_data = 0x1DEADBEE;
-	reg_la1_data = 0xF3C00000;
-	reg_la0_data = 0x00000000;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x2000A000;
-	reg_la3_data = 0xA000A000;
-	
-	// Toggle clock to write SRAM
-	reg_la3_data = 0x0800A000;
-	reg_la3_data = 0x8000A000;
-
-	// Read back data
-	// Send input packet
-	reg_la3_data = 0xA000A000;
-	reg_la2_data = 0x10000000;
-	reg_la1_data = 0x04000000;
-	reg_la0_data = 0x00000000;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x2000A000;
-	reg_la3_data = 0xA000A000;
-	
-	// Toggle clock to read SRAM
-	reg_la3_data = 0x0800A000;
-	reg_la3_data = 0x8000A000;
-
-	// Toggle clock to store into dout FF
-	reg_la3_data = 0x0000A000;
-	reg_la3_data = 0x8000A000;
-
-	// Toggle clock to replace din with dout
-	reg_la3_data = 0x10000A000;
-	reg_la3_data = 0x90000A000;
-
-	// SRAM 11
-	// Write DEADBEEF to address 1
-	// Send input packet
-	reg_la3_data = 0xA000B000;
-	reg_la2_data = 0x1DEADBEE;
-	reg_la1_data = 0xF3C00000;
-	reg_la0_data = 0x00000000;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x2000B000;
-	reg_la3_data = 0xA000B000;
-	
-	// Toggle clock to write SRAM
-	reg_la3_data = 0x0800B000;
-	reg_la3_data = 0x8000B000;
-
-	// Read back data
-	// Send input packet
-	reg_la3_data = 0xA000B000;
-	reg_la2_data = 0x10000000;
-	reg_la1_data = 0x04000000;
-	reg_la0_data = 0x00000000;
-
-	// Toggle clock to load into SRAM register
-	reg_la3_data = 0x2000B000;
-	reg_la3_data = 0xA000B000;
-	
-	// Toggle clock to read SRAM
-	reg_la3_data = 0x0800B000;
-	reg_la3_data = 0x8000B000;
-
-	// Toggle clock to store into dout FF
-	reg_la3_data = 0x0000B000;
-	reg_la3_data = 0x8000B000;
-
-	// Toggle clock to replace din with dout
-	reg_la3_data = 0x10000B000;
-	reg_la3_data = 0x90000B000;
-
-	/*
-	// This is how to read from the LA
+	// Read from the LA
 	// This will trigger a sample of the LA bits to read
 	// Configure LA probes as outputs from the cpu
 	reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0]
@@ -575,12 +139,138 @@
 	
 	reg_la_sample = 1;
 	// Now read them
-
-	if(reg_la0_data == 0x00000050){
-		print("Passed!\n");
+	if(reg_la0_data != 0x00000050){
+		reg_mprj_datal = 0x00000001 | 1 << (sel + 1);
 	}
-	*/
-	print("Done with tests\n");
+}
+
+void write_sp_sram(int sel) {
+	// Configure LA probes as outputs from the cpu
+	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]
+	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0x00000000;    // [127:96]
+
+	// Write DEADBEEF to address 1
+	// Send input packet
+	reg_la3_data = 0xA0000000 | sel << 12;
+	reg_la2_data = 0x1DEADBEE;
+	reg_la1_data = 0xF3C00000;
+	reg_la0_data = 0x00000000;
+
+	// Toggle clock to load into SRAM register
+	reg_la3_data = 0x20000000 | sel << 12;
+	reg_la3_data = 0xA0000000 | sel << 12;
+	
+	// Toggle clock to write SRAM
+	reg_la3_data = 0x08000000 | sel << 12;
+	reg_la3_data = 0x80000000 | sel << 12;
+}
+
+void read_sp_sram(int sel){
+	// Read back data
+	// Send input packet
+	reg_la3_data = 0xA0000000 | sel << 12;
+	reg_la2_data = 0x10000000;
+	reg_la1_data = 0x04000000;
+	reg_la0_data = 0x00000000;
+
+	// Toggle clock to load into SRAM register
+	reg_la3_data = 0x20000000 | sel << 12;
+	reg_la3_data = 0xA0000000 | sel << 12;
+	
+	// Toggle clock to read SRAM
+	reg_la3_data = 0x08000000 | sel << 12;
+	reg_la3_data = 0x80000000 | sel << 12;
+
+	// Toggle clock to store into dout FF
+	reg_la3_data = 0x00000000 | sel << 12;
+	reg_la3_data = 0x80000000 | sel << 12;
+
+	// Toggle clock to replace din with dout
+	reg_la3_data = 0x10000000 | sel << 12;
+	reg_la3_data = 0x90000000 | sel << 12;
+
+	// Read from the LA
+	// This will trigger a sample of the LA bits to read
+	// Configure LA probes as outputs from the cpu
+	reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0]
+	reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
+	
+	reg_la_sample = 1;
+	// Now read them
+	if(reg_la2_data != 0x1DEADBEE){
+		reg_mprj_datal = 0x00000001 | 1 << (sel - 2);
+	}
+}
+
+
+void main()
+{
+	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// This is to signal when the code is ready to the test bench
+	reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+ 
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+	
+	// To start, set pin 0 to 1
+	reg_mprj_datal = 0x00000001;
+
+	/* DUAL PORT MEMORIES */
+
+	//SRAM 0
+	write_dp_sram(0);
+	read_dp_sram(0);
+
+	//SRAM 1
+	write_dp_sram(1);
+	read_dp_sram(1);
+
+	// SRAM 2
+	write_dp_sram(2);
+	read_dp_sram(2);
+	
+	// SRAM 3
+	write_dp_sram(3);
+	read_dp_sram(3);
+
+	// SRAM 4
+	write_dp_sram(4);
+	read_dp_sram(4);
+	
+	/* SINGLE PORT MEMORIES */
+	
+	// SRAM 8
+	write_sp_sram(8);
+	read_sp_sram(8);
+	
+	// SRAM 9
+	write_sp_sram(9);
+	read_sp_sram(9);
+
+	// SRAM 10
+	write_sp_sram(10);
+	read_sp_sram(10);
+
+	// SRAM 11
+	write_sp_sram(11);
+	read_sp_sram(11);
+
 	// On end, set pin 0 to 0
 	reg_mprj_datal = 0x00000000;
 }

diff --git a/verilog/dv/la_test/la_test_tb.v b/verilog/dv/la_test/la_test_tb.v
index 5b1ad56..a4ab56e 100644
--- a/verilog/dv/la_test/la_test_tb.v
+++ b/verilog/dv/la_test/la_test_tb.v

@@ -32,6 +32,14 @@
 	wire [37:0] mprj_io;
 	wire mprj_io_0 = mprj_io[0];
 	wire mprj_io_1 = mprj_io[1];
+	wire mprj_io_2 = mprj_io[2];
+	wire mprj_io_3 = mprj_io[3];
+	wire mprj_io_4 = mprj_io[4];
+	wire mprj_io_5 = mprj_io[5];
+	wire mprj_io_6 = mprj_io[6];
+	wire mprj_io_7 = mprj_io[7];
+	wire mprj_io_8 = mprj_io[8];
+	wire mprj_io_9 = mprj_io[9];
 
 	// External clock is used by default.  Make this artificially fast for the
 	// simulation.  Normally this would be a slow clock and the digital PLL
@@ -68,17 +76,56 @@
 
 		wait(mprj_io_0 == 1'b0);
 		$display($time, " Saw bit 0: VCD stopping");
-		
+		$display("Done with tests");
 		$finish;
 
 	end // initial begin
 	
 	initial begin
-		repeat (9) begin
-			wait (mprj_io_1 == 1'b1);
-			$display($time, " Read byte correctly using logic analyzer!");
-		end
+		wait (mprj_io_1 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 0!"); $finish;
 	end
+	
+	initial begin
+		wait (mprj_io_2 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 1!"); $finish;
+	end
+		
+	initial begin 
+		wait (mprj_io_3 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 2!"); $finish;
+	end
+
+	initial begin
+		wait (mprj_io_4 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 3!"); $finish;
+	end
+
+	initial begin
+		wait (mprj_io_5 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 4!"); $finish;
+	end
+
+	initial begin
+		wait (mprj_io_6 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 8!"); $finish;
+	end
+
+	initial begin
+		wait (mprj_io_7 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 9!"); $finish;
+	end
+
+	initial begin
+		wait (mprj_io_8 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 10!"); $finish;
+	end
+
+	initial begin
+		wait (mprj_io_9 == 1'b1);
+		$display($time, " Data mismatch while reading byte from SRAM 11!"); $finish;
+	end
+
    initial begin
       //$dumpfile("foo.vcd");
       //$dumpvars(0, la_test_tb);