Debug user_project_wrapper verilog
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index e224270..f40c1d4 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -43,6 +43,10 @@
set ::env(VERILOG_FILES_BLACKBOX) "\
$script_dir/../../caravel/verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v \
+ $script_dir/../../verilog/rtl/sky130_sram_1kbyte_1rw1r_8x1024_8.v \
+ $script_dir/../../verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+ $script_dir/../../verilog/rtl/sky130_sram_4kbyte_1rw1r_32x1024_8.v \
+ $script_dir/../../verilog/rtl/sky130_sram_8kbyte_1rw1r_32x2048_8.v \
$script_dir/../../verilog/rtl/sram_1rw0r0w_32_1024_sky130.v \
$script_dir/../../verilog/rtl/sram_1rw0r0w_32_256_sky130.v \
$script_dir/../../verilog/rtl/sram_1rw0r0w_32_512_sky130.v \
@@ -51,6 +55,10 @@
set ::env(EXTRA_LEFS) "\
$script_dir/../../lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef \
+ $script_dir/../../lef/sky130_sram_1kbyte_1rw1r_8x1024_8.lef \
+ $script_dir/../../lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
+ $script_dir/../../lef/sky130_sram_4kbyte_1rw1r_32x1024_8.lef \
+ $script_dir/../../lef/sky130_sram_8kbyte_1rw1r_32x2048_8.lef \
$script_dir/../../lef/sram_1rw0r0w_32_1024_sky130.lef \
$script_dir/../../lef/sram_1rw0r0w_32_256_sky130.lef \
$script_dir/../../lef/sram_1rw0r0w_32_512_sky130.lef \
@@ -59,6 +67,10 @@
set ::env(EXTRA_GDS_FILES) "\
$script_dir/../../gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds \
+ $script_dir/../../gds/sky130_sram_1kbyte_1rw1r_8x1024_8.gds \
+ $script_dir/../../gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
+ $script_dir/../../gds/sky130_sram_4kbyte_1rw1r_32x1024_8.gds \
+ $script_dir/../../gds/sky130_sram_8kbyte_1rw1r_32x2048_8.gds \
$script_dir/../../gds/sram_1rw0r0w_32_1024_sky130.gds \
$script_dir/../../gds/sram_1rw0r0w_32_256_sky130.gds \
$script_dir/../../gds/sram_1rw0r0w_32_512_sky130.gds \
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index dcfff1a..906abc8 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -38,14 +38,14 @@
# sram_1rw0r0w_32_512_sky130
# 476 x 320
-SRAM10 1300 1200
+SRAM10 1300 1200 N
# sram_1rw0r0w_32_1024_sky130
# 801 x 348
-SRAM9 1300 1500
+SRAM9 1300 1500 N
# sram_1rw0r0w_64_512_sky130
# 823 x 335
-SRAM8 1300 2300
+SRAM8 1300 2300 N
CONTROL_LOGIC 1300 100 N
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 6f123dc..a58195e 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -144,17 +144,24 @@
.gpio_out(io_out[21]),
// Shared control/data to the SRAMs
- .addr0(addr0),
- .din0(din0),
- .web0(web0),
- .wmask0(wmask0),
- .addr1(addr1),
- .web1(web1),
- .wmask1(wmask1),
-
+ .left_addr0(addr0),
+ .left_din0(din0),
+ .left_web0(web0),
+ .left_wmask0(wmask0),
+ .left_addr1(addr1),
+ .left_web1(web1),
+ .left_wmask1(wmask1),
// One CSB for each SRAM
- .csb0(csb0)
- .csb1(csb1)
+ .left_csb0(csb0),
+ .left_csb1(csb1),
+
+ // Shared control/data to the SRAMs
+ .right_addr0(addr0),
+ .right_din0(din0),
+ .right_web0(web0),
+ .right_wmask0(wmask0),
+ // One CSB for each SRAM
+ .right_csb0(csb0),
// Clocks for each SRAM
.sram0_clk(sram0_clk),
@@ -211,52 +218,58 @@
);
- wire [31:0] din0;
- wire web0;
- wire [3:0] wmask0;
- wire [15:0] addr1;
- wire [31:0] din1;
- wire web1;
- wire [3:0] wmask1;
+ wire [`ADDR_SIZE-1:0] left_addr0;
+ wire [`DATA_SIZE-1:0] left_din0;
+ wire left_web0;
+ wire [`WMASK_SIZE-1:0] left_wmask0;
+ wire [`ADDR_SIZE-1:0] left_addr1;
+ wire [`DATA_SIZE-1:0] left_din1;
+ wire left_web1;
+ wire [`WMASK_SIZE-1:0] left_wmask1;
+ wire [`MAX_CHIPS-1:0] left_csb0;
+ wire [`MAX_CHIPS-1:0] left_csb1;
- wire [15:0] csb0;
- wire [15:0] csb1;
-
- wire [31:0] sram0_dout0;
- wire [31:0] sram0_dout1;
- wire [31:0] sram1_dout0;
- wire [31:0] sram1_dout1;
- wire [31:0] sram2_dout0;
- wire [31:0] sram2_dout1;
- wire [31:0] sram3_dout0;
- wire [31:0] sram3_dout1;
- wire [31:0] sram4_dout0;
- wire [31:0] sram4_dout1;
- wire [31:0] sram5_dout0;
- wire [31:0] sram5_dout1;
- wire [31:0] sram6_dout0;
- wire [31:0] sram6_dout1;
- wire [31:0] sram7_dout0;
- wire [31:0] sram7_dout1;
- wire [31:0] sram8_dout0;
- wire [31:0] sram8_dout1;
- wire [31:0] sram9_dout0;
- wire [31:0] sram9_dout1;
- wire [31:0] sram10_dout0;
- wire [31:0] sram10_dout1;
- wire [31:0] sram11_dout0;
- wire [31:0] sram11_dout1;
- wire [31:0] sram12_dout0;
- wire [31:0] sram12_dout1;
- wire [31:0] sram13_dout0;
- wire [31:0] sram13_dout1;
- wire [31:0] sram14_dout0;
- wire [31:0] sram14_dout1;
- wire [31:0] sram15_dout0;
- wire [31:0] sram15_dout1;
+ wire [`ADDR_SIZE-1:0] right_addr0;
+ wire [`DATA_SIZE-1:0] right_din0;
+ wire right_web0;
+ wire [`WMASK_SIZE-1:0] right_wmask0;
+ wire [`MAX_CHIPS-1:0] right_csb0;
+
+ wire [`DATA_SIZE-1:0] sram0_dout0;
+ wire [`DATA_SIZE-1:0] sram0_dout1;
+ wire [`DATA_SIZE-1:0] sram1_dout0;
+ wire [`DATA_SIZE-1:0] sram1_dout1;
+ wire [`DATA_SIZE-1:0] sram2_dout0;
+ wire [`DATA_SIZE-1:0] sram2_dout1;
+ wire [`DATA_SIZE-1:0] sram3_dout0;
+ wire [`DATA_SIZE-1:0] sram3_dout1;
+ wire [`DATA_SIZE-1:0] sram4_dout0;
+ wire [`DATA_SIZE-1:0] sram4_dout1;
+ wire [`DATA_SIZE-1:0] sram5_dout0;
+ wire [`DATA_SIZE-1:0] sram5_dout1;
+ wire [`DATA_SIZE-1:0] sram6_dout0;
+ wire [`DATA_SIZE-1:0] sram6_dout1;
+ wire [`DATA_SIZE-1:0] sram7_dout0;
+ wire [`DATA_SIZE-1:0] sram7_dout1;
+ wire [`DATA_SIZE-1:0] sram8_dout0;
+ wire [`DATA_SIZE-1:0] sram8_dout1;
+ wire [`DATA_SIZE-1:0] sram9_dout0;
+ wire [`DATA_SIZE-1:0] sram9_dout1;
+ wire [`DATA_SIZE-1:0] sram10_dout0;
+ wire [`DATA_SIZE-1:0] sram10_dout1;
+ wire [`DATA_SIZE-1:0] sram11_dout0;
+ wire [`DATA_SIZE-1:0] sram11_dout1;
+ wire [`DATA_SIZE-1:0] sram12_dout0;
+ wire [`DATA_SIZE-1:0] sram12_dout1;
+ wire [`DATA_SIZE-1:0] sram13_dout0;
+ wire [`DATA_SIZE-1:0] sram13_dout1;
+ wire [`DATA_SIZE-1:0] sram14_dout0;
+ wire [`DATA_SIZE-1:0] sram14_dout1;
+ wire [`DATA_SIZE-1:0] sram15_dout0;
+ wire [`DATA_SIZE-1:0] sram15_dout1;
// Only io_out[27] is output
- assgin io_oeb = 1'b1 << 21;
+ assign io_oeb = 1'b1 << 21;
sky130_sram_1kbyte_1rw1r_8x1024_8 SRAM0
(
@@ -265,19 +278,19 @@
.vssd1(vssd1),
`endif
.clk0 (sram0_clk),
- .csb0 (csb0[0]),
- .web0 (web0),
- .wmask0 (wmask0),
- .addr0 (addr0),
- .din0 (din0),
+ .csb0 (left_csb0[0]),
+ .web0 (left_web0),
+ .wmask0 (left_wmask0),
+ .addr0 (left_addr0),
+ .din0 (left_din0),
.dout0 (sram0_dout0[7:0]),
.clk1 (sram0_clk),
- .csb1 (csb1[0]),
- .addr1 (addr0),
+ .csb1 (left_csb1[0]),
+ .addr1 (left_addr0),
.dout1 (sram0_dout1[7:0])
);
- assign sram0_dout0[31:8] = 0;
- assign sram0_dout1[31:8] = 0;
+ assign sram0_dout0[`DATA_SIZE-1:8] = 0;
+ assign sram0_dout1[`DATA_SIZE-1:8] = 0;
sky130_sram_1kbyte_1rw1r_32x256_8 SRAM1
(
@@ -286,34 +299,34 @@
.vssd1(vssd1),
`endif
.clk0 (sram1_clk),
- .csb0 (csb0[1]),
- .web0 (web0),
- .wmask0 (wmask0),
- .addr0 (addr0),
- .din0 (din0),
+ .csb0 (left_csb0[1]),
+ .web0 (left_web0),
+ .wmask0 (left_wmask0),
+ .addr0 (left_addr0),
+ .din0 (left_din0),
.dout0 (sram1_dout0),
.clk1 (sram1_clk),
- .csb1 (csb1[1]),
- .addr1 (addr1),
+ .csb1 (left_csb1[1]),
+ .addr1 (left_addr1),
.dout1 (sram1_dout1)
);
sky130_sram_2kbyte_1rw1r_32x512_8 SRAM2
- (p
+ (
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
.clk0 (sram2_clk),
- .csb0 (csb0[2]),
- .web0 (web0),
- .wmask0 (wmask0),
- .addr0 (addr0),
- .din0 (din0),
+ .csb0 (left_csb0[2]),
+ .web0 (left_web0),
+ .wmask0 (left_wmask0),
+ .addr0 (left_addr0),
+ .din0 (left_din0),
.dout0 (sram2_dout0),
.clk1 (sram2_clk),
- .csb1 (csb1[2]),
- .addr1 (addr1),
+ .csb1 (left_csb1[2]),
+ .addr1 (left_addr1),
.dout1 (sram2_dout1)
);
@@ -324,15 +337,15 @@
.vssd1(vssd1),
`endif
.clk0 (sram3_clk),
- .csb0 (csb0[3]),
- .web0 (web0),
- .wmask0 (wmask0),
- .addr0 (addr0),
- .din0 (din0),
+ .csb0 (left_csb0[3]),
+ .web0 (left_web0),
+ .wmask0 (left_wmask0),
+ .addr0 (left_addr0),
+ .din0 (left_din0),
.dout0 (sram3_dout0),
.clk1 (sram3_clk),
- .csb1 (csb1[3]),
- .addr1 (addr1),
+ .csb1 (left_csb1[3]),
+ .addr1 (left_addr1),
.dout1 (sram3_dout1)
);
@@ -343,15 +356,15 @@
.vssd1(vssd1),
`endif
.clk0 (sram4_clk),
- .csb0 (csb0[4]),
- .web0 (web0),
- .wmask0 (wmask0),
- .addr0 (addr0),
- .din0 (din0),
+ .csb0 (left_csb0[4]),
+ .web0 (left_web0),
+ .wmask0 (left_wmask0),
+ .addr0 (left_addr0),
+ .din0 (left_din0),
.dout0 (sram4_dout0),
.clk1 (sram4_clk),
- .csb1 (csb1[4]),
- .addr1 (addr1),
+ .csb1 (left_csb1[4]),
+ .addr1 (left_addr1),
.dout1 (sram4_dout1)
);
@@ -385,11 +398,11 @@
.vssd1(vssd1),
`endif
.clk0 (sram8_clk),
- .csb0 (csb0[8]),
- .web0 (web0),
- .wmask0 (wmask0),
- .addr0 (addr0),
- .din0 (din0),
+ .csb0 (right_csb0[8]),
+ .web0 (right_web0),
+ .wmask0 (right_wmask0),
+ .addr0 (right_addr0),
+ .din0 (right_din0),
.dout0 (sram8_dout0)
);
assign sram8_dout1 = 0;
@@ -401,11 +414,11 @@
.vssd1(vssd1),
`endif
.clk0 (sram9_clk),
- .csb0 (csb0[9]),
- .web0 (web0),
- .wmask0 (wmask0),
- .addr0 (addr0),
- .din0 (din0),
+ .csb0 (right_csb0[9]),
+ .web0 (right_web0),
+ .wmask0 (right_wmask0),
+ .addr0 (right_addr0),
+ .din0 (right_din0),
.dout0 (sram9_dout0)
);
assign sram9_dout1 = 0;
@@ -417,11 +430,11 @@
.vssd1(vssd1),
`endif
.clk0 (sram10_clk),
- .csb0 (csb0[10]),
- .web0 (web0),
- .wmask0 (wmask0),
- .addr0 (addr0),
- .din0 (din0),
+ .csb0 (right_csb0[10]),
+ .web0 (right_web0),
+ .wmask0 (right_wmask0),
+ .addr0 (right_addr0),
+ .din0 (right_din0),
.dout0 (sram10_dout0)
);
assign sram10_dout1 = 0;
@@ -433,14 +446,18 @@
.vssd1(vssd1),
`endif
.clk0 (sram11_clk),
- .csb0 (csb0[11]),
- .web0 (web0),
- .wmask0 (wmask0),
- .addr0 (addr0),
- .din0 (din0),
- .dout0 (sram11_dout0)
+ .csb0 (right_csb0[11]),
+ .web0 (right_web0),
+ .wmask0 (right_wmask0),
+ .addr0 (right_addr0),
+ .din0 ({right_din0[31:16], 32'd0, right_din0[15:0]}),
+ .dout0 (temp_sram11_dout0)
);
+
+ wire [`DATA_SIZE-1:0] temp_sram11_dout0;
assign sram11_dout1 = 0;
+ assign sram11_dout0 = {temp_sram11_dout0[64:33], temp_sram11_dout[15:0]};
+
endmodule // user_project_wrapper
