commit 2cd561f3439bd8d7622dfc7419a64268314ef2e1
author mrg <mrg@ucsc.edu> Mon Jun 14 17:48:36 2021 -0700
committer mrg <mrg@ucsc.edu> Mon Jun 14 17:48:36 2021 -0700
tree 31a5cbb15589e79d557fb39ac69d5b46b028ca23
parent f8348eed1188ff0678845942ef6bcc44df42e5a1

Remove errors in configs

openlane/openram_testchip/config.tcl

diff --git a/openlane/openram_testchip/config.tcl b/openlane/openram_testchip/config.tcl
index 3c81ce3..8195c4f 100644
--- a/openlane/openram_testchip/config.tcl
+++ b/openlane/openram_testchip/config.tcl
@@ -17,11 +17,11 @@
 set ::env(IO_PCT) 0.1
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 2400"
+set ::env(DIE_AREA) "0 0 400 2200"
 set ::env(DESIGN_IS_CORE) 0
 
-set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
-set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
 
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 

openlane/user_project_wrapper/config.tcl

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 4b6844c..b13919b 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -33,7 +33,7 @@
 set ::env(CLOCK_PORT) "la_sram_clk"
 set ::env(CLOCK_NET) "sram_clk"
 
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "20"
 
 ## Internal Macros
 ### Macro Placement
@@ -89,8 +89,8 @@
 
 set ::env(PL_RANDOM_GLB_PLACEMENT) 1
 
-set ::env(GLB_RT_ADJUSTMENT) 0.15
-set ::env(PL_TARGET_DENSITY) 0.35
+set ::env(GLB_RT_ADJUSTMENT) 0.10
+set ::env(PL_TARGET_DENSITY) 0.7
 
 #set ::env(MAGIC_DRC_USE_GDS) 0
 

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5e9e3e5..4d91ad8 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -561,9 +561,24 @@
        // sram14_data1 <= sram14_dout1;
        // sram15_data0 <= sram15_dout0;
        // sram15_data1 <= sram15_dout1;
-   end
+   end // else: !if(in_reset)
 end
    
+   assign sram5_data0 = 0;
+   assign sram5_data1 = 0;
+   assign sram6_data0 = 0;
+   assign sram6_data1 = 0;
+   assign sram7_data0 = 0;
+   assign sram7_data1 = 0;
+   assign sram12_data0 = 0;
+   assign sram12_data1 = 0;
+   assign sram13_data0 = 0;
+   assign sram13_data1 = 0;
+   assign sram14_data0 = 0;
+   assign sram14_data1 = 0;
+   assign sram15_data0 = 0;
+   assign sram15_data1 = 0;
+   
 
 endmodule	// user_project_wrapper