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foss-eda-tools / third_party / shuttle / sky130 / mpw-002 / slot-009 / 2cb8c08befc549e452258011a43859fcc556f21d
commit2cb8c08befc549e452258011a43859fcc556f21d[log] [tgz]
authorAmoghLonkar <alonkar@ucsc.edu>Fri Jun 18 16:32:02 2021 -0700
committerAmoghLonkar <alonkar@ucsc.edu>Fri Jun 18 16:32:02 2021 -0700
tree35fd8412486498dea482d08c5997217aced27d28
parent383e94bc5fdefc1b053cd169e10e1c60530d9882 [diff]
parentbac364dc7becd5e172ea8e4828b7fd6fc959921f [diff]
Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main
tree: 35fd8412486498dea482d08c5997217aced27d28
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. single_port/
  11. spi/
  12. verilog/
  13. caravel
  14. .gitignore
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  16. info.yaml
  17. LICENSE
  18. Makefile
  19. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Overview

This project contains a test chip for several OpenRAM memory configurations. The configurations have varying levels of verification. In particular, it has these sizes:

  • sky130_sram_1kbyte_1rw1r_8x1024_8
  • sky130_sram_1kbyte_1rw1r_32x256_8
  • sky130_sram_2kbyte_1rw1r_32x512_8
  • sky130_sram_4kbyte_1rw1r_32x1024_8
  • sky130_sram_8kbyte_1rw1r_32x2048_8
  • sky130_sram_1kbyte_1rw_32x256_8
  • sky130_sram_2kbyte_1rw_32x512_8
  • sky130_sram_4kbyte_1rw_32x1024_8
  • sky130_sram_4kbyte_1rw_64x512_8

Test Modes

There are two test modes available. Each one inputs an packet that configures the read and write operations of a particular SRAM. The GPIO pin io_in[16] determines whether to use GPIO (1) or LA mode (0).

Test Packet

The test packet is a 112-bit value that has the follow signals and bit size:

  • chip_select (4)
  • addr0 (16)
  • din0 (32)
  • csb0 (1)
  • web0 (1)
  • wmask0 (1)
  • addr1 (16)
  • din1 (32)
  • csb1 (1)
  • web1 (1)
  • wmask1 (4)

During a read operation, the din bits are replaced with the data output bits so that they can be verified.

Note: The 64-bit memory leaves the middle 32-bits as a value of 0 and instead reads/writes the upper and lower 16-bits to reduce the number of packet bits.

GPIO Mode

In GPIO mode, the test packet is scanned in/out with the GPIO pins in 112 cycles. The GPIO pins used are as follows:

  • Test mode select: in_select io_in[16]
  • Scan reset: resetn: io_in[15]
  • Scan clock: gpio_clk io_in[17]
  • Scan enable: gpio_scan io_in[19]
  • Load SRAM result into register: gpio_sram_load io_in[20]
  • CSB for all SRAM: global_csb io_in[21]
  • Scan input: gpio_in io_in[22]
  • Scan output: gpio_out io_out[22]

LA Mode

In LA mode, the test packet is directly written from the output of the 128-bit LA. The top bits of the LA register are used for the control signals during test:

  • Control register clock: la_clk la_data_in[127]
  • Load control register: la_in_load la_data_in[125]
  • Load SRAM result into register: la_sram_load la_data_in[124]
  • CSB for all SRAM: ??