commit 245e98f0ecd2a5a65c668bbc1b9eefa41face456
author AmoghLonkar <alonkar@ucsc.edu> Thu Jun 10 22:40:28 2021 -0700
committer AmoghLonkar <alonkar@ucsc.edu> Thu Jun 10 22:40:28 2021 -0700
tree ad6ef7387639ce399c801a08fc0ae4db409fedb9
parent a44330c3d71af81a2af97ed289894a8f764cc38f

Single clock

verilog/rtl/openram_testchip.v

diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index 6b341fd..e98b7bc 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -9,8 +9,7 @@
       inout vssd1,        // User area 1 digital ground

       inout vssd2,        // User area 2 digital ground

   `endif

-  input         wb_clock,

-  input         gpio_clock,

+  input         clk,

   input         reset,

   input  [85:0] la_packet,

   input         gpio_packet,

@@ -36,7 +35,6 @@
 reg [83:0] input_connection = 84'd0;

 reg [2:0] chip_select;

 

-reg clk;

 reg sram_clk;

 reg web;

 reg csb0;

@@ -46,10 +44,6 @@
 reg[6:0] gpio_counter = 7'd0;

 reg transfer = 1'b0;

 

-always @(*) begin

-    clk = in_select ? gpio_clock : wb_clock;

-end 

-

 always @(gpio_packet, read_data) begin

     if(!transfer && in_select) begin

         transfer <= 1;

verilog/rtl/openram_testchip_tb.v

diff --git a/verilog/rtl/openram_testchip_tb.v b/verilog/rtl/openram_testchip_tb.v
index ca4c7f2..6a6e07c 100644
--- a/verilog/rtl/openram_testchip_tb.v
+++ b/verilog/rtl/openram_testchip_tb.v
@@ -41,8 +41,7 @@
 wire to_gpio;

 

 openram_testchip CONTROL_LOGIC(

-    .wb_clock(clk_in),

-    .gpio_clock(clk_in),

+    .clk(clk_in),

     .reset(rst),

     .la_packet(from_analyzer),

     .gpio_packet(from_gpio),