commit 1e29edabd48c44185c75a88a03721d2361d4cfe4
author mrg <mrg@ucsc.edu> Fri Jun 18 18:49:30 2021 -0700
committer mrg <mrg@ucsc.edu> Fri Jun 18 18:49:30 2021 -0700
tree aa38b46a18396cdb2dfc5f5f54cd1fa1febd58a0
parent be1762c047b70bcf3b0963376355cc9335c7b58e
parent 261bdc57ee9589820c51c9bf2b629306cdeaa4e9

Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main

verilog/dv/gpio_test/gpio_test_tb.v

diff --git a/verilog/dv/gpio_test/gpio_test_tb.v b/verilog/dv/gpio_test/gpio_test_tb.v
index 0f712ef..6f4ddf8 100644
--- a/verilog/dv/gpio_test/gpio_test_tb.v
+++ b/verilog/dv/gpio_test/gpio_test_tb.v
@@ -136,7 +136,7 @@
 			gpio_sram_load = 1;
 			#25;
 
-			#25;
+			#75;
 			gpio_sram_load = 0;
 			gpio_scan = 1;
 			for(j = 0; j < 112; j = j + 1) begin
@@ -184,7 +184,7 @@
 			gpio_sram_load = 1;
 			#25;    
 			
-			#25;
+			#75;
 			gpio_sram_load = 0;
 			gpio_scan = 1;
 			for(j = 0; j < 112; j = j + 1) begin
@@ -231,7 +231,7 @@
 		gpio_sram_load = 1;
 		#25;    
 		
-		#25;
+		#75;
 		gpio_sram_load = 0;
 		gpio_scan = 1;
 		for(j = 0; j < 112; j = j + 1) begin
@@ -242,7 +242,14 @@
 		#25;
 
 		#25; $finish;
-	end
+	end 
+
+	initial begin
+            // Observe Output pin 22
+            wait(mprj_io_22 == 8'h01);
+            $display("Saw bit 22");
+            //$finish;
+        end
 
 	initial begin
 		RSTB <= 1'b0;