Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
1ccad06612ae94254dc3a170ac15ba68dbb27dd9
commit
1ccad06612ae94254dc3a170ac15ba68dbb27dd9
[
log
]
author
AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 17:43:43 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Tue Jun 15 17:43:43 2021 -0700
tree
e40f267109b47bcde1c7dc5bdb3d87db10d7c110
parent
041a753825c8426b175defbf7f3fd0165a1bf6a9
[
diff
]
Works for all memories using LA interface
verilog/rtl/openram_testchip_tb.v
[
diff
]
1 file changed
tree: e40f267109b47bcde1c7dc5bdb3d87db10d7c110
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.