commit 16df1c4fc5698ba91a14221ec2c9ba6ce8d2bd86
author mrg <mrg@ucsc.edu> Fri Jul 09 12:07:18 2021 -0700
committer mrg <mrg@ucsc.edu> Fri Jul 09 12:07:18 2021 -0700
tree 7b58371594cfe71366b6e10b905c4d8d3e1a2286
parent cca863573f7dec6dcb91b3fff26cd9cd201aa33e

Assign spare din/dout signals

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 6b58e09..293c834 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -356,8 +356,8 @@
      .web0   (web0),
      .wmask0 (wmask0),
      .addr0  (addr0),
-     .din0   (din0),
-     .dout0  (sram8_dout0),
+     .din0   ({1'b0, din0}),
+     .dout0  ({disconn8, sram8_dout0}),
      .spare_wen0(1'b0)
      );
 
@@ -372,8 +372,8 @@
      .web0   (web0),
      .wmask0 (wmask0),
      .addr0  (addr0),
-     .din0   (din0),
-     .dout0  (sram9_dout0),
+     .din0   ({1'b0, din0}),
+     .dout0  ({disconn9, sram9_dout0}),
      .spare_wen0(1'b0)
      );
 
@@ -388,8 +388,8 @@
      .web0   (web0),
      .wmask0 (wmask0),
      .addr0  (addr0),
-     .din0   (din0),
-     .dout0  (sram10_dout0),
+     .din0   ({1'b0, din0}),
+     .dout0  ({disconn10, sram10_dout0}),
      .spare_wen0(1'b0)
      );
 
@@ -406,8 +406,8 @@
      .web0   (web0),
      .wmask0 ({wmask0[3:2],4'hF,wmask0[1:0]}),
      .addr0  (addr0),
-     .din0   ({din0, din0}),
-     .dout0  (temp_sram11_dout0),
+     .din0   ({1'b0, din0, din0}),
+     .dout0  ({disconn11, temp_sram11_dout0}),
      .spare_wen0(1'b0)
      );
    assign sram11_dout0 = {temp_sram11_dout0[63:48], temp_sram11_dout0[15:0]};