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foss-eda-tools/third_party/shuttle/sky130/mpw-002/slot-009/0dd2159263d27fb686644a247968325067c8ff36^!/.
commit
0dd2159263d27fb686644a247968325067c8ff36
[log]
author
mrg <mrg@ucsc.edu>
Thu Jun 17 05:35:41 2021 -0700
committer
mrg <mrg@ucsc.edu>
Thu Jun 17 05:35:41 2021 -0700
tree
fcdf95bc5aeab5357d9e2405b06507f4b6cdb812
parent
d15e74c74de99d22d9b9691c1032c3fafd2d362d [diff]
Resolve clock port and net issue by making clock_mux

diff --git a/openlane/openram_testchip/config.tcl b/openlane/openram_testchip/config.tcl
index 6448023..4533576 100644
--- a/openlane/openram_testchip/config.tcl
+++ b/openlane/openram_testchip/config.tcl

@@ -7,11 +7,12 @@
 set ::env(GLB_RT_MAXLAYER) 5
 
 set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/openram_defines.v \
-			 $script_dir/../../verilog/rtl/openram_testchip.v"
+    			  $script_dir/../../verilog/rtl/clock_mux.v \
+			  $script_dir/../../verilog/rtl/openram_testchip.v"
 set ::env(BASE_SDC_FILE) "$script_dir/openram_testchip.sdc"
 
-set ::env(CLOCK_PORT) "la_clk"
-set ::env(CLOCK_NET) "clk"
+set ::env(CLOCK_PORT) "clkmux.clk"
+set ::env(CLOCK_NET) "clkmux.clk"
 set ::env(RESET_PORT) "resetn"
 
 #set ::env(CLOCK_NET) ""

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index deb410e..2b7b886 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl

@@ -27,14 +27,12 @@
 ## Source Verilog Files
 set ::env(VERILOG_FILES) "\
 	$script_dir/../../caravel/verilog/rtl/defines.v \
+	$script_dir/../../verilog/rtl/clock_mux.v \
 	$script_dir/../../verilog/rtl/user_project_wrapper.v "
 
 ## Clock configurations
-# This is la_sram_clk
-# This should be la_data_in[126]
-#set ::env(CLOCK_PORT) "la_sram_clk"
-set ::env(CLOCK_PORT) {la_data_in\[126\]}
-set ::env(CLOCK_NET) "sram_clk"
+set ::env(CLOCK_PORT) "clkmux.clk"
+set ::env(CLOCK_NET) "clkmux.clk"
 
 set ::env(CLOCK_PERIOD) "20"
 set ::env(BASE_SDC_FILE) "$script_dir/user_project_wrapper.sdc"

diff --git a/verilog/rtl/clock_mux.v b/verilog/rtl/clock_mux.v
new file mode 100644
index 0000000..c1a92b1
--- /dev/null
+++ b/verilog/rtl/clock_mux.v

@@ -0,0 +1,11 @@
+module clock_mux(
+		 input 	clk0,
+		 input 	clk1,
+		 input 	sel,
+		 output reg clk);
+
+always @(*) begin
+   clk = sel ? clk1 : clk0;
+end
+
+endmodule // clock_mux

diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index c8d89bb..0bff047 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v

@@ -85,8 +85,6 @@
 			output reg gpio_out
 );
 
-   reg clk;
-
 // Store input instruction
    reg [`TOTAL_SIZE-1:0] sram_register;
    reg 		       csb0_temp;
@@ -109,10 +107,13 @@
 
 
 
-//Selecting clock pin
-always @(*) begin
-    clk = in_select ? gpio_clk : la_clk;
-end
+   // Selecting clock pin
+   wire 		  clk;
+   clock_mux clkmux(.clk0(la_clk),
+		    .clk1(gpio_clk),
+		    .sel(in_select),
+		    .clk(clk));
+
 
 always @ (posedge clk) begin
    if(!resetn) begin

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5b1e7e3..40a8938 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v

@@ -141,85 +141,84 @@
    assign io_out[21] = gpio_out;
    assign io_out[20:0] = 0;
 
-   wire la_sram_clk = la_data_in[126];
+   wire sram_clk;
+   clock_mux clkmux(.clk0(la_data_in[126]),
+		    .clk1(gpio_sram_clk),
+		    .sel(in_select),
+		    .clk(sram_clk));
 
-   reg 	sram_clk;
 
-always @(*) begin
-    sram_clk = in_select ? gpio_sram_clk : la_sram_clk;
-end
+   openram_testchip CONTROL_LOGIC(
+				  .resetn(resetn & wb_rst_i),
+				  .in_select(in_select),
+				  .gpio_clk(gpio_clk),
+				  .gpio_scan(gpio_scan),
+				  .gpio_sram_load(gpio_sram_load),
 
-openram_testchip CONTROL_LOGIC(
-			       .resetn(resetn & wb_rst_i),
-			       .in_select(in_select),
-			       .gpio_clk(gpio_clk),
-			       .gpio_scan(gpio_scan),
-			       .gpio_sram_load(gpio_sram_load),
+				  .la_clk(la_data_in[127]),
+				  .la_in_load(la_data_in[125]),
+				  .la_sram_load(la_data_in[124]),
+				  .la_data_in(la_data_in[111:0]),
+				  .la_data_out(la_data_out[111:0]),
+				  .gpio_out(gpio_out),
 
-			       .la_clk(la_data_in[127]),
-			       .la_in_load(la_data_in[125]),
-			       .la_sram_load(la_data_in[124]),
-			       .la_data_in(la_data_in[111:0]),
-			       .la_data_out(la_data_out[111:0]),
-			       .gpio_out(gpio_out),
+				  // Shared control/data to the SRAMs
+				  .left_addr0(left_addr0),
+				  .left_din0(left_din0),
+				  .left_web0(left_web0),
+				  .left_wmask0(left_wmask0),
+				  .left_addr1(left_addr1),
+				  .left_web1(left_web1),
+				  .left_wmask1(left_wmask1),
+				  // One CSB for each SRAM
+				  .left_csb0(left_csb0),
+				  .left_csb1(left_csb1),
 
-			       // Shared control/data to the SRAMs
-			       .left_addr0(left_addr0),
-			       .left_din0(left_din0),
-			       .left_web0(left_web0),
-			       .left_wmask0(left_wmask0),
-			       .left_addr1(left_addr1),
-			       .left_web1(left_web1),
-			       .left_wmask1(left_wmask1),
-			       // One CSB for each SRAM
-			       .left_csb0(left_csb0),
-			       .left_csb1(left_csb1),
+				  // Shared control/data to the SRAMs
+				  .right_addr0(right_addr0),
+				  .right_din0(right_din0),
+				  .right_web0(right_web0),
+				  .right_wmask0(right_wmask0),
+				  // One CSB for each SRAM
+				  .right_csb0(right_csb0),
 
-			       // Shared control/data to the SRAMs
-			       .right_addr0(right_addr0),
-			       .right_din0(right_din0),
-			       .right_web0(right_web0),
-			       .right_wmask0(right_wmask0),
-			       // One CSB for each SRAM
-			       .right_csb0(right_csb0),
+				  // SRAM data outputs to be captured
+				  .sram0_data0(sram0_data0),
+				  .sram0_data1(sram0_data1),
+				  .sram1_data0(sram1_data0),
+				  .sram1_data1(sram1_data1),
+				  .sram2_data0(sram2_data0),
+				  .sram2_data1(sram2_data1),
+				  .sram3_data0(sram3_data0),
+				  .sram3_data1(sram3_data1),
+				  .sram4_data0(sram4_data0),
+				  .sram4_data1(sram4_data1),
+				  .sram5_data0(sram5_data0),
+				  .sram5_data1(sram5_data1),
+				  .sram6_data0(sram6_data0),
+				  .sram6_data1(sram6_data1),
+				  .sram7_data0(sram7_data0),
+				  .sram7_data1(sram7_data1),
+				  .sram8_data0(sram8_data0),
+				  .sram8_data1(sram8_data1),
+				  .sram9_data0(sram9_data0),
+				  .sram9_data1(sram9_data1),
+				  .sram10_data0(sram10_data0),
+				  .sram10_data1(sram10_data1),
+				  .sram11_data0(sram11_data0),
+				  .sram11_data1(sram11_data1),
+				  .sram12_data0(sram12_data0),
+				  .sram12_data1(sram12_data1),
+				  .sram13_data0(sram13_data0),
+				  .sram13_data1(sram13_data1),
+				  .sram14_data0(sram14_data0),
+				  .sram14_data1(sram14_data1),
+				  .sram15_data0(sram15_data0),
+				  .sram15_data1(sram15_data1)
 
-			       // SRAM data outputs to be captured
-			       .sram0_data0(sram0_data0),
-			       .sram0_data1(sram0_data1),
-			       .sram1_data0(sram1_data0),
-			       .sram1_data1(sram1_data1),
-			       .sram2_data0(sram2_data0),
-			       .sram2_data1(sram2_data1),
-			       .sram3_data0(sram3_data0),
-			       .sram3_data1(sram3_data1),
-			       .sram4_data0(sram4_data0),
-			       .sram4_data1(sram4_data1),
-			       .sram5_data0(sram5_data0),
-			       .sram5_data1(sram5_data1),
-			       .sram6_data0(sram6_data0),
-			       .sram6_data1(sram6_data1),
-			       .sram7_data0(sram7_data0),
-			       .sram7_data1(sram7_data1),
-			       .sram8_data0(sram8_data0),
-			       .sram8_data1(sram8_data1),
-			       .sram9_data0(sram9_data0),
-			       .sram9_data1(sram9_data1),
-			       .sram10_data0(sram10_data0),
-			       .sram10_data1(sram10_data1),
-			       .sram11_data0(sram11_data0),
-			       .sram11_data1(sram11_data1),
-			       .sram12_data0(sram12_data0),
-			       .sram12_data1(sram12_data1),
-			       .sram13_data0(sram13_data0),
-			       .sram13_data1(sram13_data1),
-			       .sram14_data0(sram14_data0),
-			       .sram14_data1(sram14_data1),
-			       .sram15_data0(sram15_data0),
-			       .sram15_data1(sram15_data1)
+				  );
 
-);
-
-   wire [`ADDR_SIZE-1:0]  left_addr0;
+   wire [`ADDR_SIZE-1:0] left_addr0;
    wire [`DATA_SIZE-1:0] left_din0;
    wire 		 left_web0;
    wire [`WMASK_SIZE-1:0] left_wmask0;
@@ -231,43 +230,43 @@
    wire [`MAX_CHIPS-1:0]  left_csb1;
 
    wire [`ADDR_SIZE-1:0]  right_addr0;
-   wire [`DATA_SIZE-1:0] right_din0;
-   wire 		 right_web0;
+   wire [`DATA_SIZE-1:0]  right_din0;
+   wire 		  right_web0;
    wire [`WMASK_SIZE-1:0] right_wmask0;
    wire [`MAX_CHIPS-1:0]  right_csb0;
 
-   wire [`DATA_SIZE-1:0] sram0_dout0;
-   wire [`DATA_SIZE-1:0] sram0_dout1;
-   wire [`DATA_SIZE-1:0] sram1_dout0;
-   wire [`DATA_SIZE-1:0] sram1_dout1;
-   wire [`DATA_SIZE-1:0] sram2_dout0;
-   wire [`DATA_SIZE-1:0] sram2_dout1;
-   wire [`DATA_SIZE-1:0] sram3_dout0;
-   wire [`DATA_SIZE-1:0] sram3_dout1;
-   wire [`DATA_SIZE-1:0] sram4_dout0;
-   wire [`DATA_SIZE-1:0] sram4_dout1;
-   wire [`DATA_SIZE-1:0] sram5_dout0;
-   wire [`DATA_SIZE-1:0] sram5_dout1;
-   wire [`DATA_SIZE-1:0] sram6_dout0;
-   wire [`DATA_SIZE-1:0] sram6_dout1;
-   wire [`DATA_SIZE-1:0] sram7_dout0;
-   wire [`DATA_SIZE-1:0] sram7_dout1;
-   wire [`DATA_SIZE-1:0] sram8_dout0;
-   wire [`DATA_SIZE-1:0] sram8_dout1;
-   wire [`DATA_SIZE-1:0] sram9_dout0;
-   wire [`DATA_SIZE-1:0] sram9_dout1;
-   wire [`DATA_SIZE-1:0] sram10_dout0;
-   wire [`DATA_SIZE-1:0] sram10_dout1;
-   wire [`DATA_SIZE-1:0] sram11_dout0;
-   wire [`DATA_SIZE-1:0] sram11_dout1;
-   wire [`DATA_SIZE-1:0] sram12_dout0;
-   wire [`DATA_SIZE-1:0] sram12_dout1;
-   wire [`DATA_SIZE-1:0] sram13_dout0;
-   wire [`DATA_SIZE-1:0] sram13_dout1;
-   wire [`DATA_SIZE-1:0] sram14_dout0;
-   wire [`DATA_SIZE-1:0] sram14_dout1;
-   wire [`DATA_SIZE-1:0] sram15_dout0;
-   wire [`DATA_SIZE-1:0] sram15_dout1;
+   wire [`DATA_SIZE-1:0]  sram0_dout0;
+   wire [`DATA_SIZE-1:0]  sram0_dout1;
+   wire [`DATA_SIZE-1:0]  sram1_dout0;
+   wire [`DATA_SIZE-1:0]  sram1_dout1;
+   wire [`DATA_SIZE-1:0]  sram2_dout0;
+   wire [`DATA_SIZE-1:0]  sram2_dout1;
+   wire [`DATA_SIZE-1:0]  sram3_dout0;
+   wire [`DATA_SIZE-1:0]  sram3_dout1;
+   wire [`DATA_SIZE-1:0]  sram4_dout0;
+   wire [`DATA_SIZE-1:0]  sram4_dout1;
+   wire [`DATA_SIZE-1:0]  sram5_dout0;
+   wire [`DATA_SIZE-1:0]  sram5_dout1;
+   wire [`DATA_SIZE-1:0]  sram6_dout0;
+   wire [`DATA_SIZE-1:0]  sram6_dout1;
+   wire [`DATA_SIZE-1:0]  sram7_dout0;
+   wire [`DATA_SIZE-1:0]  sram7_dout1;
+   wire [`DATA_SIZE-1:0]  sram8_dout0;
+   wire [`DATA_SIZE-1:0]  sram8_dout1;
+   wire [`DATA_SIZE-1:0]  sram9_dout0;
+   wire [`DATA_SIZE-1:0]  sram9_dout1;
+   wire [`DATA_SIZE-1:0]  sram10_dout0;
+   wire [`DATA_SIZE-1:0]  sram10_dout1;
+   wire [`DATA_SIZE-1:0]  sram11_dout0;
+   wire [`DATA_SIZE-1:0]  sram11_dout1;
+   wire [`DATA_SIZE-1:0]  sram12_dout0;
+   wire [`DATA_SIZE-1:0]  sram12_dout1;
+   wire [`DATA_SIZE-1:0]  sram13_dout0;
+   wire [`DATA_SIZE-1:0]  sram13_dout1;
+   wire [`DATA_SIZE-1:0]  sram14_dout0;
+   wire [`DATA_SIZE-1:0]  sram14_dout1;
+   wire [`DATA_SIZE-1:0]  sram15_dout0;
+   wire [`DATA_SIZE-1:0]  sram15_dout1;
 
 sky130_sram_1kbyte_1rw1r_8x1024_8 SRAM0
      (