commit 041a753825c8426b175defbf7f3fd0165a1bf6a9
author AmoghLonkar <alonkar@ucsc.edu> Tue Jun 15 16:55:56 2021 -0700
committer AmoghLonkar <alonkar@ucsc.edu> Tue Jun 15 16:55:56 2021 -0700
tree 6449f86f3c1fe3565368c78a472189d456d676b9
parent aef5f1acdc5a6e531e0b784b5350d33ad66b403e

Works for dual port memories

verilog/rtl/openram_testchip_tb.v

diff --git a/verilog/rtl/openram_testchip_tb.v b/verilog/rtl/openram_testchip_tb.v
index 9561fc0..92acf5f 100644
--- a/verilog/rtl/openram_testchip_tb.v
+++ b/verilog/rtl/openram_testchip_tb.v
@@ -391,9 +391,10 @@
       sram_clk = 1;

       #5;

       sram_clk = 0;

-      #20;

+      #5;

 

-      `assert(la_data_out, {4'd0, 16'd1, 32'd1, 1'b0, 1'b1, 4'd0, 16'd2, 32'd2, 1'b0, 1'b1, 4'd0});

+      #10;

+      `assert(la_data_out, {sel, 16'd1, 32'd1, 1'b0, 1'b1, 4'd0, 16'd2, 32'd2, 1'b0, 1'b1, 4'd0});

     end

     #10;$finish;

 end