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foss-eda-tools / third_party / shuttle / sky130 / mpw-002 / slot-008 / bcd7adcff4824b318123ed077a7a49ffcf81405f / verilog
  1. 22f3cd0 Submodule caravel-lite by manarabdelaty · 4 years ago
  2. c0f458a Update DV Makefile by manarabdelaty · 4 years ago
  3. eac56e8 Rename CARAVEL_MASTER -> CARAVEL_ROOT by manarabdelaty · 4 years ago
  4. 191408b Add SPDX header by manarabdelaty · 4 years ago
  5. 8dbabc1 Update DV Makefiles by manarabdelaty · 4 years ago
  6. 8e8bf63 Update la_test2 Makefile by manarabdelaty · 4 years ago
  7. 496112a Add CARAVEL_PATH for the testbenches by manarabdelaty · 4 years ago
  8. f989c64 Corrected the user_project_wrapper verilog to have the correct by Tim Edwards · 4 years ago
  9. a7929f3 Added mprj_stimulus test by manarabdelaty · 4 years ago
  10. d184bf6 Update wb_port dv makefile by manarabdelaty · 4 years ago
  11. 3e3151b [DATA] update views to reflect rtl change by manarabdelaty · 4 years ago
  12. a63e2e6 Makefile and RTL updates to run GL sim by manarabdelaty · 4 years ago
  13. 10b3a10 Update README.md by Manar · 4 years ago
  14. fa36b99 Merge branch 'main' of https://github.com/efabless/caravel_project_example into main by manarabdelaty · 4 years ago
  15. 69bd326 Updated DV tests by manarabdelaty · 4 years ago
  16. 548e5a7 [DATA] Adjust user_proj_example/config.tcl by Ahmed Ghazy · 4 years ago
  17. d4ec2f0 Example of a full run of user_project_wrapper by Ahmed Ghazy · 4 years ago