commit: 9e5d826da74b7ba1541c57d7db7bd021ca2c8dce
[log] [tgz]
author: dinesha <dineshannayya@users.noreply.github.com>
Sun Jun 06 09:19:03 2021 +0000
committer: dinesha <dineshannayya@users.noreply.github.com>
Sun Jun 06 09:19:03 2021 +0000
tree: 46ae517b88aceebb8324ff0e9352dfcf8d9d08c6

Initial version of efabless caravel user project

LICENSE[Added - diff]
Makefile[Added - diff]
README.md[Added - diff]
info.yaml[Added - diff]
openlane/Makefile[Added - diff]
openlane/user_project_wrapper/config.tcl[Added - diff]
openlane/user_project_wrapper/macro.cfg[Added - diff]
openlane/user_project_wrapper/pin_order.cfg[Added - diff]
openlane/yifive/config.tcl[Added - diff]
openlane/yifive/pin_order.cfg[Added - diff]
verilog/dv/Makefile[Added - diff]
verilog/dv/README.md[Added - diff]
verilog/dv/io_ports/Makefile[Added - diff]
verilog/dv/io_ports/io_ports.c[Added - diff]
verilog/dv/io_ports/io_ports_tb.v[Added - diff]
verilog/dv/la_test1/Makefile[Added - diff]
verilog/dv/la_test1/la_test1.c[Added - diff]
verilog/dv/la_test1/la_test1_tb.v[Added - diff]
verilog/dv/la_test2/Makefile[Added - diff]
verilog/dv/la_test2/la_test2.c[Added - diff]
verilog/dv/la_test2/la_test2_tb.v[Added - diff]
verilog/dv/mprj_stimulus/Makefile[Added - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Added - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Added - diff]
verilog/dv/wb_port/Makefile[Added - diff]
verilog/dv/wb_port/wb_port.c[Added - diff]
verilog/dv/wb_port/wb_port_tb.v[Added - diff]
verilog/gl/user_proj_example.v[Added - diff]
verilog/gl/user_project_wrapper.v[Added - diff]
verilog/rtl/uprj_netlists.v[Added - diff]
verilog/rtl/user_proj_example.v[Added - diff]
verilog/rtl/user_project_wrapper.v[Added - diff]

32 files changed

tree: 46ae517b88aceebb8324ff0e9352dfcf8d9d08c6

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.