commit: 0fe51f68fd99ddb927bc16ad91f00f0565432fca
[log]
author: dinesha <dineshannayya@users.noreply.github.com>
Mon Jun 07 16:02:40 2021 +0000
committer: dinesha <dineshannayya@users.noreply.github.com>
Mon Jun 07 16:02:40 2021 +0000
tree: a7aec5b0ce5abb6daf11bd349b2b8a3326a912ce
parent: 69e9dbcb292103dc645fa473148ceaef2c1bbe0e [diff]

syntacore_scr1 directory removal

verilog/rtl/syntacore_scr1/src/ahb_top.files[Deleted - diff]
verilog/rtl/syntacore_scr1/src/axi_top.files[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core.files[Deleted - diff]
verilog/rtl/syntacore_scr1/src/run_modemsim[Deleted - diff]
verilog/rtl/syntacore_scr1/src/wb_top.files[Deleted - diff]

5 files changed

tree: a7aec5b0ce5abb6daf11bd349b2b8a3326a912ce

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.