commit	21e5ba9232d8ff6df934df99088a7187bd1ded1b	[log] [tgz]
author	dinesha <dineshannayya@users.noreply.github.com>	Sun Jun 13 06:39:28 2021 +0000
committer	dinesha <dineshannayya@users.noreply.github.com>	Sun Jun 13 06:39:28 2021 +0000
tree	c71e8d0e99a8c3bb1e204262a24b33a0fda09742
parent	d4c716c8b8e35613a534c25722755902bdd69b19 [diff]

test bench update

verilog/dv/Makefile[diff]
verilog/dv/io_ports/Makefile[diff]
verilog/dv/io_ports/io_ports_tb.v[diff]
verilog/dv/io_ports/mgmt_core.sv[Added - diff]
verilog/dv/la_test1/Makefile[diff]
verilog/dv/la_test2/Makefile[diff]
verilog/dv/model/mt48lc8m8a2.v[Added - diff]
verilog/dv/risc_boot/Makefile[Added - diff]
verilog/dv/risc_boot/risc_boot.c[Added - diff]
verilog/dv/risc_boot/risc_boot_tb.v[Added - diff]
verilog/dv/risc_boot/run_iverilog[Added - diff]
verilog/dv/risc_boot/user_risc_boot.hex[Added - diff]
verilog/dv/user_risc_boot/Makefile[Added - diff]
verilog/dv/user_risc_boot/run_iverilog[Added - diff]
verilog/dv/user_risc_boot/uprj_netlists.v[Added - diff]
verilog/dv/user_risc_boot/user_risc_boot.c[Added - diff]
verilog/dv/user_risc_boot/user_risc_boot.hex[Added - diff]
verilog/dv/user_risc_boot/user_risc_boot_tb.v[Added - diff]
verilog/dv/wb_port/Makefile[diff]
verilog/dv/wb_port/wb_port.c[diff]
verilog/dv/wb_port/wb_port_tb.v[diff]
verilog/rtl/digital_core/src/glbl_cfg.sv[Added - diff]
verilog/rtl/lib/clk_ctl.v[Added - diff]
verilog/rtl/lib/registers.v[Added - diff]
verilog/rtl/syntacore/scr1/sim/tests/common/LICENSE[Added - diff]
verilog/rtl/syntacore/scr1/sim/tests/common/common.mk[Added - diff]
verilog/rtl/syntacore/scr1/sim/tests/common/crt.S[Added - diff]
verilog/rtl/syntacore/scr1/sim/tests/common/crt_tcm.S[Added - diff]
verilog/rtl/syntacore/scr1/sim/tests/common/csr.h[Added - diff]
verilog/rtl/syntacore/scr1/sim/tests/common/link.ld[Added - diff]
verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld[Added - diff]
verilog/rtl/syntacore/scr1/sim/tests/common/reloc.h[Added - diff]
verilog/rtl/syntacore/scr1/sim/tests/common/riscv_csr_encoding.h[Added - diff]
verilog/rtl/syntacore/scr1/sim/tests/common/riscv_macros.h[Added - diff]
verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.c[Added - diff]
verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.h[Added - diff]
verilog/rtl/syntacore/scr1/sim/tests/common/sc_test.h[Added - diff]
verilog/rtl/syntacore/scr1/sim/tests/common/scr1_specific.h[Added - diff]

38 files changed

tree: c71e8d0e99a8c3bb1e204262a24b33a0fda09742

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.