repo fix
diff --git a/.github/scripts/build/run-set-id.sh b/.github/scripts/build/run-set-id.sh
new file mode 100644
index 0000000..b6e9cfb
--- /dev/null
+++ b/.github/scripts/build/run-set-id.sh
@@ -0,0 +1,38 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+export UPRJ_ROOT=$(pwd)
+cd ..
+export PDK_ROOT=$(pwd)/pdks
+export CARAVEL_ROOT=$(pwd)/caravel
+export IMAGE_NAME=efabless/openlane:$OPENLANE_TAG
+export USER_ID=00000001
+
+cd $UPRJ_ROOT
+
+# Install full version of caravel
+git clone https://github.com/efabless/caravel --branch develop --depth 1 $CARAVEL_ROOT
+
+LOG_FILE=out.log
+docker run -v $UPRJ_ROOT:$UPRJ_ROOT -v $PDK_ROOT:$PDK_ROOT -v $CARAVEL_ROOT:$CARAVEL_ROOT -e UPRJ_ROOT=$UPRJ_ROOT -e PDK_ROOT=$PDK_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME bash -c "cd $CARAVEL_ROOT; make uncompress; cd $UPRJ_ROOT; export USER_ID=$USER_ID; make set_user_id | tee $LOG_FILE;"
+
+cnt=$(grep "Done" $LOG_FILE -s | wc -l)
+
+if [[ $cnt -ne 3 ]]; then
+ exit 2;
+fi
+
+exit 0
\ No newline at end of file
diff --git a/.github/scripts/build/run-truck.sh b/.github/scripts/build/run-truck.sh
new file mode 100644
index 0000000..84f183b
--- /dev/null
+++ b/.github/scripts/build/run-truck.sh
@@ -0,0 +1,36 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+export UPRJ_ROOT=$(pwd)
+cd ..
+export PDK_ROOT=$(pwd)/pdks
+export CARAVEL_ROOT=$(pwd)/caravel
+export IMAGE_NAME=efabless/openlane:$OPENLANE_TAG
+
+cd $UPRJ_ROOT
+
+# Install full version of caravel
+git clone https://github.com/efabless/caravel --branch develop --depth 1 $CARAVEL_ROOT
+
+docker run -v $UPRJ_ROOT:$UPRJ_ROOT -v $PDK_ROOT:$PDK_ROOT -v $CARAVEL_ROOT:$CARAVEL_ROOT -e UPRJ_ROOT=$UPRJ_ROOT -e PDK_ROOT=$PDK_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME bash -c "cd $CARAVEL_ROOT; make uncompress; cd $UPRJ_ROOT; make truck;"
+
+SHIP_FILE=$UPRJ_ROOT/gds/caravan.gds
+
+if test -f "$SHIP_FILE"; then
+ exit 0
+else
+ exit 2
+fi
diff --git a/.github/scripts/build/run-xor.sh b/.github/scripts/build/run-xor.sh
new file mode 100644
index 0000000..e666188
--- /dev/null
+++ b/.github/scripts/build/run-xor.sh
@@ -0,0 +1,39 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+export UPRJ_ROOT=$(pwd)
+cd ..
+export PDK_ROOT=$(pwd)/pdks
+export CARAVEL_ROOT=$(pwd)/caravel
+export IMAGE_NAME=efabless/openlane:$OPENLANE_TAG
+
+cd $UPRJ_ROOT
+
+# Install full version of caravel
+git clone https://github.com/efabless/caravel --branch develop --depth 1 $CARAVEL_ROOT
+
+LOG_FILE=out.log
+docker run -v $UPRJ_ROOT:$UPRJ_ROOT -v $PDK_ROOT:$PDK_ROOT -v $CARAVEL_ROOT:$CARAVEL_ROOT -e UPRJ_ROOT=$UPRJ_ROOT -e PDK_ROOT=$PDK_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME bash -c "cd $UPRJ_ROOT; export USER_ID=$USER_ID; make xor-analog-wrapper | tee $LOG_FILE;"
+
+cnt=$(grep -oP '(?<=Total XOR differences = )[0-9]+' $LOG_FILE)
+
+echo "Total XOR differences = $cnt"
+
+if [[ $cnt -ne 0 ]]; then
+ exit 2;
+fi
+
+exit 0
diff --git a/.github/scripts/dv/pdkBuild.sh b/.github/scripts/dv/pdkBuild.sh
new file mode 100644
index 0000000..9f9ac93
--- /dev/null
+++ b/.github/scripts/dv/pdkBuild.sh
@@ -0,0 +1,59 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+export RUN_ROOT=$(pwd)
+
+
+# By default skip timing since we don't need the libs in any of the CI tests
+export SKIP_TIMING=${1:-1}
+export IMAGE_NAME=efabless/openlane:$OPENLANE_TAG
+docker pull $IMAGE_NAME
+
+cd $RUN_ROOT/..
+export PDK_ROOT=$(pwd)/pdks
+mkdir $PDK_ROOT
+echo $PDK_ROOT
+echo $RUN_ROOT
+cd $RUN_ROOT
+make skywater-pdk
+make skywater-library
+# The following section is for running on the CI.
+# If you're running locally you should replace them with: `make skywater-library`
+# This is because sometimes while setting up the conda env (skywater's make timing) it fails to fetch something
+# Then it exits without retrying. So, here we're retrying, and if something goes wrong it will exit after 5 retries.
+# Section Begin
+if [ $SKIP_TIMING -eq 0 ]; then
+ cnt=0
+ until make skywater-timing; do
+ cnt=$((cnt+1))
+ if [ $cnt -eq 5 ]; then
+ exit 2
+ fi
+ rm -rf $PDK_ROOT/skywater-pdk
+ make skywater-pdk
+ make skywater-library
+ done
+fi
+# Section End
+
+make open_pdks
+docker run -v $RUN_ROOT:/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME bash -c "make build-pdk"
+
+rm -rf $PDK_ROOT/open_pdks
+rm -rf $PDK_ROOT/skywater-pdk
+
+echo "done installing"
+cd $RUN_ROOT
+exit 0
\ No newline at end of file
diff --git a/.github/scripts/dv/run-dv-wrapper.sh b/.github/scripts/dv/run-dv-wrapper.sh
new file mode 100644
index 0000000..f431eca
--- /dev/null
+++ b/.github/scripts/dv/run-dv-wrapper.sh
@@ -0,0 +1,77 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# comma seperated test ids
+IDS=$1
+# simulation mode : RTL/GL
+SIM_MODE=$2
+
+DV_TEST_IDS=(${IDS//,/ })
+
+export TARGET_PATH=$(pwd)
+export CARAVEL_ROOT=$(pwd)/caravel
+
+if [ ! -d $TARGET_PATH ]
+then
+ echo "Directory /path/to/dir DOES NOT exists."
+ exit 9999
+fi
+
+cd ..
+
+export PDK_PATH=$(pwd)/pdks/sky130A
+if [ ! -d $PDK_PATH ]
+then
+ echo "Directory /path/to/dir DOES NOT exists."
+ exit 9999
+fi
+
+DV_PATH=$TARGET_PATH/verilog/dv
+if [ ! -d $DV_PATH ]
+then
+ echo "Directory /path/to/dir DOES NOT exists."
+ exit 9999
+fi
+
+for id in "${DV_TEST_IDS[@]}"
+do
+ docker run -v $TARGET_PATH:$TARGET_PATH -v $PDK_PATH:$PDK_PATH \
+ -v $CARAVEL_ROOT:$CARAVEL_ROOT \
+ -e TARGET_PATH=$TARGET_PATH -e PDK_PATH=$PDK_PATH \
+ -e CARAVEL_ROOT=$CARAVEL_ROOT \
+ -u $(id -u $USER):$(id -g $USER) efabless/dv_setup:latest \
+ bash -c "bash $TARGET_PATH/.github/scripts/dv/run-dv.sh $PDK_PATH $DV_PATH $id $SIM_MODE"
+
+ echo "DONE!"
+
+ VERDICT_FILE=$TARGET_PATH/verilog/dv/$id.out
+
+ if [ -f $VERDICT_FILE ]; then
+ cnt=$(grep "Pass" $VERDICT_FILE -s | wc -l)
+ if ! [[ $cnt ]]; then cnt = 0; fi
+ else
+ echo "DV check failed due to subscript failure. Please review the logs";
+ exit 2;
+ fi
+
+ echo "Verdict: $cnt"
+
+ if [[ $cnt -ne 1 ]]; then
+ exit 2;
+ fi
+done
+
+exit 0;
diff --git a/.github/scripts/dv/run-dv.sh b/.github/scripts/dv/run-dv.sh
new file mode 100644
index 0000000..125cf3c
--- /dev/null
+++ b/.github/scripts/dv/run-dv.sh
@@ -0,0 +1,40 @@
+PDK_PATH=$1
+DV_PATH=$2
+DV_TEST_ID=$3
+SIM_MODE=$4
+
+cd $DV_PATH
+
+## get the name of all subdfolders under verilog/dv
+ALL_DV_TESTS="$(find * -maxdepth 0 -type d)"
+## convert all ALL_DV_TESTS to an array
+TESTS_ARR=($ALL_DV_TESTS)
+## get length of the TESTS array
+len=${#TESTS_ARR[@]}
+
+## make sure that the test ID is less than the array length
+if [ $DV_TEST_ID -ge $len ]
+then
+ echo "Error: Invalid Test ID"
+ exit 1
+fi
+
+## get the name corresponding to the test ID
+PATTERN=${TESTS_ARR[$DV_TEST_ID]}
+
+OUT_FILE=$DV_PATH/$DV_TEST_ID.out
+
+export SIM=$SIM_MODE
+echo "Running $PATTERN $SIM.."
+logFile=$DV_PATH/$PATTERN.$SIM.dv.out
+cd $PATTERN
+echo $(pwd)
+make 2>&1 | tee $logFile
+grep "Monitor" $logFile >> $OUT_FILE
+make clean
+
+echo "Execution Done on $PATTERN !"
+
+cat $OUT_FILE
+
+exit 0
\ No newline at end of file
diff --git a/.github/scripts/precheck/precheckBuild.sh b/.github/scripts/precheck/precheckBuild.sh
new file mode 100644
index 0000000..d618190
--- /dev/null
+++ b/.github/scripts/precheck/precheckBuild.sh
@@ -0,0 +1,36 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# By default build pdk since we don't need the other script for the main purpose
+export SKIP_PDK_BUILD=${1:-0}
+
+export TARGET_PATH=$(pwd)
+git clone https://github.com/efabless/open_mpw_precheck.git
+
+docker pull efabless/open_mpw_precheck:latest
+
+
+if [ $SKIP_PDK_BUILD -eq 0 ]; then
+ cd $TARGET_PATH/..
+ export PDK_ROOT=$(pwd)/precheck_pdks
+ mkdir $PDK_ROOT
+ cd $TARGET_PATH/open_mpw_precheck/dependencies
+ sh build-pdk.sh
+ cd $TARGET_DIR
+
+fi
+
+exit 0
diff --git a/.github/scripts/precheck/run-precheck-drc.sh b/.github/scripts/precheck/run-precheck-drc.sh
new file mode 100644
index 0000000..489b314
--- /dev/null
+++ b/.github/scripts/precheck/run-precheck-drc.sh
@@ -0,0 +1,36 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+export TARGET_PATH=$(pwd)
+export CARAVEL_ROOT=$(pwd)/caravel
+cd ..
+export PDK_ROOT=$(pwd)/precheck_pdks
+cd $TARGET_PATH/open_mpw_precheck/
+
+docker run -v $(pwd):/usr/local/bin -v $TARGET_PATH:$TARGET_PATH -v $CARAVEL_ROOT:$CARAVEL_ROOT -v $PDK_ROOT:$PDK_ROOT -u $(id -u $USER):$(id -g $USER) efabless/open_mpw_precheck:latest bash -c "python3 open_mpw_prechecker.py --drc_only -p $PDK_ROOT -t $TARGET_PATH -c $CARAVEL_ROOT"
+output=$TARGET_PATH/checks/full_log.log
+
+gzipped_file=$TARGET_PATH/checks/full_log.log.gz
+
+if [[ -f $gzipped_file ]]; then
+ gzip -d $gzipped_file
+fi
+
+grep "Violation Message" $output
+
+cnt=$(grep -c "All Checks PASSED!" $output)
+if ! [[ $cnt ]]; then cnt=0; fi
+if [[ $cnt -eq 1 ]]; then exit 0; fi
+exit 2
\ No newline at end of file
diff --git a/.github/scripts/precheck/run-precheck.sh b/.github/scripts/precheck/run-precheck.sh
new file mode 100644
index 0000000..b248a79
--- /dev/null
+++ b/.github/scripts/precheck/run-precheck.sh
@@ -0,0 +1,36 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+export TARGET_PATH=$(pwd)
+export CARAVEL_ROOT=$(pwd)/caravel
+cd ..
+export PDK_ROOT=$(pwd)/precheck_pdks
+cd $TARGET_PATH/open_mpw_precheck/
+
+docker run -v $(pwd):/usr/local/bin -v $TARGET_PATH:$TARGET_PATH -v $PDK_ROOT:$PDK_ROOT -v $CARAVEL_ROOT:$CARAVEL_ROOT -u $(id -u $USER):$(id -g $USER) efabless/open_mpw_precheck:latest bash -c "python3 open_mpw_prechecker.py --skip_drc -p $PDK_ROOT -t $TARGET_PATH -c $CARAVEL_ROOT"
+output=$TARGET_PATH/checks/full_log.log
+
+gzipped_file=$TARGET_PATH/checks/full_log.log.gz
+
+if [[ -f $gzipped_file ]]; then
+ gzip -d $gzipped_file
+fi
+
+grep "Violation Message" $output
+
+cnt=$(grep -c "All Checks PASSED!" $output)
+if ! [[ $cnt ]]; then cnt=0; fi
+if [[ $cnt -eq 1 ]]; then exit 0; fi
+exit 2
diff --git a/.github/workflows/auto_update_submodule.yml b/.github/workflows/auto_update_submodule.yml
new file mode 100644
index 0000000..7219ddf
--- /dev/null
+++ b/.github/workflows/auto_update_submodule.yml
@@ -0,0 +1,41 @@
+
+name: 'Auto-update Submodules'
+
+on:
+ workflow_dispatch:
+ schedule:
+ - cron: "0 0 * * *"
+
+jobs:
+ sync:
+ name: 'Auto-update Submodules'
+ runs-on: ubuntu-latest
+
+ # Use the Bash shell regardless whether the GitHub Actions runner is ubuntu-latest, macos-latest, or windows-latest
+ defaults:
+ run:
+ shell: bash
+
+ steps:
+ # Checkout the repository to the GitHub Actions runner
+ - name: Checkout
+ uses: actions/checkout@v2
+ with:
+ submodules: true
+
+ # Git config
+ - name: Git Configurations
+ run: |
+ git config --global user.name 'Git bot'
+ git config --global user.email 'bot@noreply.github.com'
+
+ # Update references
+ - name: Git Sumbodule Update
+ run: |
+ git submodule update --init --recursive
+ git submodule update --remote --recursive
+
+ - name: Commit update
+ run: |
+ git remote set-url origin https://x-access-token:${{ secrets.GITHUB_TOKEN }}@github.com/${{ github.repository }}
+ git commit -am "Auto updated submodule references" && git push || echo "No changes to commit"
diff --git a/.github/workflows/caravan_build.yml b/.github/workflows/caravan_build.yml
new file mode 100644
index 0000000..ea05126
--- /dev/null
+++ b/.github/workflows/caravan_build.yml
@@ -0,0 +1,78 @@
+name: Caravan Build
+
+
+on:
+ # Runs on Every Push
+ push:
+ # Runs on Pull Requests
+ pull_request:
+
+jobs:
+ make_truck:
+ runs-on: ubuntu-latest
+ steps:
+ - uses: actions/checkout@v2
+ with:
+ submodules: 'true'
+
+ - name: Set up QEMU
+ uses: docker/setup-qemu-action@v1
+
+ - name: Set up Docker Buildx
+ uses: docker/setup-buildx-action@v1
+
+ - name: Install The PDK
+ run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/pdkBuild.sh
+ env:
+ OPENLANE_TAG: v0.12
+
+ - name: Run make truck
+ run: bash ${GITHUB_WORKSPACE}/.github/scripts/build/run-truck.sh
+ env:
+ OPENLANE_TAG: v0.12
+
+ set_user_id:
+ runs-on: ubuntu-latest
+ steps:
+ - uses: actions/checkout@v2
+ with:
+ submodules: 'true'
+
+ - name: Set up QEMU
+ uses: docker/setup-qemu-action@v1
+
+ - name: Set up Docker Buildx
+ uses: docker/setup-buildx-action@v1
+
+ - name: Install The PDK
+ run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/pdkBuild.sh
+ env:
+ OPENLANE_TAG: v0.12
+
+ - name: Run Set User ID
+ run: bash ${GITHUB_WORKSPACE}/.github/scripts/build/run-set-id.sh
+ env:
+ OPENLANE_TAG: v0.12
+
+ xor_wrapper:
+ runs-on: ubuntu-latest
+ steps:
+ - uses: actions/checkout@v2
+ with:
+ submodules: 'true'
+
+ - name: Set up QEMU
+ uses: docker/setup-qemu-action@v1
+
+ - name: Set up Docker Buildx
+ uses: docker/setup-buildx-action@v1
+
+ - name: Install The PDK
+ run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/pdkBuild.sh
+ env:
+ OPENLANE_TAG: v0.12
+
+ - name: Run XOR Check
+ run: bash ${GITHUB_WORKSPACE}/.github/scripts/build/run-xor.sh
+ env:
+ OPENLANE_TAG: v0.12
diff --git a/.github/workflows/user_project_ci.yml b/.github/workflows/user_project_ci.yml
new file mode 100644
index 0000000..15a4916
--- /dev/null
+++ b/.github/workflows/user_project_ci.yml
@@ -0,0 +1,99 @@
+name: UPRJ_CI
+
+
+on:
+ # Runs on Every Push
+ push:
+ # Runs on Pull Requests
+ pull_request:
+
+jobs:
+ precheck:
+ runs-on: ubuntu-latest
+ timeout-minutes: 720
+ steps:
+ - uses: actions/checkout@v2
+ with:
+ submodules: 'true'
+
+ - name: Set up QEMU
+ uses: docker/setup-qemu-action@v1
+
+ - name: Set up Docker Buildx
+ uses: docker/setup-buildx-action@v1
+
+ - name: Install The Precheck
+ run: sh ${GITHUB_WORKSPACE}/.github/scripts/precheck/precheckBuild.sh
+
+ - name: Run The Precheck
+ run: bash ${GITHUB_WORKSPACE}/.github/scripts/precheck/run-precheck.sh
+
+ precheck-drc:
+ timeout-minutes: 720
+ runs-on: ubuntu-latest
+ steps:
+ - uses: actions/checkout@v2
+ with:
+ submodules: 'true'
+
+ - name: Set up QEMU
+ uses: docker/setup-qemu-action@v1
+
+ - name: Set up Docker Buildx
+ uses: docker/setup-buildx-action@v1
+
+ - name: Install The Precheck
+ run: sh ${GITHUB_WORKSPACE}/.github/scripts/precheck/precheckBuild.sh
+
+ - name: Run The Precheck
+ run: bash ${GITHUB_WORKSPACE}/.github/scripts/precheck/run-precheck-drc.sh
+
+ dv_rtl:
+ runs-on: ubuntu-latest
+ steps:
+ - uses: actions/checkout@v2
+ with:
+ submodules: 'true'
+
+ - name: Set up QEMU
+ uses: docker/setup-qemu-action@v1
+
+ - name: Set up Docker Buildx
+ uses: docker/setup-buildx-action@v1
+
+ - name: Install The PDK
+ run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/pdkBuild.sh
+ env:
+ OPENLANE_TAG: v0.12
+
+ - name: Install The Dockerized DV Setup
+ run: docker pull efabless/dv_setup:latest
+
+ - name: Run DV tests
+ # Run test number 0,1,2,3,4 in one job <test-ids> <sim-mode>
+ run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/run-dv-wrapper.sh 0 RTL
+
+ # dv_gl:
+ # runs-on: ubuntu-latest
+ # steps:
+ # - uses: actions/checkout@v2
+ # with:
+ # submodules: 'true'
+
+ # - name: Set up QEMU
+ # uses: docker/setup-qemu-action@v1
+
+ # - name: Set up Docker Buildx
+ # uses: docker/setup-buildx-action@v1
+
+ # - name: Install The PDK
+ # run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/pdkBuild.sh
+ # env:
+ # OPENLANE_TAG: v0.12
+
+ # - name: Install The Dockerized DV Setup
+ # run: docker pull efabless/dv_setup:latest
+
+ # - name: Run DV tests
+ # # Run test number 0,1,2,3,4 in one job <test-ids> <sim-mode>
+ # run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/run-dv-wrapper.sh 0,1,2,3,4 GL
\ No newline at end of file
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..c73b442
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "caravel-lite"]
+ path = caravel
+ url = https://github.com/efabless/caravel-lite
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..261eeb9
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,201 @@
+ Apache License
+ Version 2.0, January 2004
+ http://www.apache.org/licenses/
+
+ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+ 1. Definitions.
+
+ "License" shall mean the terms and conditions for use, reproduction,
+ and distribution as defined by Sections 1 through 9 of this document.
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+ "Licensor" shall mean the copyright owner or entity authorized by
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+
+ "Legal Entity" shall mean the union of the acting entity and all
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+ "You" (or "Your") shall mean an individual or Legal Entity
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+
+ "Work" shall mean the work of authorship, whether in Source or
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+ "Derivative Works" shall mean any work, whether in Source or Object
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+ editorial revisions, annotations, elaborations, or other modifications
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+ the Work and Derivative Works thereof.
+
+ "Contribution" shall mean any work of authorship, including
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+ "Contributor" shall mean Licensor and any individual or Legal Entity
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+
+ (a) You must give any other recipients of the Work or
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+ (b) You must cause any modified files to carry prominent notices
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+ (c) You must retain, in the Source form of any Derivative Works
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+ You may add Your own copyright statement to Your modifications and
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+ for use, reproduction, or distribution of Your modifications, or
+ for any such Derivative Works as a whole, provided Your use,
+ reproduction, and distribution of the Work otherwise complies with
+ the conditions stated in this License.
+
+ 5. Submission of Contributions. Unless You explicitly state otherwise,
+ any Contribution intentionally submitted for inclusion in the Work
+ by You to the Licensor shall be under the terms and conditions of
+ this License, without any additional terms or conditions.
+ Notwithstanding the above, nothing herein shall supersede or modify
+ the terms of any separate license agreement you may have executed
+ with Licensor regarding such Contributions.
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+ 6. Trademarks. This License does not grant permission to use the trade
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+ origin of the Work and reproducing the content of the NOTICE file.
+
+ 7. Disclaimer of Warranty. Unless required by applicable law or
+ agreed to in writing, Licensor provides the Work (and each
+ Contributor provides its Contributions) on an "AS IS" BASIS,
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+ risks associated with Your exercise of permissions under this License.
+
+ 8. Limitation of Liability. In no event and under no legal theory,
+ whether in tort (including negligence), contract, or otherwise,
+ unless required by applicable law (such as deliberate and grossly
+ negligent acts) or agreed to in writing, shall any Contributor be
+ liable to You for damages, including any direct, indirect, special,
+ incidental, or consequential damages of any character arising as a
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+ 9. Accepting Warranty or Additional Liability. While redistributing
+ the Work or Derivative Works thereof, You may choose to offer,
+ and charge a fee for, acceptance of support, warranty, indemnity,
+ or other liability obligations and/or rights consistent with this
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+ on Your own behalf and on Your sole responsibility, not on behalf
+ of any other Contributor, and only if You agree to indemnify,
+ defend, and hold each Contributor harmless for any liability
+ incurred by, or claims asserted against, such Contributor by reason
+ of your accepting any such warranty or additional liability.
+
+ END OF TERMS AND CONDITIONS
+
+ APPENDIX: How to apply the Apache License to your work.
+
+ To apply the Apache License to your work, attach the following
+ boilerplate notice, with the fields enclosed by brackets "[]"
+ replaced with your own identifying information. (Don't include
+ the brackets!) The text should be enclosed in the appropriate
+ comment syntax for the file format. We also recommend that a
+ file or class name and description of purpose be included on the
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+ Copyright [yyyy] [name of copyright owner]
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+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..5208b61
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,179 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CARAVEL_ROOT?=$(PWD)/caravel
+PRECHECK_ROOT?=${HOME}/open_mpw_precheck
+SIM ?= RTL
+
+# Install lite version of caravel, (1): caravel-lite, (0): caravel
+CARAVEL_LITE?=1
+
+ifeq ($(CARAVEL_LITE),1)
+ CARAVEL_NAME := caravel-lite
+ CARAVEL_REPO := https://github.com/efabless/caravel-lite
+ CARAVEL_BRANCH := main
+else
+ CARAVEL_NAME := caravel
+ CARAVEL_REPO := https://github.com/efabless/caravel
+ CARAVEL_BRANCH := master
+endif
+
+# Install caravel as submodule, (1): submodule, (0): clone
+SUBMODULE?=1
+
+# Include Caravel Makefile Targets
+.PHONY: %
+%:
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
+
+# Verify Target for running simulations
+.PHONY: verify
+verify:
+ cd ./verilog/dv/ && \
+ export SIM=${SIM} && \
+ $(MAKE) -j$(THREADS)
+
+# Install DV setup
+.PHONY: simenv
+simenv:
+ docker pull efabless/dv_setup:latest
+
+PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+TARGET_PATH=$(shell pwd)
+PDK_PATH=${PDK_ROOT}/sky130A
+VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+$(DV_PATTERNS): verify-% : ./verilog/dv/%
+ docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_PATH}:${PDK_PATH} \
+ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+ -e TARGET_PATH=${TARGET_PATH} -e PDK_PATH=${PDK_PATH} \
+ -e CARAVEL_ROOT=${CARAVEL_ROOT} \
+ -u $(id -u $$USER):$(id -g $$USER) efabless/dv_setup:latest \
+ sh -c $(VERIFY_COMMAND)
+
+# Openlane Makefile Targets
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+.PHONY: $(BLOCKS)
+$(BLOCKS): %:
+ cd openlane && $(MAKE) $*
+
+# Install caravel
+.PHONY: install
+install:
+ifeq ($(SUBMODULE),1)
+ @echo "Installing $(CARAVEL_NAME) as a submodule.."
+# Convert CARAVEL_ROOT to relative path because .gitmodules doesn't accept '/'
+ $(eval CARAVEL_PATH := $(shell realpath --relative-to=$(shell pwd) $(CARAVEL_ROOT)))
+ @if [ ! -d $(CARAVEL_ROOT) ]; then git submodule add --name $(CARAVEL_NAME) $(CARAVEL_REPO) $(CARAVEL_PATH); fi
+ @git submodule update --init
+ @cd $(CARAVEL_ROOT); git checkout $(CARAVEL_BRANCH)
+ $(MAKE) simlink
+else
+ @echo "Installing $(CARAVEL_NAME).."
+ @git clone $(CARAVEL_REPO) $(CARAVEL_ROOT)
+ @cd $(CARAVEL_ROOT); git checkout $(CARAVEL_BRANCH)
+endif
+
+# Create symbolic links to caravel's main files
+.PHONY: simlink
+simlink: check-caravel
+### Symbolic links relative path to $CARAVEL_ROOT
+ $(eval MAKEFILE_PATH := $(shell realpath --relative-to=openlane $(CARAVEL_ROOT)/openlane/Makefile))
+ mkdir -p openlane
+ cd openlane &&\
+ ln -sf $(MAKEFILE_PATH) Makefile
+
+# Update Caravel
+.PHONY: update_caravel
+update_caravel: check-caravel
+ifeq ($(SUBMODULE),1)
+ @git submodule update --init --recursive
+ cd $(CARAVEL_ROOT) && \
+ git checkout $(CARAVEL_BRANCH) && \
+ git pull
+else
+ cd $(CARAVEL_ROOT)/ && \
+ git checkout $(CARAVEL_BRANCH) && \
+ git pull
+endif
+
+# Uninstall Caravel
+.PHONY: uninstall
+uninstall:
+ifeq ($(SUBMODULE),1)
+ git config -f .gitmodules --remove-section "submodule.$(CARAVEL_NAME)"
+ git add .gitmodules
+ git submodule deinit -f $(CARAVEL_ROOT)
+ git rm --cached $(CARAVEL_ROOT)
+ rm -rf .git/modules/$(CARAVEL_NAME)
+ rm -rf $(CARAVEL_ROOT)
+else
+ rm -rf $(CARAVEL_ROOT)
+endif
+
+# Install Openlane
+.PHONY: openlane
+openlane:
+ cd openlane && $(MAKE) openlane
+
+# Install Pre-check
+# Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
+.PHONY: precheck
+precheck:
+ @git clone https://github.com/efabless/open_mpw_precheck.git --depth=1 $(PRECHECK_ROOT)
+ @docker pull efabless/open_mpw_precheck:latest
+
+.PHONY: run-precheck
+run-precheck: check-precheck check-pdk check-caravel
+ rm -rf $(PWD)/checks
+ $(eval TARGET_PATH := $(shell pwd))
+ cd $(PRECHECK_ROOT) && \
+ docker run -e TARGET_PATH=$(TARGET_PATH) -e PDK_ROOT=$(PDK_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -v $(PRECHECK_ROOT):/usr/local/bin -v $(TARGET_PATH):$(TARGET_PATH) -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/open_mpw_precheck:latest bash -c "python3 open_mpw_prechecker.py --pdk_root $(PDK_ROOT) --target_path $(TARGET_PATH) -rfc -c $(CARAVEL_ROOT)"
+
+# Install PDK using OL's Docker Image
+.PHONY: pdk-nonnative
+pdk-nonnative: skywater-pdk skywater-library skywater-timing open_pdks
+ docker run --rm -v $(PDK_ROOT):$(PDK_ROOT) -v $(pwd):/user_project -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -e PDK_ROOT=$(PDK_ROOT) -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/openlane:current sh -c "cd $(CARAVEL_ROOT); make build-pdk; make gen-sources"
+
+# Clean
+.PHONY: clean
+clean:
+ cd ./verilog/dv/ && \
+ $(MAKE) -j$(THREADS) clean
+
+check-caravel:
+ @if [ ! -d "$(CARAVEL_ROOT)" ]; then \
+ echo "Caravel Root: "$(CARAVEL_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-precheck:
+ @if [ ! -d "$(PRECHECK_ROOT)" ]; then \
+ echo "Pre-check Root: "$(PRECHECK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-pdk:
+ @if [ ! -d "$(PDK_ROOT)" ]; then \
+ echo "PDK Root: "$(PDK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+.PHONY: help
+help:
+ cd $(CARAVEL_ROOT) && $(MAKE) help
+ @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..5e01221
--- /dev/null
+++ b/README.md
@@ -0,0 +1,18 @@
+# Caravel Analog User
+
+[](https://opensource.org/licenses/Apache-2.0) [](https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml) [](https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml)
+
+---
+
+| :exclamation: Important Note |
+|-----------------------------------------|
+
+## Please fill in your project documentation in this README.md file
+
+
+:warning: | Use this sample project for analog user projects.
+:---: | :---
+
+---
+
+Refer to [README](docs/source/index.rst) for this sample project documentation.
diff --git a/caravel b/caravel
new file mode 160000
index 0000000..13f2590
--- /dev/null
+++ b/caravel
@@ -0,0 +1 @@
+Subproject commit 13f2590e4b3a74b910dac56a6b757f5a66fd5212
diff --git a/docs/Makefile b/docs/Makefile
new file mode 100644
index 0000000..c715218
--- /dev/null
+++ b/docs/Makefile
@@ -0,0 +1,37 @@
+
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line, and also
+# from the environment for the first two.
+SPHINXOPTS ?=
+SPHINXBUILD ?= sphinx-build
+SOURCEDIR = source
+BUILDDIR = build
+
+# Put it first so that "make" without argument is like "make help".
+help:
+ @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+ @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
diff --git a/docs/environment.yml b/docs/environment.yml
new file mode 100644
index 0000000..2bddf94
--- /dev/null
+++ b/docs/environment.yml
@@ -0,0 +1,23 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+name: caravel-docs
+channels:
+- defaults
+dependencies:
+- python>=3.8
+- pip:
+ - -r file:requirements.txt
diff --git a/docs/requirements.txt b/docs/requirements.txt
new file mode 100644
index 0000000..f5c5383
--- /dev/null
+++ b/docs/requirements.txt
@@ -0,0 +1,6 @@
+git+https://github.com/SymbiFlow/sphinx_materialdesign_theme.git#egg=sphinx-symbiflow-theme
+
+docutils
+sphinx
+sphinx-autobuild
+sphinxcontrib-wavedrom
diff --git a/docs/source/conf.py b/docs/source/conf.py
new file mode 100644
index 0000000..f960f13
--- /dev/null
+++ b/docs/source/conf.py
@@ -0,0 +1,89 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Configuration file for the Sphinx documentation builder.
+#
+# This file only contains a selection of the most common options. For a full
+# list see the documentation:
+# https://www.sphinx-doc.org/en/master/usage/configuration.html
+
+# -- Path setup --------------------------------------------------------------
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+#
+# import os
+# import sys
+# sys.path.insert(0, os.path.abspath('.'))
+
+
+# -- Project information -----------------------------------------------------
+
+project = 'CIIC Harness'
+copyright = '2020, efabless'
+author = 'efabless'
+
+
+# -- General configuration ---------------------------------------------------
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = [
+ 'sphinxcontrib.wavedrom',
+ 'sphinx.ext.mathjax',
+ 'sphinx.ext.todo'
+]
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+# This pattern also affects html_static_path and html_extra_path.
+exclude_patterns = [
+ 'build',
+ 'Thumbs.db',
+ # Files included in other rst files.
+ 'introduction.rst',
+]
+
+
+# -- Options for HTML output -------------------------------------------------
+"""
+html_theme_options = {
+ 'header_links' : [
+ ("Home", 'index', False, 'home'),
+ ("GitHub", "https://github.com/efabless/caravel", True, 'code'),
+ ],
+ 'hide_symbiflow_links': True,
+ 'license_url' : 'https://www.apache.org/licenses/LICENSE-2.0',
+}
+"""
+# The theme to use for HTML and HTML Help pages. See the documentation for
+# a list of builtin themes.
+#
+html_theme = 'sphinx_rtd_theme'
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+html_static_path = ['_static']
+
+todo_include_todos = False
+
+numfig = True
diff --git a/docs/source/index.rst b/docs/source/index.rst
new file mode 100644
index 0000000..a5a9e4c
--- /dev/null
+++ b/docs/source/index.rst
@@ -0,0 +1,328 @@
+.. raw:: html
+
+ <!---
+ # SPDX-FileCopyrightText: 2020 Efabless Corporation
+ #
+ # Licensed under the Apache License, Version 2.0 (the "License");
+ # you may not use this file except in compliance with the License.
+ # You may obtain a copy of the License at
+ #
+ # http://www.apache.org/licenses/LICENSE-2.0
+ #
+ # Unless required by applicable law or agreed to in writing, software
+ # distributed under the License is distributed on an "AS IS" BASIS,
+ # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ # See the License for the specific language governing permissions and
+ # limitations under the License.
+ #
+ # SPDX-License-Identifier: Apache-2.0
+ -->
+
+Caravel Analog User Project
+===========================
+
+|License| |User CI| |Caravan Build|
+
+Table of contents
+=================
+
+- `Overview <#overview>`__
+- `Install Caravel <#install-caravel>`__
+- `Caravel Integration <#caravel-integration>`__
+
+ - `User Project: Power on Reset <#user-project-power-on-reset>`_
+ - `Verilog Integration <#verilog-integration>`__
+
+- `Running Full Chip Simulation <#running-full-chip-simulation>`__
+- `Analog Design Flow <#analog-design-flow>`__
+- `Other Miscellaneous Targets <#other-miscellaneous-targets>`_
+- `Checklist for Open-MPW
+ Submission <#checklist-for-open-mpw-submission>`__
+
+Overview
+========
+
+This repo contains a sample user project that utilizes the caravan chip (analog version of `caravel <https://github.com/efabless/caravel.git>`__) user space. The user project is a simple power-on-reset that showcases how to make use of caravan's user space utilities like IO pads, logic analyzer probes, and wishbone port. The repo also demonstrates the recommended structure for the open-mpw **analog** projects.
+
+Install Caravel
+===============
+
+To setup caravel, run the following:
+
+.. code:: bash
+
+ # By default, CARAVEL_ROOT is set to $(pwd)/caravel
+ # If you want to install caravel at a different location, run "export CARAVEL_ROOT=<caravel-path>"
+ # Disable submodule installation if needed by, run "export SUBMODULE=0"
+
+ git clone https://github.com/efabless/caravel_user_project_analog.git
+ cd caravel_user_project_analog
+ make install
+
+To update the installed caravel to the latest, run:
+
+.. code:: bash
+
+ make update_caravel
+
+To remove caravel, run
+
+.. code:: bash
+
+ make uninstall
+
+By default
+`caravel-lite <https://github.com/efabless/caravel-lite.git>`__ is
+installed. To install the full version of caravel, run this prior to
+calling make install.
+
+.. code:: bash
+
+ export CARAVEL_LITE=0
+
+Caravel Integration
+=====================
+
+
+User Project: Power on Reset
+----------------------------
+
+This is an example user analog project which breaks out the power-on-reset
+circuit used by the management SoC for power-up behavior so that the circuit
+input and output can be independently controlled and measured.
+
+The power-on-reset circuit itself is a simple, non-temperature-compensated
+analog delay calibrated to 15ms under nominal conditions, with a Schmitt
+trigger inverter to provide hysteresis around the trigger point to provide
+a clean output reset signal.
+
+The circuit provides a single high-voltage (3.3V domain) sense-inverted reset
+signal "porb_h" and complementary low-voltage (1.8V domain) reset signals
+"por_l" and "porb_l".
+
+The only input to the circuit is the 3.3V domain power supply itself.
+
+
+Verilog Integration
+-------------------
+
+You need to create a wrapper around your macro that adheres to the
+template at
+`user\_analog_project\_wrapper <https://github.com/efabless/caravel/blob/master/verilog/rtl/__user_analog_project_wrapper.v>`__.
+The wrapper top module must be named ``user_analog_project_wrapper`` and must
+have the same input and output ports as the analog wrapper template. The wrapper gives access to the
+user space utilities provided by caravel like IO ports, logic analyzer
+probes, and wishbone bus connection to the management SoC.
+
+The verilog modules instantiated in the wrapper module should represent
+the analog project; they need not be more than empty blocks, but it is
+encouraged to write a simple behavioral description of the analog circuit
+in standard verilog, using real-valued wires when necessary. This allows
+the whole system to be run in a verilog testbench and verify the connectivity
+to the padframe and management SoC, even if the testbench C code does nothing
+more than set the mode of each GPIO pin. The example top-level verilog code
+emulates the behavior of the power-on-reset delay after applying a valid
+power supply to the circuit.
+
+
+Building the PDK
+================
+
+You have two options for building the pdk:
+
+- Build the pdk natively.
+
+Make sure you have `Magic VLSI Layout Tool <http://opencircuitdesign.com/magic/index.html>`__ `version 8.3.160 <https://github.com/RTimothyEdwards/magic/tree/8.3.160>`__ installed on your machine before building the pdk.
+
+.. code:: bash
+
+ # set PDK_ROOT to the path you wish to use for the pdk
+ export PDK_ROOT=<pdk-installation-path>
+
+ # you can optionally specify skywater-pdk and open-pdks commit used
+ # by setting and exporting SKYWATER_COMMIT and OPEN_PDKS_COMMIT
+ # if you do not set them, they default to the last verfied commits tested for this project
+
+ make pdk
+
+- Build the pdk using openlane's docker image which has magic installed.
+
+.. code:: bash
+
+ # set PDK_ROOT to the path you wish to use for the pdk
+ export PDK_ROOT=<pdk-installation-path>
+
+ # you can optionally specify skywater-pdk and open-pdks commit used
+ # by setting and exporting SKYWATER_COMMIT and OPEN_PDKS_COMMIT
+ # if you do not set them, they default to the last verfied commits tested for this project
+
+ make pdk-nonnative
+
+Running Full Chip Simulation
+============================
+
+First, you will need to install the simulation environment, by
+
+.. code:: bash
+
+ make simenv
+
+This will pull a docker image with the needed tools installed.
+
+To install the simulation environment locally, refer to `README <https://github.com/efabless/caravel_user_project_analog/blob/main/verilog/dv/README.md>`__
+
+Then, run the RTL and GL simulation by
+
+.. code:: bash
+
+ export PDK_ROOT=<pdk-installation-path>
+ export CARAVEL_ROOT=$(pwd)/caravel
+ # specify simulation mode: RTL/GL
+ export SIM=RTL
+ # Run the mprj_por testbench, make verify-mprj_por
+ make verify-<testbench-name>
+
+The verilog test-benches are under this directory
+`verilog/dv <https://github.com/efabless/caravel_user_project_analog/tree/main/verilog/dv>`__.
+
+
+Analog Design Flow
+===================
+
+The example project uses a very simple analog design flow with schematics
+made with xschem, simulation done using ngspice, layout done with magic,
+and LVS verification done with netgen. Sources for the power-on-reset
+circuit are in the "xschem/" directory, which also includes a schematic
+representing the wrapper with all of its ports, for use in a testbench
+circuit. There are several testbenches in the example, starting from
+tests of the component devices to a full test of the completed project
+inside the wrapper.
+
+There is no automation in this project; the schematic and layout were
+done by hand, including both the power-on-reset block and the power and
+signal routing to the pins on the wrapper.
+
+The power-on-reset circuit itself is simple and is not compensated for
+temperature or voltage variation. When the power supply reaches a
+sufficient level, the voltage divider sets the gate voltage on an nFET
+device to draw a current of nominally 240nA. The testbench
+"threshold_test_tb.spice" does a DC sweep to find the gate voltage that
+produces this value. Next, a cascaded current mirror divides down the
+current by a factor of (roughly) 400. The testbench current_test.spice
+checks the current division value. Finally, the output ~600pA from the
+end of the current mirror is accumulated on a capacitor until the value
+trips the input of the 3.3V Schmitt trigger buffer from the
+sky130_fd_sd_hvl library. The capacitor is sized to peg the nominal
+time to trigger at 15ms. The schematic "example_por_tb.sch" sets up
+the testbench for this timing test.
+
+The output of the Schmitt trigger buffer becomes the high-voltage
+output, and is input to a standard buffer and inverter used as
+level shifters from the 3.3V domain to the 1.8V domain, producing
+complementary low-voltage outputs.
+
+The user project is formed from two power-on-reset circuits, one of
+which is connected to the user area VDDA1 power supply, and the other
+of which is connected to one of the analog I/O pads, used as a power
+supply input and connected to its voltage ESD clamp circuit. The
+3.3V domain outputs are connected directly to GPIO pads through the
+ESD (150 ohm series) connection. The 1.8V domain outputs are connected
+to GPIO pads through the usual I/O connections, with the corresponding
+user output enable (sense inverted) held low to keep the output always
+active.
+
+The C code testbench is in "verilog/dv/mprj_por/mprj_por.c" and only
+sets the GPIO pins used to the correct state (user output function).
+The POR circuit outputs are monitored by the testbench verilog file
+"mprj_por_tb.v" which will fail if the connections are wrong or if
+the behavioral POR verilog does not work as intended.
+
+Note that to properly test this circuit, the GPIO pins have to be
+configured for output to be seen and measured, implying that the
+management SoC power supply must be stable and the C program running
+off of the SPI flash before the user area power supplies are raised.
+
+
+Running Open-MPW Precheck Locally
+=================================
+
+You can install the precheck by running
+
+.. code:: bash
+
+ # By default, this install the precheck in your home directory
+ # To change the installtion path, run "export PRECHECK_ROOT=<precheck installation path>"
+ make precheck
+
+This will clone the precheck repo and pull the latest precheck docker image.
+
+
+Then, you can run the precheck by running
+Specify CARAVEL_ROOT before running any of the following,
+
+.. code:: bash
+
+ # export CARAVEL_ROOT=$(pwd)/caravel
+ export CARAVEL_ROOT=<path-to-caravel>
+ make run-precheck
+
+This will run all the precheck checks on your project and will retain the logs under the ``checks`` directory.
+
+Other Miscellaneous Targets
+============================
+
+The makefile provides a number of useful that targets that can run compress, uncompress, and run XOR checks on your design.
+
+Compress gds files and any file larger than 100MB (GH file size limit),
+
+.. code:: bash
+
+ make compress
+
+Uncompress files,
+
+.. code:: bash
+
+ make uncompress
+
+
+Specify ``CARAVEL_ROOT`` before running any of the following,
+
+.. code:: bash
+
+ # export CARAVEL_ROOT=$(pwd)/caravel
+ export CARAVEL_ROOT=<path-to-caravel>
+
+Run XOR check,
+
+.. code:: bash
+
+ make xor-analog-wrapper
+
+Checklist for Open-MPW Submission
+=================================
+
+
+|:heavy_check_mark:| The project repo adheres to the same directory structure in this repo.
+
+|:heavy_check_mark:| The project repo contain info.yaml at the project root.
+
+|:heavy_check_mark:| Top level macro is named ``user_analog_project_wrapper``.
+
+|:heavy_check_mark:| Full Chip Simulation passes for RTL and GL (gate-level)
+
+|:heavy_check_mark:| The hardened Macros are LVS and DRC clean
+
+|:heavy_check_mark:| The ``user_analog_project_wrapper`` adheres to empty wrapper template order specified at `user_analog_project_wrapper_empty <https://github.com/efabless/caravel/blob/master/mag/user_analog_project_wrapper_empty.mag>`__
+
+|:heavy_check_mark:| XOR check passes with zero total difference.
+
+|:heavy_check_mark:| Open-MPW-Precheck tool runs successfully.
+
+
+.. |License| image:: https://img.shields.io/badge/License-Apache%202.0-blue.svg
+ :target: https://opensource.org/licenses/Apache-2.0
+.. |User CI| image:: https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml/badge.svg
+ :target: https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml
+.. |Caravan Build| image:: https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml/badge.svg
+ :target: https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml
diff --git a/gds/antenna_on_gds.tcl b/gds/antenna_on_gds.tcl
new file mode 100644
index 0000000..5f379c6
--- /dev/null
+++ b/gds/antenna_on_gds.tcl
@@ -0,0 +1,28 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+gds read $::env(DESIGN_IN_ANTENNA).gds
+select top cell
+extract do local
+extract no capacitance
+extract no coupling
+extract no resistance
+extract no adjust
+extract unique
+# extract warn all
+extract
+feedback save ./tmp/$::env(DESIGN_IN_ANTENNA)_ext2spice.antenna.feedback.txt
+antennacheck debug
+antennacheck
diff --git a/gds/drc_on_gds.tcl b/gds/drc_on_gds.tcl
new file mode 100644
index 0000000..8bb3035
--- /dev/null
+++ b/gds/drc_on_gds.tcl
@@ -0,0 +1,61 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+gds read $::env(DESIGN_IN_DRC).gds
+set fout [open ./tmp/$::env(DESIGN_IN_DRC).drc w]
+set oscale [cif scale out]
+set cell_name $::env(DESIGN_IN_DRC)
+magic::suspendall
+puts stdout "\[INFO\]: Loading $::env(DESIGN_IN_DRC)\n"
+flush stdout
+load $::env(DESIGN_IN_DRC)
+select top cell
+drc euclidean on
+drc style drc(full)
+drc check
+set drcresult [drc listall why]
+set count 0
+puts $fout "$::env(DESIGN_IN_DRC)"
+puts $fout "----------------------------------------"
+foreach {errtype coordlist} $drcresult {
+ puts $fout $errtype
+ puts $fout "----------------------------------------"
+ foreach coord $coordlist {
+ set bllx [expr {$oscale * [lindex $coord 0]}]
+ set blly [expr {$oscale * [lindex $coord 1]}]
+ set burx [expr {$oscale * [lindex $coord 2]}]
+ set bury [expr {$oscale * [lindex $coord 3]}]
+ set coords [format " %.3f %.3f %.3f %.3f" $bllx $blly $burx $bury]
+ puts $fout "$coords"
+ set count [expr {$count + 1} ]
+ }
+ puts $fout "----------------------------------------"
+}
+
+puts $fout "\[INFO\]: COUNT: $count"
+puts $fout "\[INFO\]: Should be divided by 3 or 4"
+
+puts $fout ""
+close $fout
+
+puts stdout "\[INFO\]: COUNT: $count"
+puts stdout "\[INFO\]: Should be divided by 3 or 4"
+puts stdout "\[INFO\]: DRC Checking DONE (./tmp/$::env(DESIGN_IN_DRC).drc)"
+flush stdout
+
+puts stdout "\[INFO\]: Saving mag view with DRC errors(./tmp/$::env(DESIGN_IN_DRC).drc.mag)"
+# WARNING: changes the name of the cell; keep as last step
+save ./tmp/$::env(DESIGN_IN_DRC).drc.drc.mag
+puts stdout "\[INFO\]: Saved"
diff --git a/gds/gds2mag-all.sh b/gds/gds2mag-all.sh
new file mode 100644
index 0000000..b9ca6f2
--- /dev/null
+++ b/gds/gds2mag-all.sh
@@ -0,0 +1,34 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+
+gunzip *.gz
+mv sram_1rw1r_32_256_8_sky130_lp1.gds sram_1rw1r_32_256_8_sky130.gds
+
+o-gds2mag-mag.sh simple_por.gds
+o-gds2mag-mag.sh gpio_control_block.gds
+o-gds2mag-mag.sh digital_pll.gds
+o-gds2mag-mag.sh storage.gds
+o-gds2mag-mag.sh mgmt_core.gds
+o-gds2mag-mag.sh chip_io.gds
+o-gds2mag-mag.sh sram_1rw1r_32_256_8_sky130.gds
+
+mv -f *.mag ../mag
+
+gzip -9 storage.gds mgmt_core.gds chip_io.gds
+
+
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
new file mode 100644
index 0000000..f0959a4
--- /dev/null
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/gds/user_analog_project_wrapper_empty.gds.gz b/gds/user_analog_project_wrapper_empty.gds.gz
new file mode 100644
index 0000000..1e3d18e
--- /dev/null
+++ b/gds/user_analog_project_wrapper_empty.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper_empty.gds.gz b/gds/user_project_wrapper_empty.gds.gz
new file mode 100644
index 0000000..53e60a7
--- /dev/null
+++ b/gds/user_project_wrapper_empty.gds.gz
Binary files differ
diff --git a/info.yaml b/info.yaml
new file mode 100644
index 0000000..6dec21d
--- /dev/null
+++ b/info.yaml
@@ -0,0 +1,19 @@
+ ---
+project:
+ description: "An analog implementation of the artificial neuron used in Machine Learning"
+ foundry: "SkyWater"
+ git_url: "https://github.com/lakshmi-sathi/Analog-Neural-Network.git"
+ organization: "Gatech"
+ organization_url: "http://gatech.edu"
+ owner: "Lakshmi S"
+ process: "SKY130"
+ project_name: "Analog Neuron"
+ project_id: "00000000"
+ tags:
+ - "Open MPW"
+ - "Test Harness"
+ category: "Test Harness"
+ top_level_netlist: "caravel/verilog/gl/caravan.v"
+ user_level_netlist: "verilog/rtl/user_analog_project_wrapper.v"
+ version: "1.00"
+ cover_image: "docs/source/_static/caravel_harness.png"
diff --git a/mag/.magicrc b/mag/.magicrc
new file mode 100644
index 0000000..c91aa27
--- /dev/null
+++ b/mag/.magicrc
@@ -0,0 +1,86 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Turn off the scale option on ext2spice or else it conflicts with the
+# scale in the model files.
+ext2spice scale off
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "/mnt/c/Users/LENOVO/Documents/PLL/PDK_b_latest/open_pdks/sky130/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/current/sky130A.tech
+
+# load device generator
+source $PDKPATH/libs.tech/magic/current/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/current/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/mag/Stage1_inv.mag b/mag/Stage1_inv.mag
new file mode 100644
index 0000000..0e356e1
--- /dev/null
+++ b/mag/Stage1_inv.mag
@@ -0,0 +1,1418 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627987662
+<< nwell >>
+rect 124 792 188 1230
+rect 316 792 380 1230
+rect 508 792 572 1230
+rect 700 792 764 1230
+rect 892 792 956 1230
+rect 1084 792 1148 1230
+rect 1276 792 1340 1230
+rect 1468 792 1532 1230
+rect 1660 792 1724 1230
+rect 124 114 188 552
+rect 316 114 380 552
+rect 508 114 572 552
+rect 700 114 764 552
+rect 892 114 956 552
+rect 1084 114 1148 552
+rect 1276 114 1340 552
+rect 1468 114 1532 552
+rect 1660 114 1724 552
+<< pdiff >>
+rect 124 1221 188 1230
+rect 124 803 140 1221
+rect 174 803 188 1221
+rect 124 792 188 803
+rect 316 1221 380 1230
+rect 316 803 332 1221
+rect 366 803 380 1221
+rect 316 792 380 803
+rect 508 1221 572 1230
+rect 508 803 524 1221
+rect 558 803 572 1221
+rect 508 792 572 803
+rect 700 1221 764 1230
+rect 700 803 716 1221
+rect 750 803 764 1221
+rect 700 792 764 803
+rect 892 1221 956 1230
+rect 892 803 908 1221
+rect 942 803 956 1221
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+use sky130_fd_pr__pfet_01v8_VNEHM9 sky130_fd_pr__pfet_01v8_VNEHM9_0
+timestamp 1627668659
+transform 1 0 925 0 1 673
+box -1031 -779 1031 779
+use sky130_fd_pr__nfet_01v8_BBTBMZ sky130_fd_pr__nfet_01v8_BBTBMZ_0
+timestamp 1627668659
+transform 1 0 929 0 1 -641
+box -1031 -511 1031 511
+<< labels >>
+rlabel metal3 1934 -200 1986 -36 1 out
+port 3 n
+rlabel metal2 -100 1480 1946 1582 1 VDD
+port 4 n
+rlabel metal2 -94 -1278 1952 -1176 1 GND
+port 2 n
+rlabel metal1 -160 -220 -16 -16 1 in
+port 5 n
+<< end >>
diff --git a/mag/Stage2_inv.mag b/mag/Stage2_inv.mag
new file mode 100644
index 0000000..0c24b67
--- /dev/null
+++ b/mag/Stage2_inv.mag
@@ -0,0 +1,195 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628045315
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+rect 1058 174 1064 538
+rect 996 170 1004 174
+rect 1056 170 1064 174
+rect 996 160 1064 170
+rect -58 -170 1300 -66
+<< via2 >>
+rect 180 172 232 556
+rect 232 172 236 556
+rect 618 174 620 540
+rect 620 174 672 540
+rect 672 174 674 540
+rect 810 174 812 540
+rect 812 174 864 540
+rect 864 174 866 540
+rect 1002 174 1004 538
+rect 1004 174 1056 538
+rect 1056 174 1058 538
+<< metal3 >>
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+rect 172 304 180 556
+rect 174 172 180 304
+rect 236 212 250 556
+rect 612 540 682 550
+rect 804 540 872 550
+rect 612 212 618 540
+rect 236 174 618 212
+rect 674 306 684 540
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+rect 674 212 682 306
+rect 804 212 810 306
+rect 674 174 810 212
+rect 866 212 872 540
+rect 996 538 1064 550
+rect 994 212 1002 538
+rect 866 174 1002 212
+rect 1058 350 1064 538
+rect 1058 212 1068 350
+rect 1058 174 1308 212
+rect 236 172 1308 174
+rect 174 118 1308 172
+rect 174 116 1292 118
+use sky130_fd_pr__nfet_01v8_LW2HKK sky130_fd_pr__nfet_01v8_LW2HKK_0
+timestamp 1627668659
+transform 1 0 161 0 1 670
+box -211 -730 211 730
+use sky130_fd_pr__pfet_01v8_27F7GK sky130_fd_pr__pfet_01v8_27F7GK_0
+timestamp 1627668659
+transform 1 0 837 0 1 661
+box -455 -719 455 719
+<< labels >>
+rlabel metal1 -102 32 -28 120 1 in
+port 3 n
+rlabel metal2 -54 -164 1294 -72 1 vl
+port 9 n
+rlabel locali -32 -40 40 4 1 nbody
+port 10 n
+rlabel metal2 -44 1430 1302 1524 1 vh
+port 8 n
+rlabel metal3 1208 122 1304 208 1 out
+port 11 n
+<< end >>
diff --git a/mag/analogneuron_invopamp_re_15kfeedbck.mag b/mag/analogneuron_invopamp_re_15kfeedbck.mag
new file mode 100644
index 0000000..f9017b3
--- /dev/null
+++ b/mag/analogneuron_invopamp_re_15kfeedbck.mag
@@ -0,0 +1,290 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628079258
+<< pwell >>
+rect 10446 320 10450 334
+<< locali >>
+rect 2558 1138 2565 1160
+rect 2479 1125 2513 1129
+rect 2527 1125 2561 1131
+rect 2479 1012 2561 1125
+rect 2190 978 2561 1012
+rect 4392 878 6400 1768
+rect 8149 200 8369 234
+rect 8165 173 8369 200
+rect 8335 102 8369 173
+rect 8334 18 8530 102
+<< viali >>
+rect 126 726 224 1630
+<< metal1 >>
+rect 2316 2400 2960 2430
+rect 2316 2374 3294 2400
+rect 134 1650 236 1654
+rect 108 1632 236 1650
+rect 108 1630 270 1632
+rect 108 1108 126 1630
+rect -1354 382 -932 776
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+rect 2386 1270 2456 1432
+rect 4246 1943 4300 1992
+rect 4429 1943 4483 1989
+rect 4623 1943 4677 1981
+rect 4823 1943 4877 1991
+rect 5011 1943 5065 1969
+rect 5207 1943 5261 1963
+rect 5387 1943 5441 1985
+rect 5583 1943 5637 1975
+rect 5779 1943 5833 1965
+rect 5975 1943 6029 1967
+rect 6155 1943 6209 1975
+rect 6355 1970 6409 1971
+rect 6551 1970 6605 1981
+rect 6260 1943 6610 1970
+rect 6739 1943 6793 1973
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+<< via1 >>
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+rect 2455 2560 4030 2680
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+<< metal3 >>
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+rect 4068 1626 4108 1742
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+rect 8208 1626 8264 1688
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+rect -10 -51 166 -46
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+<< via3 >>
+rect 0 -46 156 238
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+rect 10540 -30 10668 232
+<< metal4 >>
+rect -15 238 10686 244
+rect -15 -46 0 238
+rect 156 232 10686 238
+rect 156 230 10540 232
+rect 156 -46 6912 230
+rect -15 -48 6912 -46
+rect 7948 -30 10540 230
+rect 10668 -30 10686 232
+rect 7948 -48 10686 -30
+rect -15 -54 10686 -48
+use sky130_fd_pr__res_xhigh_po_0p35_NZHUVC sky130_fd_pr__res_xhigh_po_0p35_NZHUVC_2
+timestamp 1627748178
+transform 0 1 -840 -1 0 93
+box -37 -508 37 508
+use sky130_fd_pr__res_xhigh_po_0p35_NZHUVC sky130_fd_pr__res_xhigh_po_0p35_NZHUVC_1
+timestamp 1627748178
+transform 0 1 -844 -1 0 423
+box -37 -508 37 508
+use sky130_fd_pr__res_xhigh_po_0p35_NZHUVC sky130_fd_pr__res_xhigh_po_0p35_NZHUVC_0
+timestamp 1627748178
+transform 0 1 -842 -1 0 741
+box -37 -508 37 508
+use Stage1_inv Stage1_inv_0
+timestamp 1627987662
+transform 1 0 362 0 1 1178
+box -166 -1292 1986 1598
+use Stage1_inv Stage1_inv_1
+timestamp 1627987662
+transform -1 0 10370 0 1 1184
+box -166 -1292 1986 1598
+use biasnmos biasnmos_0
+timestamp 1627800883
+transform 1 0 2416 0 1 90
+box -106 -320 4260 833
+use Stage2_inv Stage2_inv_1
+timestamp 1628045315
+transform -1 0 8210 0 1 224
+box -102 -170 1308 1530
+use Stage2_inv Stage2_inv_0
+timestamp 1628045315
+transform 1 0 2512 0 1 1150
+box -102 -170 1308 1530
+use biaspmos biaspmos_0
+timestamp 1627991837
+transform 1 0 4116 0 1 3370
+box -52 -1706 4314 -516
+<< labels >>
+rlabel metal1 10448 716 10622 1604 1 in2
+port 4 n
+rlabel metal2 78 2790 10680 2896 1 VDD
+port 1 n
+rlabel metal1 126 728 222 1632 1 in1
+port 6 n
+rlabel metal1 -748 722 100 1096 1 in
+port 7 n
+rlabel metal3 10526 -62 10694 254 1 out
+port 8 n
+rlabel metal2 254 -222 10880 -110 1 GND
+port 9 n
+<< end >>
diff --git a/mag/aninv_.mag b/mag/aninv_.mag
new file mode 100644
index 0000000..22cb1fb
--- /dev/null
+++ b/mag/aninv_.mag
@@ -0,0 +1,185 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628080314
+<< poly >>
+rect 1196 371 1226 429
+rect 1143 367 1226 371
+rect 1127 341 1226 367
+rect 247 -342 277 -281
+rect 247 -372 318 -342
+<< viali >>
+rect 464 1464 1288 1522
+rect 47 -597 1691 -525
+<< metal1 >>
+rect 452 1522 1300 1528
+rect 452 1464 464 1522
+rect 1288 1464 1300 1522
+rect 452 1458 1300 1464
+rect 1425 1378 1548 1383
+rect 606 1332 1548 1378
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+rect 448 -242 458 -190
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+rect 944 -340 954 -280
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+rect 1486 -318 1574 6
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+rect 1380 -398 1574 -318
+rect 41 -519 1697 -504
+rect 35 -525 1703 -519
+rect 35 -597 47 -525
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+rect 35 -603 1703 -597
+rect 41 -605 1697 -603
+<< via1 >>
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+rect 658 938 712 1292
+rect 850 938 904 1292
+rect 1042 938 1096 1292
+rect 1234 938 1288 1292
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+rect 458 -242 776 -190
+rect 954 -340 1272 -280
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+rect 47 -597 1691 -525
+<< metal2 >>
+rect -52 1558 1820 1584
+rect -54 1522 1824 1558
+rect -54 1478 464 1522
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+rect 1288 1478 1824 1522
+rect 1288 1464 1296 1478
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+rect 458 -378 776 -368
+rect 458 -440 776 -430
+rect 460 -515 776 -440
+rect 47 -525 1691 -515
+rect -63 -597 47 -583
+rect 1691 -597 1811 -583
+rect -63 -721 1811 -597
+<< via2 >>
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+rect 746 442 812 782
+rect 938 442 1004 782
+rect 1130 442 1196 782
+rect 334 140 766 208
+rect 954 -340 1272 -280
+<< metal3 >>
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+rect 736 784 822 787
+rect 928 784 1014 787
+rect 1120 784 1206 787
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+rect 944 -280 1282 -275
+rect 944 -340 954 -280
+rect 1272 -340 1282 -280
+rect 944 -345 1282 -340
+rect 954 -346 1210 -345
+use sky130_fd_pr__nfet_01v8_XG2GE7 sky130_fd_pr__nfet_01v8_XG2GE7_0
+timestamp 1628080314
+transform 0 1 838 -1 0 -309
+box -263 -720 263 720
+use sky130_fd_pr__pfet_01v8_396TWK sky130_fd_pr__pfet_01v8_396TWK_0
+timestamp 1628080314
+transform 1 0 875 0 1 859
+box -551 -649 551 649
+use sky130_fd_pr__res_high_po_0p35_C72MAQ sky130_fd_pr__res_high_po_0p35_C72MAQ_0
+timestamp 1628058135
+transform 0 1 864 -1 0 53
+box -37 -532 37 532
+use sky130_fd_pr__res_high_po_0p69_7JPRER sky130_fd_pr__res_high_po_0p69_7JPRER_0
+timestamp 1628069922
+transform 1 0 1719 0 1 543
+box -71 -527 71 527
+<< labels >>
+rlabel metal2 -63 -721 1811 -597 1 GND
+port 2 n
+rlabel metal3 38 142 182 222 1 Out
+port 6 n
+rlabel metal1 1810 692 1948 1002 1 In
+port 5 n
+rlabel metal2 -52 1480 1818 1584 1 VDD
+port 1 n
+<< end >>
diff --git a/mag/biasnmos.mag b/mag/biasnmos.mag
new file mode 100644
index 0000000..1035397
--- /dev/null
+++ b/mag/biasnmos.mag
@@ -0,0 +1,600 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627800883
+<< poly >>
+rect 3963 675 4060 701
+rect 3967 671 4060 675
+rect 4030 623 4060 671
+<< locali >>
+rect 50 -128 4114 -118
+rect 50 -206 62 -128
+rect 4102 -206 4114 -128
+rect 50 -216 4114 -206
+<< viali >>
+rect 62 -206 4102 -128
+<< metal1 >>
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+<< via1 >>
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+rect 3964 354 4032 364
+use sky130_fd_pr__nfet_01v8_4PXCG5 sky130_fd_pr__nfet_01v8_4PXCG5_0
+timestamp 1627727346
+transform 1 0 2077 0 -1 323
+box -2183 -510 2183 510
+<< labels >>
+rlabel metal2 28 -318 4124 -206 1 GND
+port 2 n
+rlabel metal1 80 656 3976 704 1 gate
+port 4 n
+rlabel metal3 124 748 4024 810 1 vl
+port 5 n
+<< end >>
diff --git a/mag/biaspmos.mag b/mag/biaspmos.mag
new file mode 100644
index 0000000..c87e9a6
--- /dev/null
+++ b/mag/biaspmos.mag
@@ -0,0 +1,591 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627991837
+<< nwell >>
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+rect -52 -1438 4314 -640
+rect -52 -1442 348 -1438
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+rect 2286 -1706 2310 -1502
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+rect 4230 -752 4276 -716
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+rect 78 -1640 4180 -1450
+use sky130_fd_pr__pfet_01v8_CC7KEW sky130_fd_pr__pfet_01v8_CC7KEW_0
+timestamp 1627668659
+transform 1 0 2131 0 1 -1038
+box -2081 -400 2081 400
+<< labels >>
+rlabel metal3 82 -1636 4176 -1558 1 vh
+port 4 n
+rlabel metal1 134 -1430 4034 -1378 1 gate
+port 6 n
+rlabel metal2 90 -612 4174 -524 1 VDD
+port 7 n
+rlabel psubdiffcont 276 -1706 2286 -1502 1 GND
+<< end >>
diff --git a/mag/neuron_s.mag b/mag/neuron_s.mag
new file mode 100644
index 0000000..c9403c7
--- /dev/null
+++ b/mag/neuron_s.mag
@@ -0,0 +1,94 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628080429
+<< metal1 >>
+rect -6183 4348 -4726 4674
+rect -6176 1604 -4518 1896
+rect 442 1736 1162 1752
+rect 436 1270 446 1736
+rect 1142 1270 1162 1736
+rect 442 1210 1162 1270
+rect 11910 1040 12486 1410
+rect -6200 -1284 -4518 -992
+<< via1 >>
+rect 446 1270 1142 1736
+<< metal2 >>
+rect -2211 5291 -2105 5305
+rect -2985 5275 -2387 5277
+rect -2309 5275 -2105 5291
+rect -2985 5171 -2105 5275
+rect -2471 3445 -2105 5171
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+rect -3050 -2634 2430 -2578
+rect -5494 -3042 2432 -2634
+<< via2 >>
+rect 446 1270 1142 1736
+<< metal3 >>
+rect -2651 3897 -2380 5933
+rect -3113 3807 -2380 3897
+rect -2033 1125 -1673 5938
+rect -3049 1035 -1673 1125
+rect -1209 -1755 -711 5957
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+rect 11886 190 13048 498
+rect -3039 -1845 -711 -1755
+use aninv_ aninv__2
+timestamp 1628080314
+transform -1 0 -2858 0 1 -1981
+box -63 -721 1952 1584
+use aninv_ aninv__1
+timestamp 1628080314
+transform -1 0 -2858 0 1 899
+box -63 -721 1952 1584
+use aninv_ aninv__0
+timestamp 1628080314
+transform -1 0 -2858 0 1 3671
+box -63 -721 1952 1584
+use analogneuron_invopamp_re_15kfeedbck analogneuron_invopamp_re_15kfeedbck_0
+timestamp 1628079258
+transform 1 0 1354 0 1 234
+box -1354 -234 10900 2910
+<< labels >>
+rlabel metal3 12386 200 13016 482 1 Out
+port 1 n
+rlabel metal1 -6158 4352 -5796 4664 1 In1
+port 3 n
+rlabel metal1 12116 1056 12472 1404 1 Vref
+port 4 n
+rlabel metal1 -6164 1612 -5830 1880 1 In2
+port 5 n
+rlabel metal1 -6176 -1274 -5842 -1006 1 In3
+port 6 n
+rlabel metal3 -2636 5770 -2388 5924 1 R1
+port 7 n
+rlabel metal3 -2018 5770 -1686 5926 1 R2
+port 8 n
+rlabel metal3 -1192 5782 -728 5942 1 R3
+port 9 n
+rlabel metal3 470 5766 1042 5966 1 amp_in
+port 10 n
+rlabel metal2 1706 3070 11834 3360 1 VDD
+port 11 n
+rlabel metal2 1726 -248 11738 2 1 GND
+port 12 n
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_4PXCG5.mag b/mag/sky130_fd_pr__nfet_01v8_4PXCG5.mag
new file mode 100644
index 0000000..d5d94b3
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_4PXCG5.mag
@@ -0,0 +1,1309 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627727346
+<< error_p >>
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+<< pwell >>
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+<< nmos >>
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+rect 1651 -378 1709 -372
+rect 1843 -338 1901 -332
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+rect 1889 -372 1901 -338
+rect 1843 -378 1901 -372
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -2130 -457 2130 457
+string parameters w 3 l 0.150 m 1 nf 42 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_52TL5F.mag b/mag/sky130_fd_pr__nfet_01v8_52TL5F.mag
new file mode 100644
index 0000000..6b2671b
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_52TL5F.mag
@@ -0,0 +1,115 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628068563
+<< error_p >>
+rect 19 552 77 558
+rect 19 518 31 552
+rect 19 512 77 518
+rect -77 -518 -19 -512
+rect -77 -552 -65 -518
+rect -77 -558 -19 -552
+<< pwell >>
+rect -263 -690 263 690
+<< nmos >>
+rect -63 -480 -33 480
+rect 33 -480 63 480
+<< ndiff >>
+rect -125 468 -63 480
+rect -125 -468 -113 468
+rect -79 -468 -63 468
+rect -125 -480 -63 -468
+rect -33 468 33 480
+rect -33 -468 -17 468
+rect 17 -468 33 468
+rect -33 -480 33 -468
+rect 63 468 125 480
+rect 63 -468 79 468
+rect 113 -468 125 468
+rect 63 -480 125 -468
+<< ndiffc >>
+rect -113 -468 -79 468
+rect -17 -468 17 468
+rect 79 -468 113 468
+<< psubdiff >>
+rect -227 620 -131 654
+rect 131 620 227 654
+rect -227 558 -193 620
+rect 193 558 227 620
+rect -227 -620 -193 -558
+rect 193 -620 227 -558
+rect -227 -654 -131 -620
+rect 131 -654 227 -620
+<< psubdiffcont >>
+rect -131 620 131 654
+rect -227 -558 -193 558
+rect 193 -558 227 558
+rect -131 -654 131 -620
+<< poly >>
+rect 15 552 81 568
+rect 15 518 31 552
+rect 65 518 81 552
+rect -63 480 -33 506
+rect 15 502 81 518
+rect 33 480 63 502
+rect -63 -502 -33 -480
+rect -81 -518 -15 -502
+rect 33 -506 63 -480
+rect -81 -552 -65 -518
+rect -31 -552 -15 -518
+rect -81 -568 -15 -552
+<< polycont >>
+rect 31 518 65 552
+rect -65 -552 -31 -518
+<< locali >>
+rect -227 620 -131 654
+rect 131 620 227 654
+rect -227 558 -193 620
+rect 193 558 227 620
+rect 15 518 31 552
+rect 65 518 81 552
+rect -113 468 -79 484
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+rect -17 468 17 484
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+rect -31 -552 -15 -518
+rect -227 -620 -193 -558
+rect 193 -620 227 -558
+rect -227 -654 -131 -620
+rect 131 -654 227 -620
+<< viali >>
+rect 31 518 65 552
+rect -113 -468 -79 468
+rect -17 -468 17 468
+rect 79 -468 113 468
+rect -65 -552 -31 -518
+<< metal1 >>
+rect 19 552 77 558
+rect 19 518 31 552
+rect 65 518 77 552
+rect 19 512 77 518
+rect -119 468 -73 480
+rect -119 -468 -113 468
+rect -79 -468 -73 468
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+rect 73 468 119 480
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+rect 73 -480 119 -468
+rect -77 -518 -19 -512
+rect -77 -552 -65 -518
+rect -31 -552 -19 -518
+rect -77 -558 -19 -552
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -210 -637 210 637
+string parameters w 4.8 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_5QB7GF.mag b/mag/sky130_fd_pr__nfet_01v8_5QB7GF.mag
new file mode 100644
index 0000000..6c804d5
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_5QB7GF.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628056522
+<< error_p >>
+rect -29 881 29 887
+rect -29 847 -17 881
+rect -29 841 29 847
+<< pwell >>
+rect -211 -1019 211 1019
+<< nmos >>
+rect -15 -871 15 809
+<< ndiff >>
+rect -73 797 -15 809
+rect -73 -859 -61 797
+rect -27 -859 -15 797
+rect -73 -871 -15 -859
+rect 15 797 73 809
+rect 15 -859 27 797
+rect 61 -859 73 797
+rect 15 -871 73 -859
+<< ndiffc >>
+rect -61 -859 -27 797
+rect 27 -859 61 797
+<< psubdiff >>
+rect -175 949 -79 983
+rect 79 949 175 983
+rect -175 887 -141 949
+rect 141 887 175 949
+rect -175 -949 -141 -887
+rect 141 -949 175 -887
+rect -175 -983 -79 -949
+rect 79 -983 175 -949
+<< psubdiffcont >>
+rect -79 949 79 983
+rect -175 -887 -141 887
+rect 141 -887 175 887
+rect -79 -983 79 -949
+<< poly >>
+rect -33 881 33 897
+rect -33 847 -17 881
+rect 17 847 33 881
+rect -33 831 33 847
+rect -15 809 15 831
+rect -15 -897 15 -871
+<< polycont >>
+rect -17 847 17 881
+<< locali >>
+rect -175 949 -79 983
+rect 79 949 175 983
+rect -175 887 -141 949
+rect 141 887 175 949
+rect -33 847 -17 881
+rect 17 847 33 881
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+rect 27 -875 61 -859
+rect -175 -949 -141 -887
+rect 141 -949 175 -887
+rect -175 -983 -79 -949
+rect 79 -983 175 -949
+<< viali >>
+rect -17 847 17 881
+rect -61 -859 -27 797
+rect 27 -859 61 797
+<< metal1 >>
+rect -29 881 29 887
+rect -29 847 -17 881
+rect 17 847 29 881
+rect -29 841 29 847
+rect -67 797 -21 809
+rect -67 -859 -61 797
+rect -27 -859 -21 797
+rect -67 -871 -21 -859
+rect 21 797 67 809
+rect 21 -859 27 797
+rect 61 -859 67 797
+rect 21 -871 67 -859
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -966 158 966
+string parameters w 8.4 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 0 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_782H3L.mag b/mag/sky130_fd_pr__nfet_01v8_782H3L.mag
new file mode 100644
index 0000000..01c46ba
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_782H3L.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628059907
+<< error_p >>
+rect -29 1321 29 1327
+rect -29 1287 -17 1321
+rect -29 1281 29 1287
+<< pwell >>
+rect -211 -1459 211 1459
+<< nmos >>
+rect -15 -1311 15 1249
+<< ndiff >>
+rect -73 1237 -15 1249
+rect -73 -1299 -61 1237
+rect -27 -1299 -15 1237
+rect -73 -1311 -15 -1299
+rect 15 1237 73 1249
+rect 15 -1299 27 1237
+rect 61 -1299 73 1237
+rect 15 -1311 73 -1299
+<< ndiffc >>
+rect -61 -1299 -27 1237
+rect 27 -1299 61 1237
+<< psubdiff >>
+rect -175 1389 -79 1423
+rect 79 1389 175 1423
+rect -175 1327 -141 1389
+rect 141 1327 175 1389
+rect -175 -1389 -141 -1327
+rect 141 -1389 175 -1327
+rect -175 -1423 -79 -1389
+rect 79 -1423 175 -1389
+<< psubdiffcont >>
+rect -79 1389 79 1423
+rect -175 -1327 -141 1327
+rect 141 -1327 175 1327
+rect -79 -1423 79 -1389
+<< poly >>
+rect -33 1321 33 1337
+rect -33 1287 -17 1321
+rect 17 1287 33 1321
+rect -33 1271 33 1287
+rect -15 1249 15 1271
+rect -15 -1337 15 -1311
+<< polycont >>
+rect -17 1287 17 1321
+<< locali >>
+rect -175 1389 -79 1423
+rect 79 1389 175 1423
+rect -175 1327 -141 1389
+rect 141 1327 175 1389
+rect -33 1287 -17 1321
+rect 17 1287 33 1321
+rect -61 1237 -27 1253
+rect -61 -1315 -27 -1299
+rect 27 1237 61 1253
+rect 27 -1315 61 -1299
+rect -175 -1389 -141 -1327
+rect 141 -1389 175 -1327
+rect -175 -1423 -79 -1389
+rect 79 -1423 175 -1389
+<< viali >>
+rect -17 1287 17 1321
+rect -61 -1299 -27 1237
+rect 27 -1299 61 1237
+<< metal1 >>
+rect -29 1321 29 1327
+rect -29 1287 -17 1321
+rect 17 1287 29 1321
+rect -29 1281 29 1287
+rect -67 1237 -21 1249
+rect -67 -1299 -61 1237
+rect -27 -1299 -21 1237
+rect -67 -1311 -21 -1299
+rect 21 1237 67 1249
+rect 21 -1299 27 1237
+rect 61 -1299 67 1237
+rect 21 -1311 67 -1299
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -1406 158 1406
+string parameters w 12.8 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 0 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_7ZKCBF.mag b/mag/sky130_fd_pr__nfet_01v8_7ZKCBF.mag
new file mode 100644
index 0000000..d47a0d8
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_7ZKCBF.mag
@@ -0,0 +1,60 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627719842
+<< error_p >>
+rect -29 341 29 347
+rect -29 307 -17 341
+rect -29 301 29 307
+<< nmos >>
+rect -15 -331 15 269
+<< ndiff >>
+rect -73 257 -15 269
+rect -73 -319 -61 257
+rect -27 -319 -15 257
+rect -73 -331 -15 -319
+rect 15 257 73 269
+rect 15 -319 27 257
+rect 61 -319 73 257
+rect 15 -331 73 -319
+<< ndiffc >>
+rect -61 -319 -27 257
+rect 27 -319 61 257
+<< poly >>
+rect -33 341 33 357
+rect -33 307 -17 341
+rect 17 307 33 341
+rect -33 291 33 307
+rect -15 269 15 291
+rect -15 -357 15 -331
+<< polycont >>
+rect -17 307 17 341
+<< locali >>
+rect -33 307 -17 341
+rect 17 307 33 341
+rect -61 257 -27 273
+rect -61 -335 -27 -319
+rect 27 257 61 273
+rect 27 -335 61 -319
+<< viali >>
+rect -17 307 17 341
+rect -61 -319 -27 257
+rect 27 -319 61 257
+<< metal1 >>
+rect -29 341 29 347
+rect -29 307 -17 341
+rect 17 307 29 341
+rect -29 301 29 307
+rect -67 257 -21 269
+rect -67 -319 -61 257
+rect -27 -319 -21 257
+rect -67 -331 -21 -319
+rect 21 257 67 269
+rect 21 -319 27 257
+rect 61 -319 67 257
+rect 21 -331 67 -319
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string parameters w 3 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_9UJ7GX.mag b/mag/sky130_fd_pr__nfet_01v8_9UJ7GX.mag
new file mode 100644
index 0000000..00c1043
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_9UJ7GX.mag
@@ -0,0 +1,127 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628066849
+<< error_p >>
+rect -29 959 29 965
+rect -29 925 -17 959
+rect -29 919 29 925
+rect -29 -37 29 -31
+rect -29 -71 -17 -37
+rect -29 -77 29 -71
+<< pwell >>
+rect -211 -1097 211 1097
+<< nmos >>
+rect -15 47 15 887
+rect -15 -949 15 -109
+<< ndiff >>
+rect -73 875 -15 887
+rect -73 59 -61 875
+rect -27 59 -15 875
+rect -73 47 -15 59
+rect 15 875 73 887
+rect 15 59 27 875
+rect 61 59 73 875
+rect 15 47 73 59
+rect -73 -121 -15 -109
+rect -73 -937 -61 -121
+rect -27 -937 -15 -121
+rect -73 -949 -15 -937
+rect 15 -121 73 -109
+rect 15 -937 27 -121
+rect 61 -937 73 -121
+rect 15 -949 73 -937
+<< ndiffc >>
+rect -61 59 -27 875
+rect 27 59 61 875
+rect -61 -937 -27 -121
+rect 27 -937 61 -121
+<< psubdiff >>
+rect -175 1027 -79 1061
+rect 79 1027 175 1061
+rect -175 965 -141 1027
+rect 141 965 175 1027
+rect -175 -1027 -141 -965
+rect 141 -1027 175 -965
+rect -175 -1061 -79 -1027
+rect 79 -1061 175 -1027
+<< psubdiffcont >>
+rect -79 1027 79 1061
+rect -175 -965 -141 965
+rect 141 -965 175 965
+rect -79 -1061 79 -1027
+<< poly >>
+rect -33 959 33 975
+rect -33 925 -17 959
+rect 17 925 33 959
+rect -33 909 33 925
+rect -15 887 15 909
+rect -15 21 15 47
+rect -33 -37 33 -21
+rect -33 -71 -17 -37
+rect 17 -71 33 -37
+rect -33 -87 33 -71
+rect -15 -109 15 -87
+rect -15 -975 15 -949
+<< polycont >>
+rect -17 925 17 959
+rect -17 -71 17 -37
+<< locali >>
+rect -175 1027 -79 1061
+rect 79 1027 175 1061
+rect -175 965 -141 1027
+rect 141 965 175 1027
+rect -33 925 -17 959
+rect 17 925 33 959
+rect -61 875 -27 891
+rect -61 43 -27 59
+rect 27 875 61 891
+rect 27 43 61 59
+rect -33 -71 -17 -37
+rect 17 -71 33 -37
+rect -61 -121 -27 -105
+rect -61 -953 -27 -937
+rect 27 -121 61 -105
+rect 27 -953 61 -937
+rect -175 -1027 -141 -965
+rect 141 -1027 175 -965
+rect -175 -1061 -79 -1027
+rect 79 -1061 175 -1027
+<< viali >>
+rect -17 925 17 959
+rect -61 59 -27 875
+rect 27 59 61 875
+rect -17 -71 17 -37
+rect -61 -937 -27 -121
+rect 27 -937 61 -121
+<< metal1 >>
+rect -29 959 29 965
+rect -29 925 -17 959
+rect 17 925 29 959
+rect -29 919 29 925
+rect -67 875 -21 887
+rect -67 59 -61 875
+rect -27 59 -21 875
+rect -67 47 -21 59
+rect 21 875 67 887
+rect 21 59 27 875
+rect 61 59 67 875
+rect 21 47 67 59
+rect -29 -37 29 -31
+rect -29 -71 -17 -37
+rect 17 -71 29 -37
+rect -29 -77 29 -71
+rect -67 -121 -21 -109
+rect -67 -937 -61 -121
+rect -27 -937 -21 -121
+rect -67 -949 -21 -937
+rect 21 -121 67 -109
+rect 21 -937 27 -121
+rect 61 -937 67 -121
+rect 21 -949 67 -937
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -1044 158 1044
+string parameters w 4.2 l 0.150 m 2 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 0 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_A2TL5X.mag b/mag/sky130_fd_pr__nfet_01v8_A2TL5X.mag
new file mode 100644
index 0000000..9a3c2bd
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_A2TL5X.mag
@@ -0,0 +1,115 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628066849
+<< error_p >>
+rect 19 492 77 498
+rect 19 458 31 492
+rect 19 452 77 458
+rect -77 -458 -19 -452
+rect -77 -492 -65 -458
+rect -77 -498 -19 -492
+<< pwell >>
+rect -263 -630 263 630
+<< nmos >>
+rect -63 -420 -33 420
+rect 33 -420 63 420
+<< ndiff >>
+rect -125 408 -63 420
+rect -125 -408 -113 408
+rect -79 -408 -63 408
+rect -125 -420 -63 -408
+rect -33 408 33 420
+rect -33 -408 -17 408
+rect 17 -408 33 408
+rect -33 -420 33 -408
+rect 63 408 125 420
+rect 63 -408 79 408
+rect 113 -408 125 408
+rect 63 -420 125 -408
+<< ndiffc >>
+rect -113 -408 -79 408
+rect -17 -408 17 408
+rect 79 -408 113 408
+<< psubdiff >>
+rect -227 560 -131 594
+rect 131 560 227 594
+rect -227 498 -193 560
+rect 193 498 227 560
+rect -227 -560 -193 -498
+rect 193 -560 227 -498
+rect -227 -594 -131 -560
+rect 131 -594 227 -560
+<< psubdiffcont >>
+rect -131 560 131 594
+rect -227 -498 -193 498
+rect 193 -498 227 498
+rect -131 -594 131 -560
+<< poly >>
+rect 15 492 81 508
+rect 15 458 31 492
+rect 65 458 81 492
+rect -63 420 -33 446
+rect 15 442 81 458
+rect 33 420 63 442
+rect -63 -442 -33 -420
+rect -81 -458 -15 -442
+rect 33 -446 63 -420
+rect -81 -492 -65 -458
+rect -31 -492 -15 -458
+rect -81 -508 -15 -492
+<< polycont >>
+rect 31 458 65 492
+rect -65 -492 -31 -458
+<< locali >>
+rect -227 560 -131 594
+rect 131 560 227 594
+rect -227 498 -193 560
+rect 193 498 227 560
+rect 15 458 31 492
+rect 65 458 81 492
+rect -113 408 -79 424
+rect -113 -424 -79 -408
+rect -17 408 17 424
+rect -17 -424 17 -408
+rect 79 408 113 424
+rect 79 -424 113 -408
+rect -81 -492 -65 -458
+rect -31 -492 -15 -458
+rect -227 -560 -193 -498
+rect 193 -560 227 -498
+rect -227 -594 -131 -560
+rect 131 -594 227 -560
+<< viali >>
+rect 31 458 65 492
+rect -113 -408 -79 408
+rect -17 -408 17 408
+rect 79 -408 113 408
+rect -65 -492 -31 -458
+<< metal1 >>
+rect 19 492 77 498
+rect 19 458 31 492
+rect 65 458 77 492
+rect 19 452 77 458
+rect -119 408 -73 420
+rect -119 -408 -113 408
+rect -79 -408 -73 408
+rect -119 -420 -73 -408
+rect -23 408 23 420
+rect -23 -408 -17 408
+rect 17 -408 23 408
+rect -23 -420 23 -408
+rect 73 408 119 420
+rect 73 -408 79 408
+rect 113 -408 119 408
+rect 73 -420 119 -408
+rect -77 -458 -19 -452
+rect -77 -492 -65 -458
+rect -31 -492 -19 -458
+rect -77 -498 -19 -492
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -210 -577 210 577
+string parameters w 4.2 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_AAC7GX.mag b/mag/sky130_fd_pr__nfet_01v8_AAC7GX.mag
new file mode 100644
index 0000000..64e8fb5
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_AAC7GX.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628058135
+<< error_p >>
+rect -29 1001 29 1007
+rect -29 967 -17 1001
+rect -29 961 29 967
+<< pwell >>
+rect -211 -1139 211 1139
+<< nmos >>
+rect -15 -991 15 929
+<< ndiff >>
+rect -73 917 -15 929
+rect -73 -979 -61 917
+rect -27 -979 -15 917
+rect -73 -991 -15 -979
+rect 15 917 73 929
+rect 15 -979 27 917
+rect 61 -979 73 917
+rect 15 -991 73 -979
+<< ndiffc >>
+rect -61 -979 -27 917
+rect 27 -979 61 917
+<< psubdiff >>
+rect -175 1069 -79 1103
+rect 79 1069 175 1103
+rect -175 1007 -141 1069
+rect 141 1007 175 1069
+rect -175 -1069 -141 -1007
+rect 141 -1069 175 -1007
+rect -175 -1103 -79 -1069
+rect 79 -1103 175 -1069
+<< psubdiffcont >>
+rect -79 1069 79 1103
+rect -175 -1007 -141 1007
+rect 141 -1007 175 1007
+rect -79 -1103 79 -1069
+<< poly >>
+rect -33 1001 33 1017
+rect -33 967 -17 1001
+rect 17 967 33 1001
+rect -33 951 33 967
+rect -15 929 15 951
+rect -15 -1017 15 -991
+<< polycont >>
+rect -17 967 17 1001
+<< locali >>
+rect -175 1069 -79 1103
+rect 79 1069 175 1103
+rect -175 1007 -141 1069
+rect 141 1007 175 1069
+rect -33 967 -17 1001
+rect 17 967 33 1001
+rect -61 917 -27 933
+rect -61 -995 -27 -979
+rect 27 917 61 933
+rect 27 -995 61 -979
+rect -175 -1069 -141 -1007
+rect 141 -1069 175 -1007
+rect -175 -1103 -79 -1069
+rect 79 -1103 175 -1069
+<< viali >>
+rect -17 967 17 1001
+rect -61 -979 -27 917
+rect 27 -979 61 917
+<< metal1 >>
+rect -29 1001 29 1007
+rect -29 967 -17 1001
+rect 17 967 29 1001
+rect -29 961 29 967
+rect -67 917 -21 929
+rect -67 -979 -61 917
+rect -27 -979 -21 917
+rect -67 -991 -21 -979
+rect 21 917 67 929
+rect 21 -979 27 917
+rect 61 -979 67 917
+rect 21 -991 67 -979
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -1086 158 1086
+string parameters w 9.6 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 0 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_AGP7GX.mag b/mag/sky130_fd_pr__nfet_01v8_AGP7GX.mag
new file mode 100644
index 0000000..0107806
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_AGP7GX.mag
@@ -0,0 +1,126 @@
+magic
+tech sky130A
+timestamp 1628066849
+<< error_p >>
+rect 38 246 67 249
+rect 38 229 44 246
+rect 38 226 67 229
+rect -67 -229 -38 -226
+rect -67 -246 -61 -229
+rect -67 -249 -38 -246
+<< pwell >>
+rect -160 -315 160 315
+<< nmos >>
+rect -60 -210 -45 210
+rect 45 -210 60 210
+<< ndiff >>
+rect -91 204 -60 210
+rect -91 -204 -85 204
+rect -68 -204 -60 204
+rect -91 -210 -60 -204
+rect -45 204 -14 210
+rect -45 -204 -37 204
+rect -20 -204 -14 204
+rect -45 -210 -14 -204
+rect 14 204 45 210
+rect 14 -204 20 204
+rect 37 -204 45 204
+rect 14 -210 45 -204
+rect 60 204 91 210
+rect 60 -204 68 204
+rect 85 -204 91 204
+rect 60 -210 91 -204
+<< ndiffc >>
+rect -85 -204 -68 204
+rect -37 -204 -20 204
+rect 20 -204 37 204
+rect 68 -204 85 204
+<< psubdiff >>
+rect -142 280 -94 297
+rect 94 280 142 297
+rect -142 249 -125 280
+rect 125 249 142 280
+rect -142 -280 -125 -249
+rect 125 -280 142 -249
+rect -142 -297 -94 -280
+rect 94 -297 142 -280
+<< psubdiffcont >>
+rect -94 280 94 297
+rect -142 -249 -125 249
+rect 125 -249 142 249
+rect -94 -297 94 -280
+<< poly >>
+rect 36 246 69 254
+rect 36 229 44 246
+rect 61 229 69 246
+rect -60 210 -45 223
+rect 36 221 69 229
+rect 45 210 60 221
+rect -60 -221 -45 -210
+rect -69 -229 -36 -221
+rect 45 -223 60 -210
+rect -69 -246 -61 -229
+rect -44 -246 -36 -229
+rect -69 -254 -36 -246
+<< polycont >>
+rect 44 229 61 246
+rect -61 -246 -44 -229
+<< locali >>
+rect -142 280 -94 297
+rect 94 280 142 297
+rect -142 249 -125 280
+rect 125 249 142 280
+rect 36 229 44 246
+rect 61 229 69 246
+rect -85 204 -68 212
+rect -85 -212 -68 -204
+rect -37 204 -20 212
+rect -37 -212 -20 -204
+rect 20 204 37 212
+rect 20 -212 37 -204
+rect 68 204 85 212
+rect 68 -212 85 -204
+rect -69 -246 -61 -229
+rect -44 -246 -36 -229
+rect -142 -280 -125 -249
+rect 125 -280 142 -249
+rect -142 -297 -94 -280
+rect 94 -297 142 -280
+<< viali >>
+rect 44 229 61 246
+rect -85 -204 -68 204
+rect -37 -204 -20 204
+rect 20 -204 37 204
+rect 68 -204 85 204
+rect -61 -246 -44 -229
+<< metal1 >>
+rect 38 246 67 249
+rect 38 229 44 246
+rect 61 229 67 246
+rect 38 226 67 229
+rect -88 204 -65 210
+rect -88 -204 -85 204
+rect -68 -204 -65 204
+rect -88 -210 -65 -204
+rect -40 204 -17 210
+rect -40 -204 -37 204
+rect -20 -204 -17 204
+rect -40 -210 -17 -204
+rect 17 204 40 210
+rect 17 -204 20 204
+rect 37 -204 40 204
+rect 17 -210 40 -204
+rect 65 204 88 210
+rect 65 -204 68 204
+rect 85 -204 88 204
+rect 65 -210 88 -204
+rect -67 -229 -38 -226
+rect -67 -246 -61 -229
+rect -44 -246 -38 -229
+rect -67 -249 -38 -246
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -133 -288 133 288
+string parameters w 4.2 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 0 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_AZFMGK.mag b/mag/sky130_fd_pr__nfet_01v8_AZFMGK.mag
new file mode 100644
index 0000000..dda0eff
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_AZFMGK.mag
@@ -0,0 +1,60 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627719842
+<< error_p >>
+rect -29 341 29 347
+rect -29 307 -17 341
+rect -29 301 29 307
+<< nmos >>
+rect -15 -331 15 269
+<< ndiff >>
+rect -73 257 -15 269
+rect -73 -319 -61 257
+rect -27 -319 -15 257
+rect -73 -331 -15 -319
+rect 15 257 73 269
+rect 15 -319 27 257
+rect 61 -319 73 257
+rect 15 -331 73 -319
+<< ndiffc >>
+rect -61 -319 -27 257
+rect 27 -319 61 257
+<< poly >>
+rect -33 341 33 357
+rect -33 307 -17 341
+rect 17 307 33 341
+rect -33 291 33 307
+rect -15 269 15 291
+rect -15 -357 15 -331
+<< polycont >>
+rect -17 307 17 341
+<< locali >>
+rect -33 307 -17 341
+rect 17 307 33 341
+rect -61 257 -27 273
+rect -61 -335 -27 -319
+rect 27 257 61 273
+rect 27 -335 61 -319
+<< viali >>
+rect -17 307 17 341
+rect -61 -319 -27 257
+rect 27 -319 61 257
+<< metal1 >>
+rect -29 341 29 347
+rect -29 307 -17 341
+rect 17 307 29 341
+rect -29 301 29 307
+rect -67 257 -21 269
+rect -67 -319 -61 257
+rect -27 -319 -21 257
+rect -67 -331 -21 -319
+rect 21 257 67 269
+rect 21 -319 27 257
+rect 61 -319 67 257
+rect 21 -331 67 -319
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string parameters w 3 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 0 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_BBTBMZ.mag b/mag/sky130_fd_pr__nfet_01v8_BBTBMZ.mag
new file mode 100644
index 0000000..a5c2936
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_BBTBMZ.mag
@@ -0,0 +1,1147 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627668659
+<< error_p >>
+rect -845 373 -787 379
+rect -653 373 -595 379
+rect -461 373 -403 379
+rect -269 373 -211 379
+rect -77 373 -19 379
+rect 115 373 173 379
+rect 307 373 365 379
+rect 499 373 557 379
+rect 691 373 749 379
+rect -845 339 -833 373
+rect -653 339 -641 373
+rect -461 339 -449 373
+rect -269 339 -257 373
+rect -77 339 -65 373
+rect 115 339 127 373
+rect 307 339 319 373
+rect 499 339 511 373
+rect 691 339 703 373
+rect -845 333 -787 339
+rect -653 333 -595 339
+rect -461 333 -403 339
+rect -269 333 -211 339
+rect -77 333 -19 339
+rect 115 333 173 339
+rect 307 333 365 339
+rect 499 333 557 339
+rect 691 333 749 339
+rect -749 71 -691 77
+rect -557 71 -499 77
+rect -365 71 -307 77
+rect -173 71 -115 77
+rect 19 71 77 77
+rect 211 71 269 77
+rect 403 71 461 77
+rect 595 71 653 77
+rect 787 71 845 77
+rect -749 37 -737 71
+rect -557 37 -545 71
+rect -365 37 -353 71
+rect -173 37 -161 71
+rect 19 37 31 71
+rect 211 37 223 71
+rect 403 37 415 71
+rect 595 37 607 71
+rect 787 37 799 71
+rect -749 31 -691 37
+rect -557 31 -499 37
+rect -365 31 -307 37
+rect -173 31 -115 37
+rect 19 31 77 37
+rect 211 31 269 37
+rect 403 31 461 37
+rect 595 31 653 37
+rect 787 31 845 37
+rect -749 -37 -691 -31
+rect -557 -37 -499 -31
+rect -365 -37 -307 -31
+rect -173 -37 -115 -31
+rect 19 -37 77 -31
+rect 211 -37 269 -31
+rect 403 -37 461 -31
+rect 595 -37 653 -31
+rect 787 -37 845 -31
+rect -749 -71 -737 -37
+rect -557 -71 -545 -37
+rect -365 -71 -353 -37
+rect -173 -71 -161 -37
+rect 19 -71 31 -37
+rect 211 -71 223 -37
+rect 403 -71 415 -37
+rect 595 -71 607 -37
+rect 787 -71 799 -37
+rect -749 -77 -691 -71
+rect -557 -77 -499 -71
+rect -365 -77 -307 -71
+rect -173 -77 -115 -71
+rect 19 -77 77 -71
+rect 211 -77 269 -71
+rect 403 -77 461 -71
+rect 595 -77 653 -71
+rect 787 -77 845 -71
+rect -845 -339 -787 -333
+rect -653 -339 -595 -333
+rect -461 -339 -403 -333
+rect -269 -339 -211 -333
+rect -77 -339 -19 -333
+rect 115 -339 173 -333
+rect 307 -339 365 -333
+rect 499 -339 557 -333
+rect 691 -339 749 -333
+rect -845 -373 -833 -339
+rect -653 -373 -641 -339
+rect -461 -373 -449 -339
+rect -269 -373 -257 -339
+rect -77 -373 -65 -339
+rect 115 -373 127 -339
+rect 307 -373 319 -339
+rect 499 -373 511 -339
+rect 691 -373 703 -339
+rect -845 -379 -787 -373
+rect -653 -379 -595 -373
+rect -461 -379 -403 -373
+rect -269 -379 -211 -373
+rect -77 -379 -19 -373
+rect 115 -379 173 -373
+rect 307 -379 365 -373
+rect 499 -379 557 -373
+rect 691 -379 749 -373
+<< pwell >>
+rect -1031 -511 1031 511
+<< nmos >>
+rect -831 109 -801 301
+rect -735 109 -705 301
+rect -639 109 -609 301
+rect -543 109 -513 301
+rect -447 109 -417 301
+rect -351 109 -321 301
+rect -255 109 -225 301
+rect -159 109 -129 301
+rect -63 109 -33 301
+rect 33 109 63 301
+rect 129 109 159 301
+rect 225 109 255 301
+rect 321 109 351 301
+rect 417 109 447 301
+rect 513 109 543 301
+rect 609 109 639 301
+rect 705 109 735 301
+rect 801 109 831 301
+rect -831 -301 -801 -109
+rect -735 -301 -705 -109
+rect -639 -301 -609 -109
+rect -543 -301 -513 -109
+rect -447 -301 -417 -109
+rect -351 -301 -321 -109
+rect -255 -301 -225 -109
+rect -159 -301 -129 -109
+rect -63 -301 -33 -109
+rect 33 -301 63 -109
+rect 129 -301 159 -109
+rect 225 -301 255 -109
+rect 321 -301 351 -109
+rect 417 -301 447 -109
+rect 513 -301 543 -109
+rect 609 -301 639 -109
+rect 705 -301 735 -109
+rect 801 -301 831 -109
+<< ndiff >>
+rect -893 289 -831 301
+rect -893 121 -881 289
+rect -847 121 -831 289
+rect -893 109 -831 121
+rect -801 289 -735 301
+rect -801 121 -785 289
+rect -751 121 -735 289
+rect -801 109 -735 121
+rect -705 289 -639 301
+rect -705 121 -689 289
+rect -655 121 -639 289
+rect -705 109 -639 121
+rect -609 289 -543 301
+rect -609 121 -593 289
+rect -559 121 -543 289
+rect -609 109 -543 121
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+rect 499 -379 557 -373
+rect 691 -339 749 -333
+rect 691 -373 703 -339
+rect 737 -373 749 -339
+rect 691 -379 749 -373
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -978 -458 978 458
+string parameters w 0.96 l 0.150 m 2 nf 18 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_C2ELAV.mag b/mag/sky130_fd_pr__nfet_01v8_C2ELAV.mag
new file mode 100644
index 0000000..8b16eb7
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_C2ELAV.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627964331
+<< error_p >>
+rect -29 -507 29 -501
+rect -29 -541 -17 -507
+rect -29 -547 29 -541
+<< pwell >>
+rect -211 -679 211 679
+<< nmos >>
+rect -15 -469 15 531
+<< ndiff >>
+rect -73 519 -15 531
+rect -73 -457 -61 519
+rect -27 -457 -15 519
+rect -73 -469 -15 -457
+rect 15 519 73 531
+rect 15 -457 27 519
+rect 61 -457 73 519
+rect 15 -469 73 -457
+<< ndiffc >>
+rect -61 -457 -27 519
+rect 27 -457 61 519
+<< psubdiff >>
+rect -175 609 -79 643
+rect 79 609 175 643
+rect -175 547 -141 609
+rect 141 547 175 609
+rect -175 -609 -141 -547
+rect 141 -609 175 -547
+rect -175 -643 -79 -609
+rect 79 -643 175 -609
+<< psubdiffcont >>
+rect -79 609 79 643
+rect -175 -547 -141 547
+rect 141 -547 175 547
+rect -79 -643 79 -609
+<< poly >>
+rect -15 531 15 557
+rect -15 -491 15 -469
+rect -33 -507 33 -491
+rect -33 -541 -17 -507
+rect 17 -541 33 -507
+rect -33 -557 33 -541
+<< polycont >>
+rect -17 -541 17 -507
+<< locali >>
+rect -175 609 -79 643
+rect 79 609 175 643
+rect -175 547 -141 609
+rect 141 547 175 609
+rect -61 519 -27 535
+rect -61 -473 -27 -457
+rect 27 519 61 535
+rect 27 -473 61 -457
+rect -33 -541 -17 -507
+rect 17 -541 33 -507
+rect -175 -609 -141 -547
+rect 141 -609 175 -547
+rect -175 -643 -79 -609
+rect 79 -643 175 -609
+<< viali >>
+rect -61 -457 -27 519
+rect 27 -457 61 519
+rect -17 -541 17 -507
+<< metal1 >>
+rect -67 519 -21 531
+rect -67 -457 -61 519
+rect -27 -457 -21 519
+rect -67 -469 -21 -457
+rect 21 519 67 531
+rect 21 -457 27 519
+rect 61 -457 67 519
+rect 21 -469 67 -457
+rect -29 -507 29 -501
+rect -29 -541 -17 -507
+rect 17 -541 29 -507
+rect -29 -547 29 -541
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -626 158 626
+string parameters w 5 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_CXV4AJ.mag b/mag/sky130_fd_pr__nfet_01v8_CXV4AJ.mag
new file mode 100644
index 0000000..78966b8
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_CXV4AJ.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627111729
+<< nmos >>
+rect -15 -42 15 42
+<< ndiff >>
+rect -73 30 -15 42
+rect -73 -30 -61 30
+rect -27 -30 -15 30
+rect -73 -42 -15 -30
+rect 15 30 73 42
+rect 15 -30 27 30
+rect 61 -30 73 30
+rect 15 -42 73 -30
+<< ndiffc >>
+rect -61 -30 -27 30
+rect 27 -30 61 30
+<< poly >>
+rect -15 42 15 68
+rect -15 -68 15 -42
+<< locali >>
+rect -61 30 -27 46
+rect -61 -46 -27 -30
+rect 27 30 61 46
+rect 27 -46 61 -30
+<< viali >>
+rect -61 -30 -27 30
+rect 27 -30 61 30
+<< metal1 >>
+rect -67 30 -21 42
+rect -67 -30 -61 30
+rect -27 -30 -21 30
+rect -67 -42 -21 -30
+rect 21 30 67 42
+rect 21 -30 27 30
+rect 61 -30 67 30
+rect 21 -42 67 -30
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string parameters w 0.420 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 0 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_GP3VPT.mag b/mag/sky130_fd_pr__nfet_01v8_GP3VPT.mag
new file mode 100644
index 0000000..6a41193
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_GP3VPT.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628056522
+<< nmos >>
+rect -15 -840 15 840
+<< ndiff >>
+rect -73 828 -15 840
+rect -73 -828 -61 828
+rect -27 -828 -15 828
+rect -73 -840 -15 -828
+rect 15 828 73 840
+rect 15 -828 27 828
+rect 61 -828 73 828
+rect 15 -840 73 -828
+<< ndiffc >>
+rect -61 -828 -27 828
+rect 27 -828 61 828
+<< poly >>
+rect -15 840 15 866
+rect -15 -866 15 -840
+<< locali >>
+rect -61 828 -27 844
+rect -61 -844 -27 -828
+rect 27 828 61 844
+rect 27 -844 61 -828
+<< viali >>
+rect -61 -828 -27 828
+rect 27 -828 61 828
+<< metal1 >>
+rect -67 828 -21 840
+rect -67 -828 -61 828
+rect -27 -828 -21 828
+rect -67 -840 -21 -828
+rect 21 828 67 840
+rect 21 -828 27 828
+rect 61 -828 67 828
+rect 21 -840 67 -828
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string parameters w 8.4 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 0 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_HX3HLY.mag b/mag/sky130_fd_pr__nfet_01v8_HX3HLY.mag
new file mode 100644
index 0000000..5b74a78
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_HX3HLY.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627965226
+<< error_p >>
+rect -29 -49 29 -43
+rect -29 -83 -17 -49
+rect -29 -89 29 -83
+<< pwell >>
+rect -211 -221 211 221
+<< nmos >>
+rect -15 -11 15 73
+<< ndiff >>
+rect -73 61 -15 73
+rect -73 1 -61 61
+rect -27 1 -15 61
+rect -73 -11 -15 1
+rect 15 61 73 73
+rect 15 1 27 61
+rect 61 1 73 61
+rect 15 -11 73 1
+<< ndiffc >>
+rect -61 1 -27 61
+rect 27 1 61 61
+<< psubdiff >>
+rect -175 151 -79 185
+rect 79 151 175 185
+rect -175 89 -141 151
+rect 141 89 175 151
+rect -175 -151 -141 -89
+rect 141 -151 175 -89
+rect -175 -185 -79 -151
+rect 79 -185 175 -151
+<< psubdiffcont >>
+rect -79 151 79 185
+rect -175 -89 -141 89
+rect 141 -89 175 89
+rect -79 -185 79 -151
+<< poly >>
+rect -15 73 15 99
+rect -15 -33 15 -11
+rect -33 -49 33 -33
+rect -33 -83 -17 -49
+rect 17 -83 33 -49
+rect -33 -99 33 -83
+<< polycont >>
+rect -17 -83 17 -49
+<< locali >>
+rect -175 151 -79 185
+rect 79 151 175 185
+rect -175 89 -141 151
+rect 141 89 175 151
+rect -61 61 -27 77
+rect -61 -15 -27 1
+rect 27 61 61 77
+rect 27 -15 61 1
+rect -33 -83 -17 -49
+rect 17 -83 33 -49
+rect -175 -151 -141 -89
+rect 141 -151 175 -89
+rect -175 -185 -79 -151
+rect 79 -185 175 -151
+<< viali >>
+rect -61 1 -27 61
+rect 27 1 61 61
+rect -17 -83 17 -49
+<< metal1 >>
+rect -67 61 -21 73
+rect -67 1 -61 61
+rect -27 1 -21 61
+rect -67 -11 -21 1
+rect 21 61 67 73
+rect 21 1 27 61
+rect 61 1 67 61
+rect 21 -11 67 1
+rect -29 -49 29 -43
+rect -29 -83 -17 -49
+rect 17 -83 29 -49
+rect -29 -89 29 -83
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -168 158 168
+string parameters w 0.42 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_LHCY62.mag b/mag/sky130_fd_pr__nfet_01v8_LHCY62.mag
new file mode 100644
index 0000000..2475213
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_LHCY62.mag
@@ -0,0 +1,75 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627059151
+<< error_p >>
+rect -29 114 29 120
+rect -29 80 -17 114
+rect -29 74 29 80
+rect -29 -80 29 -74
+rect -29 -114 -17 -80
+rect -29 -120 29 -114
+<< nmos >>
+rect -15 -42 15 42
+<< ndiff >>
+rect -73 30 -15 42
+rect -73 -30 -61 30
+rect -27 -30 -15 30
+rect -73 -42 -15 -30
+rect 15 30 73 42
+rect 15 -30 27 30
+rect 61 -30 73 30
+rect 15 -42 73 -30
+<< ndiffc >>
+rect -61 -30 -27 30
+rect 27 -30 61 30
+<< poly >>
+rect -33 114 33 130
+rect -33 80 -17 114
+rect 17 80 33 114
+rect -33 64 33 80
+rect -15 42 15 64
+rect -15 -64 15 -42
+rect -33 -80 33 -64
+rect -33 -114 -17 -80
+rect 17 -114 33 -80
+rect -33 -130 33 -114
+<< polycont >>
+rect -17 80 17 114
+rect -17 -114 17 -80
+<< locali >>
+rect -33 80 -17 114
+rect 17 80 33 114
+rect -61 30 -27 46
+rect -61 -46 -27 -30
+rect 27 30 61 46
+rect 27 -46 61 -30
+rect -33 -114 -17 -80
+rect 17 -114 33 -80
+<< viali >>
+rect -17 80 17 114
+rect -61 -30 -27 30
+rect 27 -30 61 30
+rect -17 -114 17 -80
+<< metal1 >>
+rect -29 114 29 120
+rect -29 80 -17 114
+rect 17 80 29 114
+rect -29 74 29 80
+rect -67 30 -21 42
+rect -67 -30 -61 30
+rect -27 -30 -21 30
+rect -67 -42 -21 -30
+rect 21 30 67 42
+rect 21 -30 27 30
+rect 61 -30 67 30
+rect 21 -42 67 -30
+rect -29 -80 29 -74
+rect -29 -114 -17 -80
+rect 17 -114 29 -80
+rect -29 -120 29 -114
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string parameters w 0.42 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_LW2HKK.mag b/mag/sky130_fd_pr__nfet_01v8_LW2HKK.mag
new file mode 100644
index 0000000..24935a3
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_LW2HKK.mag
@@ -0,0 +1,100 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627668659
+<< error_p >>
+rect -29 592 29 598
+rect -29 558 -17 592
+rect -29 552 29 558
+rect -29 -558 29 -552
+rect -29 -592 -17 -558
+rect -29 -598 29 -592
+<< pwell >>
+rect -211 -730 211 730
+<< nmos >>
+rect -15 -520 15 520
+<< ndiff >>
+rect -73 508 -15 520
+rect -73 -508 -61 508
+rect -27 -508 -15 508
+rect -73 -520 -15 -508
+rect 15 508 73 520
+rect 15 -508 27 508
+rect 61 -508 73 508
+rect 15 -520 73 -508
+<< ndiffc >>
+rect -61 -508 -27 508
+rect 27 -508 61 508
+<< psubdiff >>
+rect -175 660 -79 694
+rect 79 660 175 694
+rect -175 598 -141 660
+rect 141 598 175 660
+rect -175 -660 -141 -598
+rect 141 -660 175 -598
+rect -175 -694 -79 -660
+rect 79 -694 175 -660
+<< psubdiffcont >>
+rect -79 660 79 694
+rect -175 -598 -141 598
+rect 141 -598 175 598
+rect -79 -694 79 -660
+<< poly >>
+rect -33 592 33 608
+rect -33 558 -17 592
+rect 17 558 33 592
+rect -33 542 33 558
+rect -15 520 15 542
+rect -15 -542 15 -520
+rect -33 -558 33 -542
+rect -33 -592 -17 -558
+rect 17 -592 33 -558
+rect -33 -608 33 -592
+<< polycont >>
+rect -17 558 17 592
+rect -17 -592 17 -558
+<< locali >>
+rect -175 660 -79 694
+rect 79 660 175 694
+rect -175 598 -141 660
+rect 141 598 175 660
+rect -33 558 -17 592
+rect 17 558 33 592
+rect -61 508 -27 524
+rect -61 -524 -27 -508
+rect 27 508 61 524
+rect 27 -524 61 -508
+rect -33 -592 -17 -558
+rect 17 -592 33 -558
+rect -175 -660 -141 -598
+rect 141 -660 175 -598
+rect -175 -694 -79 -660
+rect 79 -694 175 -660
+<< viali >>
+rect -17 558 17 592
+rect -61 -508 -27 508
+rect 27 -508 61 508
+rect -17 -592 17 -558
+<< metal1 >>
+rect -29 592 29 598
+rect -29 558 -17 592
+rect 17 558 29 592
+rect -29 552 29 558
+rect -67 508 -21 520
+rect -67 -508 -61 508
+rect -27 -508 -21 508
+rect -67 -520 -21 -508
+rect 21 508 67 520
+rect 21 -508 27 508
+rect 61 -508 67 508
+rect 21 -520 67 -508
+rect -29 -558 29 -552
+rect -29 -592 -17 -558
+rect 17 -592 29 -558
+rect -29 -598 29 -592
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -677 158 677
+string parameters w 5.2 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_PNXWEF.mag b/mag/sky130_fd_pr__nfet_01v8_PNXWEF.mag
new file mode 100644
index 0000000..27b1fb0
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_PNXWEF.mag
@@ -0,0 +1,1315 @@
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+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -2130 -457 2130 457
+string parameters w 3 l 0.150 m 1 nf 42 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_S3F2PV.mag b/mag/sky130_fd_pr__nfet_01v8_S3F2PV.mag
new file mode 100644
index 0000000..51e37e6
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_S3F2PV.mag
@@ -0,0 +1,1315 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626800441
+<< error_p >>
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+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -2130 -457 2130 457
+string parameters w 3 l 0.150 m 1 nf 42 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_SLJCGW.mag b/mag/sky130_fd_pr__nfet_01v8_SLJCGW.mag
new file mode 100644
index 0000000..cfdcbef
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_SLJCGW.mag
@@ -0,0 +1,60 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627111729
+<< error_p >>
+rect -29 83 29 89
+rect -29 49 -17 83
+rect -29 43 29 49
+<< nmos >>
+rect -15 -73 15 11
+<< ndiff >>
+rect -73 -1 -15 11
+rect -73 -61 -61 -1
+rect -27 -61 -15 -1
+rect -73 -73 -15 -61
+rect 15 -1 73 11
+rect 15 -61 27 -1
+rect 61 -61 73 -1
+rect 15 -73 73 -61
+<< ndiffc >>
+rect -61 -61 -27 -1
+rect 27 -61 61 -1
+<< poly >>
+rect -33 83 33 99
+rect -33 49 -17 83
+rect 17 49 33 83
+rect -33 33 33 49
+rect -15 11 15 33
+rect -15 -99 15 -73
+<< polycont >>
+rect -17 49 17 83
+<< locali >>
+rect -33 49 -17 83
+rect 17 49 33 83
+rect -61 -1 -27 15
+rect -61 -77 -27 -61
+rect 27 -1 61 15
+rect 27 -77 61 -61
+<< viali >>
+rect -17 49 17 83
+rect -61 -61 -27 -1
+rect 27 -61 61 -1
+<< metal1 >>
+rect -29 83 29 89
+rect -29 49 -17 83
+rect 17 49 29 83
+rect -29 43 29 49
+rect -67 -1 -21 11
+rect -67 -61 -61 -1
+rect -27 -61 -21 -1
+rect -67 -73 -21 -61
+rect 21 -1 67 11
+rect 21 -61 27 -1
+rect 61 -61 67 -1
+rect 21 -73 67 -61
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string parameters w 0.420 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_TY4QAD.mag b/mag/sky130_fd_pr__nfet_01v8_TY4QAD.mag
new file mode 100644
index 0000000..bff1a4e
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_TY4QAD.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627838634
+<< error_p >>
+rect -29 -307 29 -301
+rect -29 -341 -17 -307
+rect -29 -347 29 -341
+<< pwell >>
+rect -211 -479 211 479
+<< nmos >>
+rect -15 -269 15 331
+<< ndiff >>
+rect -73 319 -15 331
+rect -73 -257 -61 319
+rect -27 -257 -15 319
+rect -73 -269 -15 -257
+rect 15 319 73 331
+rect 15 -257 27 319
+rect 61 -257 73 319
+rect 15 -269 73 -257
+<< ndiffc >>
+rect -61 -257 -27 319
+rect 27 -257 61 319
+<< psubdiff >>
+rect -175 409 -79 443
+rect 79 409 175 443
+rect -175 347 -141 409
+rect 141 347 175 409
+rect -175 -409 -141 -347
+rect 141 -409 175 -347
+rect -175 -443 -79 -409
+rect 79 -443 175 -409
+<< psubdiffcont >>
+rect -79 409 79 443
+rect -175 -347 -141 347
+rect 141 -347 175 347
+rect -79 -443 79 -409
+<< poly >>
+rect -15 331 15 357
+rect -15 -291 15 -269
+rect -33 -307 33 -291
+rect -33 -341 -17 -307
+rect 17 -341 33 -307
+rect -33 -357 33 -341
+<< polycont >>
+rect -17 -341 17 -307
+<< locali >>
+rect -175 409 -79 443
+rect 79 409 175 443
+rect -175 347 -141 409
+rect 141 347 175 409
+rect -61 319 -27 335
+rect -61 -273 -27 -257
+rect 27 319 61 335
+rect 27 -273 61 -257
+rect -33 -341 -17 -307
+rect 17 -341 33 -307
+rect -175 -409 -141 -347
+rect 141 -409 175 -347
+rect -175 -443 -79 -409
+rect 79 -443 175 -409
+<< viali >>
+rect -61 -257 -27 319
+rect 27 -257 61 319
+rect -17 -341 17 -307
+<< metal1 >>
+rect -67 319 -21 331
+rect -67 -257 -61 319
+rect -27 -257 -21 319
+rect -67 -269 -21 -257
+rect 21 319 67 331
+rect 21 -257 27 319
+rect 61 -257 67 319
+rect 21 -269 67 -257
+rect -29 -307 29 -301
+rect -29 -341 -17 -307
+rect 17 -341 29 -307
+rect -29 -347 29 -341
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -426 158 426
+string parameters w 3 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_W9EUVL.mag b/mag/sky130_fd_pr__nfet_01v8_W9EUVL.mag
new file mode 100644
index 0000000..0487fa4
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_W9EUVL.mag
@@ -0,0 +1,115 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628069291
+<< error_p >>
+rect 19 672 77 678
+rect 19 638 31 672
+rect 19 632 77 638
+rect -77 -638 -19 -632
+rect -77 -672 -65 -638
+rect -77 -678 -19 -672
+<< pwell >>
+rect -263 -810 263 810
+<< nmos >>
+rect -63 -600 -33 600
+rect 33 -600 63 600
+<< ndiff >>
+rect -125 588 -63 600
+rect -125 -588 -113 588
+rect -79 -588 -63 588
+rect -125 -600 -63 -588
+rect -33 588 33 600
+rect -33 -588 -17 588
+rect 17 -588 33 588
+rect -33 -600 33 -588
+rect 63 588 125 600
+rect 63 -588 79 588
+rect 113 -588 125 588
+rect 63 -600 125 -588
+<< ndiffc >>
+rect -113 -588 -79 588
+rect -17 -588 17 588
+rect 79 -588 113 588
+<< psubdiff >>
+rect -227 740 -131 774
+rect 131 740 227 774
+rect -227 678 -193 740
+rect 193 678 227 740
+rect -227 -740 -193 -678
+rect 193 -740 227 -678
+rect -227 -774 -131 -740
+rect 131 -774 227 -740
+<< psubdiffcont >>
+rect -131 740 131 774
+rect -227 -678 -193 678
+rect 193 -678 227 678
+rect -131 -774 131 -740
+<< poly >>
+rect 15 672 81 688
+rect 15 638 31 672
+rect 65 638 81 672
+rect -63 600 -33 626
+rect 15 622 81 638
+rect 33 600 63 622
+rect -63 -622 -33 -600
+rect -81 -638 -15 -622
+rect 33 -626 63 -600
+rect -81 -672 -65 -638
+rect -31 -672 -15 -638
+rect -81 -688 -15 -672
+<< polycont >>
+rect 31 638 65 672
+rect -65 -672 -31 -638
+<< locali >>
+rect -227 740 -131 774
+rect 131 740 227 774
+rect -227 678 -193 740
+rect 193 678 227 740
+rect 15 638 31 672
+rect 65 638 81 672
+rect -113 588 -79 604
+rect -113 -604 -79 -588
+rect -17 588 17 604
+rect -17 -604 17 -588
+rect 79 588 113 604
+rect 79 -604 113 -588
+rect -81 -672 -65 -638
+rect -31 -672 -15 -638
+rect -227 -740 -193 -678
+rect 193 -740 227 -678
+rect -227 -774 -131 -740
+rect 131 -774 227 -740
+<< viali >>
+rect 31 638 65 672
+rect -113 -588 -79 588
+rect -17 -588 17 588
+rect 79 -588 113 588
+rect -65 -672 -31 -638
+<< metal1 >>
+rect 19 672 77 678
+rect 19 638 31 672
+rect 65 638 77 672
+rect 19 632 77 638
+rect -119 588 -73 600
+rect -119 -588 -113 588
+rect -79 -588 -73 588
+rect -119 -600 -73 -588
+rect -23 588 23 600
+rect -23 -588 -17 588
+rect 17 -588 23 588
+rect -23 -600 23 -588
+rect 73 588 119 600
+rect 73 -588 79 588
+rect 113 -588 119 588
+rect 73 -600 119 -588
+rect -77 -638 -19 -632
+rect -77 -672 -65 -638
+rect -31 -672 -19 -638
+rect -77 -678 -19 -672
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -210 -757 210 757
+string parameters w 6 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_XG2GE7.mag b/mag/sky130_fd_pr__nfet_01v8_XG2GE7.mag
new file mode 100644
index 0000000..bb3e8ed
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_XG2GE7.mag
@@ -0,0 +1,115 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628080314
+<< error_p >>
+rect 19 582 77 588
+rect 19 548 31 582
+rect 19 542 77 548
+rect -77 -548 -19 -542
+rect -77 -582 -65 -548
+rect -77 -588 -19 -582
+<< pwell >>
+rect -263 -720 263 720
+<< nmos >>
+rect -63 -510 -33 510
+rect 33 -510 63 510
+<< ndiff >>
+rect -125 498 -63 510
+rect -125 -498 -113 498
+rect -79 -498 -63 498
+rect -125 -510 -63 -498
+rect -33 498 33 510
+rect -33 -498 -17 498
+rect 17 -498 33 498
+rect -33 -510 33 -498
+rect 63 498 125 510
+rect 63 -498 79 498
+rect 113 -498 125 498
+rect 63 -510 125 -498
+<< ndiffc >>
+rect -113 -498 -79 498
+rect -17 -498 17 498
+rect 79 -498 113 498
+<< psubdiff >>
+rect -227 650 -131 684
+rect 131 650 227 684
+rect -227 588 -193 650
+rect 193 588 227 650
+rect -227 -650 -193 -588
+rect 193 -650 227 -588
+rect -227 -684 -131 -650
+rect 131 -684 227 -650
+<< psubdiffcont >>
+rect -131 650 131 684
+rect -227 -588 -193 588
+rect 193 -588 227 588
+rect -131 -684 131 -650
+<< poly >>
+rect 15 582 81 598
+rect 15 548 31 582
+rect 65 548 81 582
+rect -63 510 -33 536
+rect 15 532 81 548
+rect 33 510 63 532
+rect -63 -532 -33 -510
+rect -81 -548 -15 -532
+rect 33 -536 63 -510
+rect -81 -582 -65 -548
+rect -31 -582 -15 -548
+rect -81 -598 -15 -582
+<< polycont >>
+rect 31 548 65 582
+rect -65 -582 -31 -548
+<< locali >>
+rect -227 650 -131 684
+rect 131 650 227 684
+rect -227 588 -193 650
+rect 193 588 227 650
+rect 15 548 31 582
+rect 65 548 81 582
+rect -113 498 -79 514
+rect -113 -514 -79 -498
+rect -17 498 17 514
+rect -17 -514 17 -498
+rect 79 498 113 514
+rect 79 -514 113 -498
+rect -81 -582 -65 -548
+rect -31 -582 -15 -548
+rect -227 -650 -193 -588
+rect 193 -650 227 -588
+rect -227 -684 -131 -650
+rect 131 -684 227 -650
+<< viali >>
+rect 31 548 65 582
+rect -113 -498 -79 498
+rect -17 -498 17 498
+rect 79 -498 113 498
+rect -65 -582 -31 -548
+<< metal1 >>
+rect 19 582 77 588
+rect 19 548 31 582
+rect 65 548 77 582
+rect 19 542 77 548
+rect -119 498 -73 510
+rect -119 -498 -113 498
+rect -79 -498 -73 498
+rect -119 -510 -73 -498
+rect -23 498 23 510
+rect -23 -498 -17 498
+rect 17 -498 23 498
+rect -23 -510 23 -498
+rect 73 498 119 510
+rect 73 -498 79 498
+rect 113 -498 119 498
+rect 73 -510 119 -498
+rect -77 -548 -19 -542
+rect -77 -582 -65 -548
+rect -31 -582 -19 -548
+rect -77 -588 -19 -582
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -210 -667 210 667
+string parameters w 5.1 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_27F7GK.mag b/mag/sky130_fd_pr__pfet_01v8_27F7GK.mag
new file mode 100644
index 0000000..694acb1
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_27F7GK.mag
@@ -0,0 +1,235 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627668659
+<< error_p >>
+rect -173 581 -115 587
+rect 19 581 77 587
+rect 211 581 269 587
+rect -173 547 -161 581
+rect 19 547 31 581
+rect 211 547 223 581
+rect -173 541 -115 547
+rect 19 541 77 547
+rect 211 541 269 547
+rect -269 -547 -211 -541
+rect -77 -547 -19 -541
+rect 115 -547 173 -541
+rect -269 -581 -257 -547
+rect -77 -581 -65 -547
+rect 115 -581 127 -547
+rect -269 -587 -211 -581
+rect -77 -587 -19 -581
+rect 115 -587 173 -581
+<< nwell >>
+rect -455 -719 455 719
+<< pmos >>
+rect -255 -500 -225 500
+rect -159 -500 -129 500
+rect -63 -500 -33 500
+rect 33 -500 63 500
+rect 129 -500 159 500
+rect 225 -500 255 500
+<< pdiff >>
+rect -317 488 -255 500
+rect -317 -488 -305 488
+rect -271 -488 -255 488
+rect -317 -500 -255 -488
+rect -225 488 -159 500
+rect -225 -488 -209 488
+rect -175 -488 -159 488
+rect -225 -500 -159 -488
+rect -129 488 -63 500
+rect -129 -488 -113 488
+rect -79 -488 -63 488
+rect -129 -500 -63 -488
+rect -33 488 33 500
+rect -33 -488 -17 488
+rect 17 -488 33 488
+rect -33 -500 33 -488
+rect 63 488 129 500
+rect 63 -488 79 488
+rect 113 -488 129 488
+rect 63 -500 129 -488
+rect 159 488 225 500
+rect 159 -488 175 488
+rect 209 -488 225 488
+rect 159 -500 225 -488
+rect 255 488 317 500
+rect 255 -488 271 488
+rect 305 -488 317 488
+rect 255 -500 317 -488
+<< pdiffc >>
+rect -305 -488 -271 488
+rect -209 -488 -175 488
+rect -113 -488 -79 488
+rect -17 -488 17 488
+rect 79 -488 113 488
+rect 175 -488 209 488
+rect 271 -488 305 488
+<< nsubdiff >>
+rect -419 649 -323 683
+rect 323 649 419 683
+rect -419 587 -385 649
+rect 385 587 419 649
+rect -419 -649 -385 -587
+rect 385 -649 419 -587
+rect -419 -683 -323 -649
+rect 323 -683 419 -649
+<< nsubdiffcont >>
+rect -323 649 323 683
+rect -419 -587 -385 587
+rect 385 -587 419 587
+rect -323 -683 323 -649
+<< poly >>
+rect -177 581 -111 597
+rect -177 547 -161 581
+rect -127 547 -111 581
+rect -177 531 -111 547
+rect 15 581 81 597
+rect 15 547 31 581
+rect 65 547 81 581
+rect 15 531 81 547
+rect 207 581 273 597
+rect 207 547 223 581
+rect 257 547 273 581
+rect 207 531 273 547
+rect -255 500 -225 526
+rect -159 500 -129 531
+rect -63 500 -33 526
+rect 33 500 63 531
+rect 129 500 159 526
+rect 225 500 255 531
+rect -255 -531 -225 -500
+rect -159 -526 -129 -500
+rect -63 -531 -33 -500
+rect 33 -526 63 -500
+rect 129 -531 159 -500
+rect 225 -526 255 -500
+rect -273 -547 -207 -531
+rect -273 -581 -257 -547
+rect -223 -581 -207 -547
+rect -273 -597 -207 -581
+rect -81 -547 -15 -531
+rect -81 -581 -65 -547
+rect -31 -581 -15 -547
+rect -81 -597 -15 -581
+rect 111 -547 177 -531
+rect 111 -581 127 -547
+rect 161 -581 177 -547
+rect 111 -597 177 -581
+<< polycont >>
+rect -161 547 -127 581
+rect 31 547 65 581
+rect 223 547 257 581
+rect -257 -581 -223 -547
+rect -65 -581 -31 -547
+rect 127 -581 161 -547
+<< locali >>
+rect -419 649 -323 683
+rect 323 649 419 683
+rect -419 587 -385 649
+rect 385 587 419 649
+rect -177 547 -161 581
+rect -127 547 -111 581
+rect 15 547 31 581
+rect 65 547 81 581
+rect 207 547 223 581
+rect 257 547 273 581
+rect -305 488 -271 504
+rect -305 -504 -271 -488
+rect -209 488 -175 504
+rect -209 -504 -175 -488
+rect -113 488 -79 504
+rect -113 -504 -79 -488
+rect -17 488 17 504
+rect -17 -504 17 -488
+rect 79 488 113 504
+rect 79 -504 113 -488
+rect 175 488 209 504
+rect 175 -504 209 -488
+rect 271 488 305 504
+rect 271 -504 305 -488
+rect -273 -581 -257 -547
+rect -223 -581 -207 -547
+rect -81 -581 -65 -547
+rect -31 -581 -15 -547
+rect 111 -581 127 -547
+rect 161 -581 177 -547
+rect -419 -649 -385 -587
+rect 385 -649 419 -587
+rect -419 -683 -323 -649
+rect 323 -683 419 -649
+<< viali >>
+rect -161 547 -127 581
+rect 31 547 65 581
+rect 223 547 257 581
+rect -305 -488 -271 488
+rect -209 -488 -175 488
+rect -113 -488 -79 488
+rect -17 -488 17 488
+rect 79 -488 113 488
+rect 175 -488 209 488
+rect 271 -488 305 488
+rect -257 -581 -223 -547
+rect -65 -581 -31 -547
+rect 127 -581 161 -547
+<< metal1 >>
+rect -173 581 -115 587
+rect -173 547 -161 581
+rect -127 547 -115 581
+rect -173 541 -115 547
+rect 19 581 77 587
+rect 19 547 31 581
+rect 65 547 77 581
+rect 19 541 77 547
+rect 211 581 269 587
+rect 211 547 223 581
+rect 257 547 269 581
+rect 211 541 269 547
+rect -311 488 -265 500
+rect -311 -488 -305 488
+rect -271 -488 -265 488
+rect -311 -500 -265 -488
+rect -215 488 -169 500
+rect -215 -488 -209 488
+rect -175 -488 -169 488
+rect -215 -500 -169 -488
+rect -119 488 -73 500
+rect -119 -488 -113 488
+rect -79 -488 -73 488
+rect -119 -500 -73 -488
+rect -23 488 23 500
+rect -23 -488 -17 488
+rect 17 -488 23 488
+rect -23 -500 23 -488
+rect 73 488 119 500
+rect 73 -488 79 488
+rect 113 -488 119 488
+rect 73 -500 119 -488
+rect 169 488 215 500
+rect 169 -488 175 488
+rect 209 -488 215 488
+rect 169 -500 215 -488
+rect 265 488 311 500
+rect 265 -488 271 488
+rect 305 -488 311 488
+rect 265 -500 311 -488
+rect -269 -547 -211 -541
+rect -269 -581 -257 -547
+rect -223 -581 -211 -547
+rect -269 -587 -211 -581
+rect -77 -547 -19 -541
+rect -77 -581 -65 -547
+rect -31 -581 -19 -547
+rect -77 -587 -19 -581
+rect 115 -547 173 -541
+rect 115 -581 127 -547
+rect 161 -581 173 -547
+rect 115 -587 173 -581
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -402 -666 402 666
+string parameters w 5 l 0.15 m 1 nf 6 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_396TWK.mag b/mag/sky130_fd_pr__pfet_01v8_396TWK.mag
new file mode 100644
index 0000000..f2e045b
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_396TWK.mag
@@ -0,0 +1,295 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628080314
+<< error_p >>
+rect -269 511 -211 517
+rect -77 511 -19 517
+rect 115 511 173 517
+rect 307 511 365 517
+rect -269 477 -257 511
+rect -77 477 -65 511
+rect 115 477 127 511
+rect 307 477 319 511
+rect -269 471 -211 477
+rect -77 471 -19 477
+rect 115 471 173 477
+rect 307 471 365 477
+rect -365 -477 -307 -471
+rect -173 -477 -115 -471
+rect 19 -477 77 -471
+rect 211 -477 269 -471
+rect -365 -511 -353 -477
+rect -173 -511 -161 -477
+rect 19 -511 31 -477
+rect 211 -511 223 -477
+rect -365 -517 -307 -511
+rect -173 -517 -115 -511
+rect 19 -517 77 -511
+rect 211 -517 269 -511
+<< nwell >>
+rect -551 -649 551 649
+<< pmos >>
+rect -351 -430 -321 430
+rect -255 -430 -225 430
+rect -159 -430 -129 430
+rect -63 -430 -33 430
+rect 33 -430 63 430
+rect 129 -430 159 430
+rect 225 -430 255 430
+rect 321 -430 351 430
+<< pdiff >>
+rect -413 418 -351 430
+rect -413 -418 -401 418
+rect -367 -418 -351 418
+rect -413 -430 -351 -418
+rect -321 418 -255 430
+rect -321 -418 -305 418
+rect -271 -418 -255 418
+rect -321 -430 -255 -418
+rect -225 418 -159 430
+rect -225 -418 -209 418
+rect -175 -418 -159 418
+rect -225 -430 -159 -418
+rect -129 418 -63 430
+rect -129 -418 -113 418
+rect -79 -418 -63 418
+rect -129 -430 -63 -418
+rect -33 418 33 430
+rect -33 -418 -17 418
+rect 17 -418 33 418
+rect -33 -430 33 -418
+rect 63 418 129 430
+rect 63 -418 79 418
+rect 113 -418 129 418
+rect 63 -430 129 -418
+rect 159 418 225 430
+rect 159 -418 175 418
+rect 209 -418 225 418
+rect 159 -430 225 -418
+rect 255 418 321 430
+rect 255 -418 271 418
+rect 305 -418 321 418
+rect 255 -430 321 -418
+rect 351 418 413 430
+rect 351 -418 367 418
+rect 401 -418 413 418
+rect 351 -430 413 -418
+<< pdiffc >>
+rect -401 -418 -367 418
+rect -305 -418 -271 418
+rect -209 -418 -175 418
+rect -113 -418 -79 418
+rect -17 -418 17 418
+rect 79 -418 113 418
+rect 175 -418 209 418
+rect 271 -418 305 418
+rect 367 -418 401 418
+<< nsubdiff >>
+rect -515 579 -419 613
+rect 419 579 515 613
+rect -515 517 -481 579
+rect 481 517 515 579
+rect -515 -579 -481 -517
+rect 481 -579 515 -517
+rect -515 -613 -419 -579
+rect 419 -613 515 -579
+<< nsubdiffcont >>
+rect -419 579 419 613
+rect -515 -517 -481 517
+rect 481 -517 515 517
+rect -419 -613 419 -579
+<< poly >>
+rect -273 511 -207 527
+rect -273 477 -257 511
+rect -223 477 -207 511
+rect -273 461 -207 477
+rect -81 511 -15 527
+rect -81 477 -65 511
+rect -31 477 -15 511
+rect -81 461 -15 477
+rect 111 511 177 527
+rect 111 477 127 511
+rect 161 477 177 511
+rect 111 461 177 477
+rect 303 511 369 527
+rect 303 477 319 511
+rect 353 477 369 511
+rect 303 461 369 477
+rect -351 430 -321 456
+rect -255 430 -225 461
+rect -159 430 -129 456
+rect -63 430 -33 461
+rect 33 430 63 456
+rect 129 430 159 461
+rect 225 430 255 456
+rect 321 430 351 461
+rect -351 -461 -321 -430
+rect -255 -456 -225 -430
+rect -159 -461 -129 -430
+rect -63 -456 -33 -430
+rect 33 -461 63 -430
+rect 129 -456 159 -430
+rect 225 -461 255 -430
+rect 321 -456 351 -430
+rect -369 -477 -303 -461
+rect -369 -511 -353 -477
+rect -319 -511 -303 -477
+rect -369 -527 -303 -511
+rect -177 -477 -111 -461
+rect -177 -511 -161 -477
+rect -127 -511 -111 -477
+rect -177 -527 -111 -511
+rect 15 -477 81 -461
+rect 15 -511 31 -477
+rect 65 -511 81 -477
+rect 15 -527 81 -511
+rect 207 -477 273 -461
+rect 207 -511 223 -477
+rect 257 -511 273 -477
+rect 207 -527 273 -511
+<< polycont >>
+rect -257 477 -223 511
+rect -65 477 -31 511
+rect 127 477 161 511
+rect 319 477 353 511
+rect -353 -511 -319 -477
+rect -161 -511 -127 -477
+rect 31 -511 65 -477
+rect 223 -511 257 -477
+<< locali >>
+rect -515 579 -419 613
+rect 419 579 515 613
+rect -515 517 -481 579
+rect 481 517 515 579
+rect -273 477 -257 511
+rect -223 477 -207 511
+rect -81 477 -65 511
+rect -31 477 -15 511
+rect 111 477 127 511
+rect 161 477 177 511
+rect 303 477 319 511
+rect 353 477 369 511
+rect -401 418 -367 434
+rect -401 -434 -367 -418
+rect -305 418 -271 434
+rect -305 -434 -271 -418
+rect -209 418 -175 434
+rect -209 -434 -175 -418
+rect -113 418 -79 434
+rect -113 -434 -79 -418
+rect -17 418 17 434
+rect -17 -434 17 -418
+rect 79 418 113 434
+rect 79 -434 113 -418
+rect 175 418 209 434
+rect 175 -434 209 -418
+rect 271 418 305 434
+rect 271 -434 305 -418
+rect 367 418 401 434
+rect 367 -434 401 -418
+rect -369 -511 -353 -477
+rect -319 -511 -303 -477
+rect -177 -511 -161 -477
+rect -127 -511 -111 -477
+rect 15 -511 31 -477
+rect 65 -511 81 -477
+rect 207 -511 223 -477
+rect 257 -511 273 -477
+rect -515 -579 -481 -517
+rect 481 -579 515 -517
+rect -515 -613 -419 -579
+rect 419 -613 515 -579
+<< viali >>
+rect -257 477 -223 511
+rect -65 477 -31 511
+rect 127 477 161 511
+rect 319 477 353 511
+rect -401 -418 -367 418
+rect -305 -418 -271 418
+rect -209 -418 -175 418
+rect -113 -418 -79 418
+rect -17 -418 17 418
+rect 79 -418 113 418
+rect 175 -418 209 418
+rect 271 -418 305 418
+rect 367 -418 401 418
+rect -353 -511 -319 -477
+rect -161 -511 -127 -477
+rect 31 -511 65 -477
+rect 223 -511 257 -477
+<< metal1 >>
+rect -269 511 -211 517
+rect -269 477 -257 511
+rect -223 477 -211 511
+rect -269 471 -211 477
+rect -77 511 -19 517
+rect -77 477 -65 511
+rect -31 477 -19 511
+rect -77 471 -19 477
+rect 115 511 173 517
+rect 115 477 127 511
+rect 161 477 173 511
+rect 115 471 173 477
+rect 307 511 365 517
+rect 307 477 319 511
+rect 353 477 365 511
+rect 307 471 365 477
+rect -407 418 -361 430
+rect -407 -418 -401 418
+rect -367 -418 -361 418
+rect -407 -430 -361 -418
+rect -311 418 -265 430
+rect -311 -418 -305 418
+rect -271 -418 -265 418
+rect -311 -430 -265 -418
+rect -215 418 -169 430
+rect -215 -418 -209 418
+rect -175 -418 -169 418
+rect -215 -430 -169 -418
+rect -119 418 -73 430
+rect -119 -418 -113 418
+rect -79 -418 -73 418
+rect -119 -430 -73 -418
+rect -23 418 23 430
+rect -23 -418 -17 418
+rect 17 -418 23 418
+rect -23 -430 23 -418
+rect 73 418 119 430
+rect 73 -418 79 418
+rect 113 -418 119 418
+rect 73 -430 119 -418
+rect 169 418 215 430
+rect 169 -418 175 418
+rect 209 -418 215 418
+rect 169 -430 215 -418
+rect 265 418 311 430
+rect 265 -418 271 418
+rect 305 -418 311 418
+rect 265 -430 311 -418
+rect 361 418 407 430
+rect 361 -418 367 418
+rect 401 -418 407 418
+rect 361 -430 407 -418
+rect -365 -477 -307 -471
+rect -365 -511 -353 -477
+rect -319 -511 -307 -477
+rect -365 -517 -307 -511
+rect -173 -477 -115 -471
+rect -173 -511 -161 -477
+rect -127 -511 -115 -477
+rect -173 -517 -115 -511
+rect 19 -477 77 -471
+rect 19 -511 31 -477
+rect 65 -511 77 -477
+rect 19 -517 77 -511
+rect 211 -477 269 -471
+rect 211 -511 223 -477
+rect 257 -511 269 -477
+rect 211 -517 269 -511
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -498 -596 498 596
+string parameters w 4.3 l 0.15 m 1 nf 8 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_3BZUWK.mag b/mag/sky130_fd_pr__pfet_01v8_3BZUWK.mag
new file mode 100644
index 0000000..1ee02e6
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_3BZUWK.mag
@@ -0,0 +1,295 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628068563
+<< error_p >>
+rect -269 501 -211 507
+rect -77 501 -19 507
+rect 115 501 173 507
+rect 307 501 365 507
+rect -269 467 -257 501
+rect -77 467 -65 501
+rect 115 467 127 501
+rect 307 467 319 501
+rect -269 461 -211 467
+rect -77 461 -19 467
+rect 115 461 173 467
+rect 307 461 365 467
+rect -365 -467 -307 -461
+rect -173 -467 -115 -461
+rect 19 -467 77 -461
+rect 211 -467 269 -461
+rect -365 -501 -353 -467
+rect -173 -501 -161 -467
+rect 19 -501 31 -467
+rect 211 -501 223 -467
+rect -365 -507 -307 -501
+rect -173 -507 -115 -501
+rect 19 -507 77 -501
+rect 211 -507 269 -501
+<< nwell >>
+rect -551 -639 551 639
+<< pmos >>
+rect -351 -420 -321 420
+rect -255 -420 -225 420
+rect -159 -420 -129 420
+rect -63 -420 -33 420
+rect 33 -420 63 420
+rect 129 -420 159 420
+rect 225 -420 255 420
+rect 321 -420 351 420
+<< pdiff >>
+rect -413 408 -351 420
+rect -413 -408 -401 408
+rect -367 -408 -351 408
+rect -413 -420 -351 -408
+rect -321 408 -255 420
+rect -321 -408 -305 408
+rect -271 -408 -255 408
+rect -321 -420 -255 -408
+rect -225 408 -159 420
+rect -225 -408 -209 408
+rect -175 -408 -159 408
+rect -225 -420 -159 -408
+rect -129 408 -63 420
+rect -129 -408 -113 408
+rect -79 -408 -63 408
+rect -129 -420 -63 -408
+rect -33 408 33 420
+rect -33 -408 -17 408
+rect 17 -408 33 408
+rect -33 -420 33 -408
+rect 63 408 129 420
+rect 63 -408 79 408
+rect 113 -408 129 408
+rect 63 -420 129 -408
+rect 159 408 225 420
+rect 159 -408 175 408
+rect 209 -408 225 408
+rect 159 -420 225 -408
+rect 255 408 321 420
+rect 255 -408 271 408
+rect 305 -408 321 408
+rect 255 -420 321 -408
+rect 351 408 413 420
+rect 351 -408 367 408
+rect 401 -408 413 408
+rect 351 -420 413 -408
+<< pdiffc >>
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+rect -305 -408 -271 408
+rect -209 -408 -175 408
+rect -113 -408 -79 408
+rect -17 -408 17 408
+rect 79 -408 113 408
+rect 175 -408 209 408
+rect 271 -408 305 408
+rect 367 -408 401 408
+<< nsubdiff >>
+rect -515 569 -419 603
+rect 419 569 515 603
+rect -515 507 -481 569
+rect 481 507 515 569
+rect -515 -569 -481 -507
+rect 481 -569 515 -507
+rect -515 -603 -419 -569
+rect 419 -603 515 -569
+<< nsubdiffcont >>
+rect -419 569 419 603
+rect -515 -507 -481 507
+rect 481 -507 515 507
+rect -419 -603 419 -569
+<< poly >>
+rect -273 501 -207 517
+rect -273 467 -257 501
+rect -223 467 -207 501
+rect -273 451 -207 467
+rect -81 501 -15 517
+rect -81 467 -65 501
+rect -31 467 -15 501
+rect -81 451 -15 467
+rect 111 501 177 517
+rect 111 467 127 501
+rect 161 467 177 501
+rect 111 451 177 467
+rect 303 501 369 517
+rect 303 467 319 501
+rect 353 467 369 501
+rect 303 451 369 467
+rect -351 420 -321 446
+rect -255 420 -225 451
+rect -159 420 -129 446
+rect -63 420 -33 451
+rect 33 420 63 446
+rect 129 420 159 451
+rect 225 420 255 446
+rect 321 420 351 451
+rect -351 -451 -321 -420
+rect -255 -446 -225 -420
+rect -159 -451 -129 -420
+rect -63 -446 -33 -420
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+rect 129 -446 159 -420
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+rect -369 -467 -303 -451
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+rect -319 -501 -303 -467
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+rect 65 -501 81 -467
+rect 15 -517 81 -501
+rect 207 -467 273 -451
+rect 207 -501 223 -467
+rect 257 -501 273 -467
+rect 207 -517 273 -501
+<< polycont >>
+rect -257 467 -223 501
+rect -65 467 -31 501
+rect 127 467 161 501
+rect 319 467 353 501
+rect -353 -501 -319 -467
+rect -161 -501 -127 -467
+rect 31 -501 65 -467
+rect 223 -501 257 -467
+<< locali >>
+rect -515 569 -419 603
+rect 419 569 515 603
+rect -515 507 -481 569
+rect 481 507 515 569
+rect -273 467 -257 501
+rect -223 467 -207 501
+rect -81 467 -65 501
+rect -31 467 -15 501
+rect 111 467 127 501
+rect 161 467 177 501
+rect 303 467 319 501
+rect 353 467 369 501
+rect -401 408 -367 424
+rect -401 -424 -367 -408
+rect -305 408 -271 424
+rect -305 -424 -271 -408
+rect -209 408 -175 424
+rect -209 -424 -175 -408
+rect -113 408 -79 424
+rect -113 -424 -79 -408
+rect -17 408 17 424
+rect -17 -424 17 -408
+rect 79 408 113 424
+rect 79 -424 113 -408
+rect 175 408 209 424
+rect 175 -424 209 -408
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+rect 367 408 401 424
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+rect -369 -501 -353 -467
+rect -319 -501 -303 -467
+rect -177 -501 -161 -467
+rect -127 -501 -111 -467
+rect 15 -501 31 -467
+rect 65 -501 81 -467
+rect 207 -501 223 -467
+rect 257 -501 273 -467
+rect -515 -569 -481 -507
+rect 481 -569 515 -507
+rect -515 -603 -419 -569
+rect 419 -603 515 -569
+<< viali >>
+rect -257 467 -223 501
+rect -65 467 -31 501
+rect 127 467 161 501
+rect 319 467 353 501
+rect -401 -408 -367 408
+rect -305 -408 -271 408
+rect -209 -408 -175 408
+rect -113 -408 -79 408
+rect -17 -408 17 408
+rect 79 -408 113 408
+rect 175 -408 209 408
+rect 271 -408 305 408
+rect 367 -408 401 408
+rect -353 -501 -319 -467
+rect -161 -501 -127 -467
+rect 31 -501 65 -467
+rect 223 -501 257 -467
+<< metal1 >>
+rect -269 501 -211 507
+rect -269 467 -257 501
+rect -223 467 -211 501
+rect -269 461 -211 467
+rect -77 501 -19 507
+rect -77 467 -65 501
+rect -31 467 -19 501
+rect -77 461 -19 467
+rect 115 501 173 507
+rect 115 467 127 501
+rect 161 467 173 501
+rect 115 461 173 467
+rect 307 501 365 507
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+rect 307 461 365 467
+rect -407 408 -361 420
+rect -407 -408 -401 408
+rect -367 -408 -361 408
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+rect -311 408 -265 420
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+rect -271 -408 -265 408
+rect -311 -420 -265 -408
+rect -215 408 -169 420
+rect -215 -408 -209 408
+rect -175 -408 -169 408
+rect -215 -420 -169 -408
+rect -119 408 -73 420
+rect -119 -408 -113 408
+rect -79 -408 -73 408
+rect -119 -420 -73 -408
+rect -23 408 23 420
+rect -23 -408 -17 408
+rect 17 -408 23 408
+rect -23 -420 23 -408
+rect 73 408 119 420
+rect 73 -408 79 408
+rect 113 -408 119 408
+rect 73 -420 119 -408
+rect 169 408 215 420
+rect 169 -408 175 408
+rect 209 -408 215 408
+rect 169 -420 215 -408
+rect 265 408 311 420
+rect 265 -408 271 408
+rect 305 -408 311 408
+rect 265 -420 311 -408
+rect 361 408 407 420
+rect 361 -408 367 408
+rect 401 -408 407 408
+rect 361 -420 407 -408
+rect -365 -467 -307 -461
+rect -365 -501 -353 -467
+rect -319 -501 -307 -467
+rect -365 -507 -307 -501
+rect -173 -467 -115 -461
+rect -173 -501 -161 -467
+rect -127 -501 -115 -467
+rect -173 -507 -115 -501
+rect 19 -467 77 -461
+rect 19 -501 31 -467
+rect 65 -501 77 -467
+rect 19 -507 77 -501
+rect 211 -467 269 -461
+rect 211 -501 223 -467
+rect 257 -501 269 -467
+rect 211 -507 269 -501
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -498 -586 498 586
+string parameters w 4.2 l 0.15 m 1 nf 8 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_3FVSWK.mag b/mag/sky130_fd_pr__pfet_01v8_3FVSWK.mag
new file mode 100644
index 0000000..5df0aa2
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_3FVSWK.mag
@@ -0,0 +1,295 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628069291
+<< error_p >>
+rect -269 521 -211 527
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+rect 307 521 365 527
+rect -269 487 -257 521
+rect -77 487 -65 521
+rect 115 487 127 521
+rect 307 487 319 521
+rect -269 481 -211 487
+rect -77 481 -19 487
+rect 115 481 173 487
+rect 307 481 365 487
+rect -365 -487 -307 -481
+rect -173 -487 -115 -481
+rect 19 -487 77 -481
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+rect -365 -521 -353 -487
+rect -173 -521 -161 -487
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+rect 211 -521 223 -487
+rect -365 -527 -307 -521
+rect -173 -527 -115 -521
+rect 19 -527 77 -521
+rect 211 -527 269 -521
+<< nwell >>
+rect -551 -659 551 659
+<< pmos >>
+rect -351 -440 -321 440
+rect -255 -440 -225 440
+rect -159 -440 -129 440
+rect -63 -440 -33 440
+rect 33 -440 63 440
+rect 129 -440 159 440
+rect 225 -440 255 440
+rect 321 -440 351 440
+<< pdiff >>
+rect -413 428 -351 440
+rect -413 -428 -401 428
+rect -367 -428 -351 428
+rect -413 -440 -351 -428
+rect -321 428 -255 440
+rect -321 -428 -305 428
+rect -271 -428 -255 428
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+rect -225 428 -159 440
+rect -225 -428 -209 428
+rect -175 -428 -159 428
+rect -225 -440 -159 -428
+rect -129 428 -63 440
+rect -129 -428 -113 428
+rect -79 -428 -63 428
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+rect -33 428 33 440
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+rect 63 428 129 440
+rect 63 -428 79 428
+rect 113 -428 129 428
+rect 63 -440 129 -428
+rect 159 428 225 440
+rect 159 -428 175 428
+rect 209 -428 225 428
+rect 159 -440 225 -428
+rect 255 428 321 440
+rect 255 -428 271 428
+rect 305 -428 321 428
+rect 255 -440 321 -428
+rect 351 428 413 440
+rect 351 -428 367 428
+rect 401 -428 413 428
+rect 351 -440 413 -428
+<< pdiffc >>
+rect -401 -428 -367 428
+rect -305 -428 -271 428
+rect -209 -428 -175 428
+rect -113 -428 -79 428
+rect -17 -428 17 428
+rect 79 -428 113 428
+rect 175 -428 209 428
+rect 271 -428 305 428
+rect 367 -428 401 428
+<< nsubdiff >>
+rect -515 589 -419 623
+rect 419 589 515 623
+rect -515 527 -481 589
+rect 481 527 515 589
+rect -515 -589 -481 -527
+rect 481 -589 515 -527
+rect -515 -623 -419 -589
+rect 419 -623 515 -589
+<< nsubdiffcont >>
+rect -419 589 419 623
+rect -515 -527 -481 527
+rect 481 -527 515 527
+rect -419 -623 419 -589
+<< poly >>
+rect -273 521 -207 537
+rect -273 487 -257 521
+rect -223 487 -207 521
+rect -273 471 -207 487
+rect -81 521 -15 537
+rect -81 487 -65 521
+rect -31 487 -15 521
+rect -81 471 -15 487
+rect 111 521 177 537
+rect 111 487 127 521
+rect 161 487 177 521
+rect 111 471 177 487
+rect 303 521 369 537
+rect 303 487 319 521
+rect 353 487 369 521
+rect 303 471 369 487
+rect -351 440 -321 466
+rect -255 440 -225 471
+rect -159 440 -129 466
+rect -63 440 -33 471
+rect 33 440 63 466
+rect 129 440 159 471
+rect 225 440 255 466
+rect 321 440 351 471
+rect -351 -471 -321 -440
+rect -255 -466 -225 -440
+rect -159 -471 -129 -440
+rect -63 -466 -33 -440
+rect 33 -471 63 -440
+rect 129 -466 159 -440
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+rect -369 -487 -303 -471
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+rect -319 -521 -303 -487
+rect -369 -537 -303 -521
+rect -177 -487 -111 -471
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+rect -127 -521 -111 -487
+rect -177 -537 -111 -521
+rect 15 -487 81 -471
+rect 15 -521 31 -487
+rect 65 -521 81 -487
+rect 15 -537 81 -521
+rect 207 -487 273 -471
+rect 207 -521 223 -487
+rect 257 -521 273 -487
+rect 207 -537 273 -521
+<< polycont >>
+rect -257 487 -223 521
+rect -65 487 -31 521
+rect 127 487 161 521
+rect 319 487 353 521
+rect -353 -521 -319 -487
+rect -161 -521 -127 -487
+rect 31 -521 65 -487
+rect 223 -521 257 -487
+<< locali >>
+rect -515 589 -419 623
+rect 419 589 515 623
+rect -515 527 -481 589
+rect 481 527 515 589
+rect -273 487 -257 521
+rect -223 487 -207 521
+rect -81 487 -65 521
+rect -31 487 -15 521
+rect 111 487 127 521
+rect 161 487 177 521
+rect 303 487 319 521
+rect 353 487 369 521
+rect -401 428 -367 444
+rect -401 -444 -367 -428
+rect -305 428 -271 444
+rect -305 -444 -271 -428
+rect -209 428 -175 444
+rect -209 -444 -175 -428
+rect -113 428 -79 444
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+rect -17 -444 17 -428
+rect 79 428 113 444
+rect 79 -444 113 -428
+rect 175 428 209 444
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+rect 271 428 305 444
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+rect 367 428 401 444
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+rect -369 -521 -353 -487
+rect -319 -521 -303 -487
+rect -177 -521 -161 -487
+rect -127 -521 -111 -487
+rect 15 -521 31 -487
+rect 65 -521 81 -487
+rect 207 -521 223 -487
+rect 257 -521 273 -487
+rect -515 -589 -481 -527
+rect 481 -589 515 -527
+rect -515 -623 -419 -589
+rect 419 -623 515 -589
+<< viali >>
+rect -257 487 -223 521
+rect -65 487 -31 521
+rect 127 487 161 521
+rect 319 487 353 521
+rect -401 -428 -367 428
+rect -305 -428 -271 428
+rect -209 -428 -175 428
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+rect -17 -428 17 428
+rect 79 -428 113 428
+rect 175 -428 209 428
+rect 271 -428 305 428
+rect 367 -428 401 428
+rect -353 -521 -319 -487
+rect -161 -521 -127 -487
+rect 31 -521 65 -487
+rect 223 -521 257 -487
+<< metal1 >>
+rect -269 521 -211 527
+rect -269 487 -257 521
+rect -223 487 -211 521
+rect -269 481 -211 487
+rect -77 521 -19 527
+rect -77 487 -65 521
+rect -31 487 -19 521
+rect -77 481 -19 487
+rect 115 521 173 527
+rect 115 487 127 521
+rect 161 487 173 521
+rect 115 481 173 487
+rect 307 521 365 527
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+rect 307 481 365 487
+rect -407 428 -361 440
+rect -407 -428 -401 428
+rect -367 -428 -361 428
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+rect -311 428 -265 440
+rect -311 -428 -305 428
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+rect -215 -440 -169 -428
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+rect -23 428 23 440
+rect -23 -428 -17 428
+rect 17 -428 23 428
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+rect 73 -428 79 428
+rect 113 -428 119 428
+rect 73 -440 119 -428
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+rect 169 -428 175 428
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+rect 265 428 311 440
+rect 265 -428 271 428
+rect 305 -428 311 428
+rect 265 -440 311 -428
+rect 361 428 407 440
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+rect 401 -428 407 428
+rect 361 -440 407 -428
+rect -365 -487 -307 -481
+rect -365 -521 -353 -487
+rect -319 -521 -307 -487
+rect -365 -527 -307 -521
+rect -173 -487 -115 -481
+rect -173 -521 -161 -487
+rect -127 -521 -115 -487
+rect -173 -527 -115 -521
+rect 19 -487 77 -481
+rect 19 -521 31 -487
+rect 65 -521 77 -487
+rect 19 -527 77 -521
+rect 211 -487 269 -481
+rect 211 -521 223 -487
+rect 257 -521 269 -487
+rect 211 -527 269 -521
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -498 -606 498 606
+string parameters w 4.4 l 0.15 m 1 nf 8 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_73WZNP.mag b/mag/sky130_fd_pr__pfet_01v8_73WZNP.mag
new file mode 100644
index 0000000..806762a
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_73WZNP.mag
@@ -0,0 +1,1315 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627115601
+<< error_p >>
+rect -1901 381 -1843 387
+rect -1709 381 -1651 387
+rect -1517 381 -1459 387
+rect -1325 381 -1267 387
+rect -1133 381 -1075 387
+rect -941 381 -883 387
+rect -749 381 -691 387
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+rect 19 381 77 387
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+rect 787 381 845 387
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+rect 1171 381 1229 387
+rect 1363 381 1421 387
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+rect -1901 347 -1889 381
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+rect -941 347 -929 381
+rect -749 347 -737 381
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+rect 1555 347 1567 381
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+rect 1939 347 1951 381
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+rect -365 341 -307 347
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+rect 19 341 77 347
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+rect 403 341 461 347
+rect 595 341 653 347
+rect 787 341 845 347
+rect 979 341 1037 347
+rect 1171 341 1229 347
+rect 1363 341 1421 347
+rect 1555 341 1613 347
+rect 1747 341 1805 347
+rect 1939 341 1997 347
+rect -1997 -347 -1939 -341
+rect -1805 -347 -1747 -341
+rect -1613 -347 -1555 -341
+rect -1421 -347 -1363 -341
+rect -1229 -347 -1171 -341
+rect -1037 -347 -979 -341
+rect -845 -347 -787 -341
+rect -653 -347 -595 -341
+rect -461 -347 -403 -341
+rect -269 -347 -211 -341
+rect -77 -347 -19 -341
+rect 115 -347 173 -341
+rect 307 -347 365 -341
+rect 499 -347 557 -341
+rect 691 -347 749 -341
+rect 883 -347 941 -341
+rect 1075 -347 1133 -341
+rect 1267 -347 1325 -341
+rect 1459 -347 1517 -341
+rect 1651 -347 1709 -341
+rect 1843 -347 1901 -341
+rect -1997 -381 -1985 -347
+rect -1805 -381 -1793 -347
+rect -1613 -381 -1601 -347
+rect -1421 -381 -1409 -347
+rect -1229 -381 -1217 -347
+rect -1037 -381 -1025 -347
+rect -845 -381 -833 -347
+rect -653 -381 -641 -347
+rect -461 -381 -449 -347
+rect -269 -381 -257 -347
+rect -77 -381 -65 -347
+rect 115 -381 127 -347
+rect 307 -381 319 -347
+rect 499 -381 511 -347
+rect 691 -381 703 -347
+rect 883 -381 895 -347
+rect 1075 -381 1087 -347
+rect 1267 -381 1279 -347
+rect 1459 -381 1471 -347
+rect 1651 -381 1663 -347
+rect 1843 -381 1855 -347
+rect -1997 -387 -1939 -381
+rect -1805 -387 -1747 -381
+rect -1613 -387 -1555 -381
+rect -1421 -387 -1363 -381
+rect -1229 -387 -1171 -381
+rect -1037 -387 -979 -381
+rect -845 -387 -787 -381
+rect -653 -387 -595 -381
+rect -461 -387 -403 -381
+rect -269 -387 -211 -381
+rect -77 -387 -19 -381
+rect 115 -387 173 -381
+rect 307 -387 365 -381
+rect 499 -387 557 -381
+rect 691 -387 749 -381
+rect 883 -387 941 -381
+rect 1075 -387 1133 -381
+rect 1267 -387 1325 -381
+rect 1459 -387 1517 -381
+rect 1651 -387 1709 -381
+rect 1843 -387 1901 -381
+<< nwell >>
+rect -2183 -519 2183 519
+<< pmos >>
+rect -1983 -300 -1953 300
+rect -1887 -300 -1857 300
+rect -1791 -300 -1761 300
+rect -1695 -300 -1665 300
+rect -1599 -300 -1569 300
+rect -1503 -300 -1473 300
+rect -1407 -300 -1377 300
+rect -1311 -300 -1281 300
+rect -1215 -300 -1185 300
+rect -1119 -300 -1089 300
+rect -1023 -300 -993 300
+rect -927 -300 -897 300
+rect -831 -300 -801 300
+rect -735 -300 -705 300
+rect -639 -300 -609 300
+rect -543 -300 -513 300
+rect -447 -300 -417 300
+rect -351 -300 -321 300
+rect -255 -300 -225 300
+rect -159 -300 -129 300
+rect -63 -300 -33 300
+rect 33 -300 63 300
+rect 129 -300 159 300
+rect 225 -300 255 300
+rect 321 -300 351 300
+rect 417 -300 447 300
+rect 513 -300 543 300
+rect 609 -300 639 300
+rect 705 -300 735 300
+rect 801 -300 831 300
+rect 897 -300 927 300
+rect 993 -300 1023 300
+rect 1089 -300 1119 300
+rect 1185 -300 1215 300
+rect 1281 -300 1311 300
+rect 1377 -300 1407 300
+rect 1473 -300 1503 300
+rect 1569 -300 1599 300
+rect 1665 -300 1695 300
+rect 1761 -300 1791 300
+rect 1857 -300 1887 300
+rect 1953 -300 1983 300
+<< pdiff >>
+rect -2045 288 -1983 300
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+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -2130 -466 2130 466
+string parameters w 3 l 0.15 m 1 nf 42 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_79SF4X.mag b/mag/sky130_fd_pr__pfet_01v8_79SF4X.mag
new file mode 100644
index 0000000..58b97f4
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_79SF4X.mag
@@ -0,0 +1,45 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627032624
+<< nwell >>
+rect -109 -104 109 104
+<< pmos >>
+rect -15 -42 15 42
+<< pdiff >>
+rect -73 30 -15 42
+rect -73 -30 -61 30
+rect -27 -30 -15 30
+rect -73 -42 -15 -30
+rect 15 30 73 42
+rect 15 -30 27 30
+rect 61 -30 73 30
+rect 15 -42 73 -30
+<< pdiffc >>
+rect -61 -30 -27 30
+rect 27 -30 61 30
+<< poly >>
+rect -15 42 15 68
+rect -15 -68 15 -42
+<< locali >>
+rect -61 30 -27 46
+rect -61 -46 -27 -30
+rect 27 30 61 46
+rect 27 -46 61 -30
+<< viali >>
+rect -61 -30 -27 30
+rect 27 -30 61 30
+<< metal1 >>
+rect -67 30 -21 42
+rect -67 -30 -61 30
+rect -27 -30 -21 30
+rect -67 -42 -21 -30
+rect 21 30 67 42
+rect 21 -30 27 30
+rect 61 -30 67 30
+rect 21 -42 67 -30
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string parameters w 0.42 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 0 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_BDWR5Q.mag b/mag/sky130_fd_pr__pfet_01v8_BDWR5Q.mag
new file mode 100644
index 0000000..4a9378d
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_BDWR5Q.mag
@@ -0,0 +1,1315 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626798771
+<< error_p >>
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+<< nwell >>
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+<< pmos >>
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+<< pdiff >>
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+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -2130 -466 2130 466
+string parameters w 3 l 0.15 m 1 nf 42 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_C3WZJM.mag b/mag/sky130_fd_pr__pfet_01v8_C3WZJM.mag
new file mode 100644
index 0000000..c97ae1e
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_C3WZJM.mag
@@ -0,0 +1,1315 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627116355
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+rect 1651 -387 1709 -381
+rect 1843 -347 1901 -341
+rect 1843 -381 1855 -347
+rect 1889 -381 1901 -347
+rect 1843 -387 1901 -381
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -2130 -466 2130 466
+string parameters w 3 l 0.15 m 1 nf 42 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_CC7KEW.mag b/mag/sky130_fd_pr__pfet_01v8_CC7KEW.mag
new file mode 100644
index 0000000..d21a015
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_CC7KEW.mag
@@ -0,0 +1,1294 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627668659
+<< error_p >>
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+rect 2033 -288 2045 288
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+<< pdiffc >>
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+rect -1649 -288 -1615 288
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+<< poly >>
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+rect -31 -381 -19 -347
+rect -77 -387 -19 -381
+rect 115 -347 173 -341
+rect 115 -381 127 -347
+rect 161 -381 173 -347
+rect 115 -387 173 -381
+rect 307 -347 365 -341
+rect 307 -381 319 -347
+rect 353 -381 365 -347
+rect 307 -387 365 -381
+rect 499 -347 557 -341
+rect 499 -381 511 -347
+rect 545 -381 557 -347
+rect 499 -387 557 -381
+rect 691 -347 749 -341
+rect 691 -381 703 -347
+rect 737 -381 749 -347
+rect 691 -387 749 -381
+rect 883 -347 941 -341
+rect 883 -381 895 -347
+rect 929 -381 941 -347
+rect 883 -387 941 -381
+rect 1075 -347 1133 -341
+rect 1075 -381 1087 -347
+rect 1121 -381 1133 -347
+rect 1075 -387 1133 -381
+rect 1267 -347 1325 -341
+rect 1267 -381 1279 -347
+rect 1313 -381 1325 -347
+rect 1267 -387 1325 -381
+rect 1459 -347 1517 -341
+rect 1459 -381 1471 -347
+rect 1505 -381 1517 -347
+rect 1459 -387 1517 -381
+rect 1651 -347 1709 -341
+rect 1651 -381 1663 -347
+rect 1697 -381 1709 -347
+rect 1651 -387 1709 -381
+rect 1843 -347 1901 -341
+rect 1843 -381 1855 -347
+rect 1889 -381 1901 -347
+rect 1843 -387 1901 -381
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string parameters w 3 l 0.15 m 1 nf 42 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_E6WEYA.mag b/mag/sky130_fd_pr__pfet_01v8_E6WEYA.mag
new file mode 100644
index 0000000..34eb962
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_E6WEYA.mag
@@ -0,0 +1,62 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627111729
+<< error_p >>
+rect -29 129 29 135
+rect -29 95 -17 129
+rect -29 89 29 95
+<< nwell >>
+rect -109 -182 109 148
+<< pmos >>
+rect -15 -120 15 48
+<< pdiff >>
+rect -73 36 -15 48
+rect -73 -108 -61 36
+rect -27 -108 -15 36
+rect -73 -120 -15 -108
+rect 15 36 73 48
+rect 15 -108 27 36
+rect 61 -108 73 36
+rect 15 -120 73 -108
+<< pdiffc >>
+rect -61 -108 -27 36
+rect 27 -108 61 36
+<< poly >>
+rect -33 129 33 145
+rect -33 95 -17 129
+rect 17 95 33 129
+rect -33 79 33 95
+rect -15 48 15 79
+rect -15 -146 15 -120
+<< polycont >>
+rect -17 95 17 129
+<< locali >>
+rect -33 95 -17 129
+rect 17 95 33 129
+rect -61 36 -27 52
+rect -61 -124 -27 -108
+rect 27 36 61 52
+rect 27 -124 61 -108
+<< viali >>
+rect -17 95 17 129
+rect -61 -108 -27 36
+rect 27 -108 61 36
+<< metal1 >>
+rect -29 129 29 135
+rect -29 95 -17 129
+rect 17 95 29 129
+rect -29 89 29 95
+rect -67 36 -21 48
+rect -67 -108 -61 36
+rect -27 -108 -21 36
+rect -67 -120 -21 -108
+rect 21 36 67 48
+rect 21 -108 27 36
+rect 61 -108 67 36
+rect 21 -120 67 -108
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string parameters w 0.84 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_EDWR5W.mag b/mag/sky130_fd_pr__pfet_01v8_EDWR5W.mag
new file mode 100644
index 0000000..6c3c2e6
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_EDWR5W.mag
@@ -0,0 +1,1315 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626798771
+<< error_p >>
+rect -1901 381 -1843 387
+rect -1709 381 -1651 387
+rect -1517 381 -1459 387
+rect -1325 381 -1267 387
+rect -1133 381 -1075 387
+rect -941 381 -883 387
+rect -749 381 -691 387
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+rect 19 381 77 387
+rect 211 381 269 387
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+rect 595 381 653 387
+rect 787 381 845 387
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+rect 691 -387 749 -381
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+rect 1075 -387 1133 -381
+rect 1267 -387 1325 -381
+rect 1459 -387 1517 -381
+rect 1651 -387 1709 -381
+rect 1843 -387 1901 -381
+<< nwell >>
+rect -2183 -519 2183 519
+<< pmos >>
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+rect -1791 -300 -1761 300
+rect -1695 -300 -1665 300
+rect -1599 -300 -1569 300
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+rect 225 -300 255 300
+rect 321 -300 351 300
+rect 417 -300 447 300
+rect 513 -300 543 300
+rect 609 -300 639 300
+rect 705 -300 735 300
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+rect 1185 -300 1215 300
+rect 1281 -300 1311 300
+rect 1377 -300 1407 300
+rect 1473 -300 1503 300
+rect 1569 -300 1599 300
+rect 1665 -300 1695 300
+rect 1761 -300 1791 300
+rect 1857 -300 1887 300
+rect 1953 -300 1983 300
+<< pdiff >>
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+rect -2045 -288 -2033 288
+rect -1999 -288 -1983 288
+rect -2045 -300 -1983 -288
+rect -1953 288 -1887 300
+rect -1953 -288 -1937 288
+rect -1903 -288 -1887 288
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+rect 1599 288 1665 300
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+rect 1649 -288 1665 288
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+rect 1937 -288 1953 288
+rect 1887 -300 1953 -288
+rect 1983 288 2045 300
+rect 1983 -288 1999 288
+rect 2033 -288 2045 288
+rect 1983 -300 2045 -288
+<< pdiffc >>
+rect -2033 -288 -1999 288
+rect -1937 -288 -1903 288
+rect -1841 -288 -1807 288
+rect -1745 -288 -1711 288
+rect -1649 -288 -1615 288
+rect -1553 -288 -1519 288
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+rect 79 -288 113 288
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+rect 367 -288 401 288
+rect 463 -288 497 288
+rect 559 -288 593 288
+rect 655 -288 689 288
+rect 751 -288 785 288
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+rect 943 -288 977 288
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+rect 1135 -288 1169 288
+rect 1231 -288 1265 288
+rect 1327 -288 1361 288
+rect 1423 -288 1457 288
+rect 1519 -288 1553 288
+rect 1615 -288 1649 288
+rect 1711 -288 1745 288
+rect 1807 -288 1841 288
+rect 1903 -288 1937 288
+rect 1999 -288 2033 288
+<< nsubdiff >>
+rect -2147 449 -2051 483
+rect 2051 449 2147 483
+rect -2147 387 -2113 449
+rect 2113 387 2147 449
+rect -2147 -449 -2113 -387
+rect 2113 -449 2147 -387
+rect -2147 -483 -2051 -449
+rect 2051 -483 2147 -449
+<< nsubdiffcont >>
+rect -2051 449 2051 483
+rect -2147 -387 -2113 387
+rect 2113 -387 2147 387
+rect -2051 -483 2051 -449
+<< poly >>
+rect -1905 381 -1839 397
+rect -1905 347 -1889 381
+rect -1855 347 -1839 381
+rect -1905 331 -1839 347
+rect -1713 381 -1647 397
+rect -1713 347 -1697 381
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+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -2130 -466 2130 466
+string parameters w 3 l 0.15 m 1 nf 42 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_EMKQNQ.mag b/mag/sky130_fd_pr__pfet_01v8_EMKQNQ.mag
new file mode 100644
index 0000000..3712b58
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_EMKQNQ.mag
@@ -0,0 +1,62 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627111729
+<< error_p >>
+rect -29 -95 29 -89
+rect -29 -129 -17 -95
+rect -29 -135 29 -129
+<< nwell >>
+rect -109 -148 109 182
+<< pmos >>
+rect -15 -48 15 120
+<< pdiff >>
+rect -73 108 -15 120
+rect -73 -36 -61 108
+rect -27 -36 -15 108
+rect -73 -48 -15 -36
+rect 15 108 73 120
+rect 15 -36 27 108
+rect 61 -36 73 108
+rect 15 -48 73 -36
+<< pdiffc >>
+rect -61 -36 -27 108
+rect 27 -36 61 108
+<< poly >>
+rect -15 120 15 146
+rect -15 -79 15 -48
+rect -33 -95 33 -79
+rect -33 -129 -17 -95
+rect 17 -129 33 -95
+rect -33 -145 33 -129
+<< polycont >>
+rect -17 -129 17 -95
+<< locali >>
+rect -61 108 -27 124
+rect -61 -52 -27 -36
+rect 27 108 61 124
+rect 27 -52 61 -36
+rect -33 -129 -17 -95
+rect 17 -129 33 -95
+<< viali >>
+rect -61 -36 -27 108
+rect 27 -36 61 108
+rect -17 -129 17 -95
+<< metal1 >>
+rect -67 108 -21 120
+rect -67 -36 -61 108
+rect -27 -36 -21 108
+rect -67 -48 -21 -36
+rect 21 108 67 120
+rect 21 -36 27 108
+rect 61 -36 67 108
+rect 21 -48 67 -36
+rect -29 -95 29 -89
+rect -29 -129 -17 -95
+rect 17 -129 29 -95
+rect -29 -135 29 -129
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string parameters w 0.84 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_G3WZJM.mag b/mag/sky130_fd_pr__pfet_01v8_G3WZJM.mag
new file mode 100644
index 0000000..178041e
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_G3WZJM.mag
@@ -0,0 +1,1312 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627118661
+<< error_p >>
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+<< pmos >>
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+<< nsubdiff >>
+rect -2147 449 2147 483
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+rect 2113 387 2147 449
+rect -2147 -449 -2113 -387
+rect 2113 -449 2147 -387
+rect -2147 -483 -2051 -449
+rect 2051 -483 2147 -449
+<< nsubdiffcont >>
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+rect -2051 -483 2051 -449
+<< poly >>
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+rect -1905 347 -1889 381
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+rect 1843 -387 1901 -381
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -2130 -466 2130 466
+string parameters w 3 l 0.15 m 1 nf 42 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_H8Y43H.mag b/mag/sky130_fd_pr__pfet_01v8_H8Y43H.mag
new file mode 100644
index 0000000..b30c9dd
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_H8Y43H.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627838634
+<< error_p >>
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+rect -29 -351 29 -345
+<< nwell >>
+rect -211 -484 211 484
+<< pmos >>
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+<< pdiff >>
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+rect -27 -252 -15 324
+rect -73 -264 -15 -252
+rect 15 324 73 336
+rect 15 -252 27 324
+rect 61 -252 73 324
+rect 15 -264 73 -252
+<< pdiffc >>
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+rect 27 -252 61 324
+<< nsubdiff >>
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+rect 141 351 175 414
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+rect 79 -448 175 -414
+<< nsubdiffcont >>
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+<< poly >>
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+<< locali >>
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+rect 141 351 175 414
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+rect 27 324 61 340
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+<< viali >>
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+<< metal1 >>
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+rect -67 -252 -61 324
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+rect -29 -311 29 -305
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+rect 17 -345 29 -311
+rect -29 -351 29 -345
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -431 158 431
+string parameters w 3 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_KPE92J.mag b/mag/sky130_fd_pr__pfet_01v8_KPE92J.mag
new file mode 100644
index 0000000..c89e92e
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_KPE92J.mag
@@ -0,0 +1,1555 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626793425
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+rect 1546 -641 1558 -607
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+rect 1546 -647 1604 -641
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -1947 -726 1947 726
+string parameters w 2.21 l 0.15 m 2 nf 18 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 0 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_KPEH9L.mag b/mag/sky130_fd_pr__pfet_01v8_KPEH9L.mag
new file mode 100644
index 0000000..69b4554
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_KPEH9L.mag
@@ -0,0 +1,1147 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626793425
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+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -978 -726 978 726
+string parameters w 2.21 l 0.15 m 2 nf 18 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_KPEHM7.mag b/mag/sky130_fd_pr__pfet_01v8_KPEHM7.mag
new file mode 100644
index 0000000..807d862
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_KPEHM7.mag
@@ -0,0 +1,1147 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626793425
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+rect 499 -647 557 -641
+rect 691 -607 749 -601
+rect 691 -641 703 -607
+rect 737 -641 749 -607
+rect 691 -647 749 -641
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -978 -726 978 726
+string parameters w 2.21 l 0.15 m 2 nf 18 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_MJR9GH.mag b/mag/sky130_fd_pr__pfet_01v8_MJR9GH.mag
new file mode 100644
index 0000000..129c16c
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_MJR9GH.mag
@@ -0,0 +1,235 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626782926
+<< error_p >>
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+<< nwell >>
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+<< pmos >>
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+rect 225 -500 255 500
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+rect 175 -488 209 488
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+<< nsubdiff >>
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+rect 115 -547 173 -541
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+rect 161 -581 173 -547
+rect 115 -587 173 -581
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -402 -666 402 666
+string parameters w 5 l 0.15 m 1 nf 6 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_NDGGM9.mag b/mag/sky130_fd_pr__pfet_01v8_NDGGM9.mag
new file mode 100644
index 0000000..bbdf7ad
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_NDGGM9.mag
@@ -0,0 +1,1147 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626793425
+<< error_p >>
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+rect 831 -130 893 -118
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+<< pdiffc >>
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+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -978 -726 978 726
+string parameters w 2.21 l 0.15 m 2 nf 18 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_QD2RPB.mag b/mag/sky130_fd_pr__pfet_01v8_QD2RPB.mag
new file mode 100644
index 0000000..eb29b2a
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_QD2RPB.mag
@@ -0,0 +1,1327 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626798771
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+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -1122 -884 1122 884
+string parameters w 3 l 0.15 m 2 nf 21 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_QDW7KD.mag b/mag/sky130_fd_pr__pfet_01v8_QDW7KD.mag
new file mode 100644
index 0000000..f6c1fa0
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_QDW7KD.mag
@@ -0,0 +1,1555 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626798771
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+rect 73 -6140 79 -5564
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+rect 19 -6239 77 -6233
+rect 19 -6307 77 -6301
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+rect 19 -7911 77 -7905
+rect 19 -7979 77 -7973
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+rect -119 -8648 -113 -8072
+rect -79 -8648 -73 -8072
+rect -119 -8660 -73 -8648
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+rect -77 -8707 -19 -8701
+rect -77 -8741 -65 -8707
+rect -31 -8741 -19 -8707
+rect -77 -8747 -19 -8741
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -8826 210 8826
+string parameters w 3 l 0.15 m 21 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_QE3MXG.mag b/mag/sky130_fd_pr__pfet_01v8_QE3MXG.mag
new file mode 100644
index 0000000..bd23861
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_QE3MXG.mag
@@ -0,0 +1,295 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628066341
+<< error_p >>
+rect -269 481 -211 487
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+rect -269 447 -257 481
+rect -77 447 -65 481
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+rect -77 441 -19 447
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+rect 19 -487 77 -481
+rect 211 -487 269 -481
+<< nwell >>
+rect -551 -619 551 619
+<< pmos >>
+rect -351 -400 -321 400
+rect -255 -400 -225 400
+rect -159 -400 -129 400
+rect -63 -400 -33 400
+rect 33 -400 63 400
+rect 129 -400 159 400
+rect 225 -400 255 400
+rect 321 -400 351 400
+<< pdiff >>
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+rect -413 -400 -351 -388
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+rect 401 -388 413 388
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+<< nsubdiff >>
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+rect -515 -549 -481 -487
+rect 481 -549 515 -487
+rect -515 -583 -419 -549
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+<< nsubdiffcont >>
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+rect -419 -583 419 -549
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+rect 207 -447 273 -431
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+rect 319 447 353 481
+rect -353 -481 -319 -447
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+rect 31 -481 65 -447
+rect 223 -481 257 -447
+<< locali >>
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+rect -515 487 -481 549
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+rect -273 447 -257 481
+rect -223 447 -207 481
+rect -81 447 -65 481
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+rect -515 -549 -481 -487
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+rect -515 -583 -419 -549
+rect 419 -583 515 -549
+<< viali >>
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+rect -209 -388 -175 388
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+rect 367 -388 401 388
+rect -353 -481 -319 -447
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+rect 31 -481 65 -447
+rect 223 -481 257 -447
+<< metal1 >>
+rect -269 481 -211 487
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+rect -269 441 -211 447
+rect -77 481 -19 487
+rect -77 447 -65 481
+rect -31 447 -19 481
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+rect 115 481 173 487
+rect 115 447 127 481
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+rect 307 481 365 487
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+rect -407 388 -361 400
+rect -407 -388 -401 388
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+rect 265 -388 271 388
+rect 305 -388 311 388
+rect 265 -400 311 -388
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+rect 361 -388 367 388
+rect 401 -388 407 388
+rect 361 -400 407 -388
+rect -365 -447 -307 -441
+rect -365 -481 -353 -447
+rect -319 -481 -307 -447
+rect -365 -487 -307 -481
+rect -173 -447 -115 -441
+rect -173 -481 -161 -447
+rect -127 -481 -115 -447
+rect -173 -487 -115 -481
+rect 19 -447 77 -441
+rect 19 -481 31 -447
+rect 65 -481 77 -447
+rect 19 -487 77 -481
+rect 211 -447 269 -441
+rect 211 -481 223 -447
+rect 257 -481 269 -447
+rect 211 -487 269 -481
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -498 -566 498 566
+string parameters w 4 l 0.15 m 1 nf 8 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_R23ZJ6.mag b/mag/sky130_fd_pr__pfet_01v8_R23ZJ6.mag
new file mode 100644
index 0000000..862fae4
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_R23ZJ6.mag
@@ -0,0 +1,1027 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628056522
+<< error_p >>
+rect -749 599 -691 605
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+rect -749 559 -691 565
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+rect -653 -71 -641 -37
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+rect -269 -71 -257 -37
+rect -77 -71 -65 -37
+rect 115 -71 127 -37
+rect 307 -71 319 -37
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+rect 691 -71 703 -37
+rect -653 -77 -595 -71
+rect -461 -77 -403 -71
+rect -269 -77 -211 -71
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+rect 691 -77 749 -71
+rect -749 -565 -691 -559
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+rect 595 -599 607 -565
+rect -749 -605 -691 -599
+rect -557 -605 -499 -599
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+rect 595 -605 653 -599
+<< nwell >>
+rect -935 -737 935 737
+<< pmos >>
+rect -735 118 -705 518
+rect -639 118 -609 518
+rect -543 118 -513 518
+rect -447 118 -417 518
+rect -351 118 -321 518
+rect -255 118 -225 518
+rect -159 118 -129 518
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+rect -735 -518 -705 -118
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+rect 33 -518 63 -118
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+rect 225 -518 255 -118
+rect 321 -518 351 -118
+rect 417 -518 447 -118
+rect 513 -518 543 -118
+rect 609 -518 639 -118
+rect 705 -518 735 -118
+<< pdiff >>
+rect -797 506 -735 518
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+rect -705 506 -639 518
+rect -705 130 -689 506
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+rect -797 -130 -735 -118
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+rect 639 -130 705 -118
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+rect 689 -506 705 -130
+rect 639 -518 705 -506
+rect 735 -130 797 -118
+rect 735 -506 751 -130
+rect 785 -506 797 -130
+rect 735 -518 797 -506
+<< pdiffc >>
+rect -785 130 -751 506
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+rect 463 -506 497 -130
+rect 559 -506 593 -130
+rect 655 -506 689 -130
+rect 751 -506 785 -130
+<< nsubdiff >>
+rect -899 667 -803 701
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+rect -899 605 -865 667
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+rect -899 -667 -865 -605
+rect 865 -667 899 -605
+rect -899 -701 -803 -667
+rect 803 -701 899 -667
+<< nsubdiffcont >>
+rect -803 667 803 701
+rect -899 -605 -865 605
+rect 865 -605 899 605
+rect -803 -701 803 -667
+<< poly >>
+rect -753 599 -687 615
+rect -753 565 -737 599
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+rect -561 565 -545 599
+rect -511 565 -495 599
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+rect 399 599 465 615
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+rect 591 599 657 615
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+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -882 -684 882 684
+string parameters w 2 l 0.15 m 2 nf 16 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_SGAV3S.mag b/mag/sky130_fd_pr__pfet_01v8_SGAV3S.mag
new file mode 100644
index 0000000..f166fdf
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_SGAV3S.mag
@@ -0,0 +1,1027 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628060682
+<< error_p >>
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+rect 545 -71 557 -37
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+rect 691 -37 749 -31
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+rect 737 -71 749 -37
+rect 691 -77 749 -71
+rect -791 -130 -745 -118
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+rect -311 -130 -265 -118
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+rect -271 -456 -265 -130
+rect -311 -468 -265 -456
+rect -215 -130 -169 -118
+rect -215 -456 -209 -130
+rect -175 -456 -169 -130
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+rect -119 -130 -73 -118
+rect -119 -456 -113 -130
+rect -79 -456 -73 -130
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+rect 73 -130 119 -118
+rect 73 -456 79 -130
+rect 113 -456 119 -130
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+rect 169 -130 215 -118
+rect 169 -456 175 -130
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+rect 265 -130 311 -118
+rect 265 -456 271 -130
+rect 305 -456 311 -130
+rect 265 -468 311 -456
+rect 361 -130 407 -118
+rect 361 -456 367 -130
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+rect 457 -456 463 -130
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+rect 553 -456 559 -130
+rect 593 -456 599 -130
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+rect 649 -130 695 -118
+rect 649 -456 655 -130
+rect 689 -456 695 -130
+rect 649 -468 695 -456
+rect 745 -130 791 -118
+rect 745 -456 751 -130
+rect 785 -456 791 -130
+rect 745 -468 791 -456
+rect -749 -515 -691 -509
+rect -749 -549 -737 -515
+rect -703 -549 -691 -515
+rect -749 -555 -691 -549
+rect -557 -515 -499 -509
+rect -557 -549 -545 -515
+rect -511 -549 -499 -515
+rect -557 -555 -499 -549
+rect -365 -515 -307 -509
+rect -365 -549 -353 -515
+rect -319 -549 -307 -515
+rect -365 -555 -307 -549
+rect -173 -515 -115 -509
+rect -173 -549 -161 -515
+rect -127 -549 -115 -515
+rect -173 -555 -115 -549
+rect 19 -515 77 -509
+rect 19 -549 31 -515
+rect 65 -549 77 -515
+rect 19 -555 77 -549
+rect 211 -515 269 -509
+rect 211 -549 223 -515
+rect 257 -549 269 -515
+rect 211 -555 269 -549
+rect 403 -515 461 -509
+rect 403 -549 415 -515
+rect 449 -549 461 -515
+rect 403 -555 461 -549
+rect 595 -515 653 -509
+rect 595 -549 607 -515
+rect 641 -549 653 -515
+rect 595 -555 653 -549
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -882 -634 882 634
+string parameters w 1.75 l 0.15 m 2 nf 16 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_UCG7GH.mag b/mag/sky130_fd_pr__pfet_01v8_UCG7GH.mag
new file mode 100644
index 0000000..aead263
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_UCG7GH.mag
@@ -0,0 +1,205 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626782926
+<< error_p >>
+rect -125 681 -67 687
+rect 67 681 125 687
+rect -125 647 -113 681
+rect 67 647 79 681
+rect -125 641 -67 647
+rect 67 641 125 647
+rect -221 -647 -163 -641
+rect -29 -647 29 -641
+rect 163 -647 221 -641
+rect -221 -681 -209 -647
+rect -29 -681 -17 -647
+rect 163 -681 175 -647
+rect -221 -687 -163 -681
+rect -29 -687 29 -681
+rect 163 -687 221 -681
+<< nwell >>
+rect -407 -819 407 819
+<< pmos >>
+rect -207 -600 -177 600
+rect -111 -600 -81 600
+rect -15 -600 15 600
+rect 81 -600 111 600
+rect 177 -600 207 600
+<< pdiff >>
+rect -269 588 -207 600
+rect -269 -588 -257 588
+rect -223 -588 -207 588
+rect -269 -600 -207 -588
+rect -177 588 -111 600
+rect -177 -588 -161 588
+rect -127 -588 -111 588
+rect -177 -600 -111 -588
+rect -81 588 -15 600
+rect -81 -588 -65 588
+rect -31 -588 -15 588
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+rect 15 588 81 600
+rect 15 -588 31 588
+rect 65 -588 81 588
+rect 15 -600 81 -588
+rect 111 588 177 600
+rect 111 -588 127 588
+rect 161 -588 177 588
+rect 111 -600 177 -588
+rect 207 588 269 600
+rect 207 -588 223 588
+rect 257 -588 269 588
+rect 207 -600 269 -588
+<< pdiffc >>
+rect -257 -588 -223 588
+rect -161 -588 -127 588
+rect -65 -588 -31 588
+rect 31 -588 65 588
+rect 127 -588 161 588
+rect 223 -588 257 588
+<< nsubdiff >>
+rect -371 749 -275 783
+rect 275 749 371 783
+rect -371 687 -337 749
+rect 337 687 371 749
+rect -371 -749 -337 -687
+rect 337 -749 371 -687
+rect -371 -783 -275 -749
+rect 275 -783 371 -749
+<< nsubdiffcont >>
+rect -275 749 275 783
+rect -371 -687 -337 687
+rect 337 -687 371 687
+rect -275 -783 275 -749
+<< poly >>
+rect -129 681 -63 697
+rect -129 647 -113 681
+rect -79 647 -63 681
+rect -129 631 -63 647
+rect 63 681 129 697
+rect 63 647 79 681
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+rect -207 600 -177 626
+rect -111 600 -81 631
+rect -15 600 15 626
+rect 81 600 111 631
+rect 177 600 207 626
+rect -207 -631 -177 -600
+rect -111 -626 -81 -600
+rect -15 -631 15 -600
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+rect -225 -647 -159 -631
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+rect 17 -681 33 -647
+rect -33 -697 33 -681
+rect 159 -647 225 -631
+rect 159 -681 175 -647
+rect 209 -681 225 -647
+rect 159 -697 225 -681
+<< polycont >>
+rect -113 647 -79 681
+rect 79 647 113 681
+rect -209 -681 -175 -647
+rect -17 -681 17 -647
+rect 175 -681 209 -647
+<< locali >>
+rect -371 749 -275 783
+rect 275 749 371 783
+rect -371 687 -337 749
+rect 337 687 371 749
+rect -129 647 -113 681
+rect -79 647 -63 681
+rect 63 647 79 681
+rect 113 647 129 681
+rect -257 588 -223 604
+rect -257 -604 -223 -588
+rect -161 588 -127 604
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+rect -225 -681 -209 -647
+rect -175 -681 -159 -647
+rect -33 -681 -17 -647
+rect 17 -681 33 -647
+rect 159 -681 175 -647
+rect 209 -681 225 -647
+rect -371 -749 -337 -687
+rect 337 -749 371 -687
+rect -371 -783 -275 -749
+rect 275 -783 371 -749
+<< viali >>
+rect -113 647 -79 681
+rect 79 647 113 681
+rect -257 -588 -223 588
+rect -161 -588 -127 588
+rect -65 -588 -31 588
+rect 31 -588 65 588
+rect 127 -588 161 588
+rect 223 -588 257 588
+rect -209 -681 -175 -647
+rect -17 -681 17 -647
+rect 175 -681 209 -647
+<< metal1 >>
+rect -125 681 -67 687
+rect -125 647 -113 681
+rect -79 647 -67 681
+rect -125 641 -67 647
+rect 67 681 125 687
+rect 67 647 79 681
+rect 113 647 125 681
+rect 67 641 125 647
+rect -263 588 -217 600
+rect -263 -588 -257 588
+rect -223 -588 -217 588
+rect -263 -600 -217 -588
+rect -167 588 -121 600
+rect -167 -588 -161 588
+rect -127 -588 -121 588
+rect -167 -600 -121 -588
+rect -71 588 -25 600
+rect -71 -588 -65 588
+rect -31 -588 -25 588
+rect -71 -600 -25 -588
+rect 25 588 71 600
+rect 25 -588 31 588
+rect 65 -588 71 588
+rect 25 -600 71 -588
+rect 121 588 167 600
+rect 121 -588 127 588
+rect 161 -588 167 588
+rect 121 -600 167 -588
+rect 217 588 263 600
+rect 217 -588 223 588
+rect 257 -588 263 588
+rect 217 -600 263 -588
+rect -221 -647 -163 -641
+rect -221 -681 -209 -647
+rect -175 -681 -163 -647
+rect -221 -687 -163 -681
+rect -29 -647 29 -641
+rect -29 -681 -17 -647
+rect 17 -681 29 -647
+rect -29 -687 29 -681
+rect 163 -647 221 -641
+rect 163 -681 175 -647
+rect 209 -681 221 -647
+rect 163 -687 221 -681
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -354 -766 354 766
+string parameters w 6 l 0.15 m 1 nf 5 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_UJR9GH.mag b/mag/sky130_fd_pr__pfet_01v8_UJR9GH.mag
new file mode 100644
index 0000000..876bbb0
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_UJR9GH.mag
@@ -0,0 +1,235 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626782926
+<< error_p >>
+rect -173 581 -115 587
+rect 19 581 77 587
+rect 211 581 269 587
+rect -173 547 -161 581
+rect 19 547 31 581
+rect 211 547 223 581
+rect -173 541 -115 547
+rect 19 541 77 547
+rect 211 541 269 547
+rect -269 -547 -211 -541
+rect -77 -547 -19 -541
+rect 115 -547 173 -541
+rect -269 -581 -257 -547
+rect -77 -581 -65 -547
+rect 115 -581 127 -547
+rect -269 -587 -211 -581
+rect -77 -587 -19 -581
+rect 115 -587 173 -581
+<< nwell >>
+rect -455 -719 455 719
+<< pmos >>
+rect -255 -500 -225 500
+rect -159 -500 -129 500
+rect -63 -500 -33 500
+rect 33 -500 63 500
+rect 129 -500 159 500
+rect 225 -500 255 500
+<< pdiff >>
+rect -317 488 -255 500
+rect -317 -488 -305 488
+rect -271 -488 -255 488
+rect -317 -500 -255 -488
+rect -225 488 -159 500
+rect -225 -488 -209 488
+rect -175 -488 -159 488
+rect -225 -500 -159 -488
+rect -129 488 -63 500
+rect -129 -488 -113 488
+rect -79 -488 -63 488
+rect -129 -500 -63 -488
+rect -33 488 33 500
+rect -33 -488 -17 488
+rect 17 -488 33 488
+rect -33 -500 33 -488
+rect 63 488 129 500
+rect 63 -488 79 488
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+rect 63 -500 129 -488
+rect 159 488 225 500
+rect 159 -488 175 488
+rect 209 -488 225 488
+rect 159 -500 225 -488
+rect 255 488 317 500
+rect 255 -488 271 488
+rect 305 -488 317 488
+rect 255 -500 317 -488
+<< pdiffc >>
+rect -305 -488 -271 488
+rect -209 -488 -175 488
+rect -113 -488 -79 488
+rect -17 -488 17 488
+rect 79 -488 113 488
+rect 175 -488 209 488
+rect 271 -488 305 488
+<< nsubdiff >>
+rect -419 649 -323 683
+rect 323 649 419 683
+rect -419 587 -385 649
+rect 385 587 419 649
+rect -419 -649 -385 -587
+rect 385 -649 419 -587
+rect -419 -683 -323 -649
+rect 323 -683 419 -649
+<< nsubdiffcont >>
+rect -323 649 323 683
+rect -419 -587 -385 587
+rect 385 -587 419 587
+rect -323 -683 323 -649
+<< poly >>
+rect -177 581 -111 597
+rect -177 547 -161 581
+rect -127 547 -111 581
+rect -177 531 -111 547
+rect 15 581 81 597
+rect 15 547 31 581
+rect 65 547 81 581
+rect 15 531 81 547
+rect 207 581 273 597
+rect 207 547 223 581
+rect 257 547 273 581
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+rect -255 500 -225 526
+rect -159 500 -129 531
+rect -63 500 -33 526
+rect 33 500 63 531
+rect 129 500 159 526
+rect 225 500 255 531
+rect -255 -531 -225 -500
+rect -159 -526 -129 -500
+rect -63 -531 -33 -500
+rect 33 -526 63 -500
+rect 129 -531 159 -500
+rect 225 -526 255 -500
+rect -273 -547 -207 -531
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+rect -273 -597 -207 -581
+rect -81 -547 -15 -531
+rect -81 -581 -65 -547
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+rect -81 -597 -15 -581
+rect 111 -547 177 -531
+rect 111 -581 127 -547
+rect 161 -581 177 -547
+rect 111 -597 177 -581
+<< polycont >>
+rect -161 547 -127 581
+rect 31 547 65 581
+rect 223 547 257 581
+rect -257 -581 -223 -547
+rect -65 -581 -31 -547
+rect 127 -581 161 -547
+<< locali >>
+rect -419 649 -323 683
+rect 323 649 419 683
+rect -419 587 -385 649
+rect 385 587 419 649
+rect -177 547 -161 581
+rect -127 547 -111 581
+rect 15 547 31 581
+rect 65 547 81 581
+rect 207 547 223 581
+rect 257 547 273 581
+rect -305 488 -271 504
+rect -305 -504 -271 -488
+rect -209 488 -175 504
+rect -209 -504 -175 -488
+rect -113 488 -79 504
+rect -113 -504 -79 -488
+rect -17 488 17 504
+rect -17 -504 17 -488
+rect 79 488 113 504
+rect 79 -504 113 -488
+rect 175 488 209 504
+rect 175 -504 209 -488
+rect 271 488 305 504
+rect 271 -504 305 -488
+rect -273 -581 -257 -547
+rect -223 -581 -207 -547
+rect -81 -581 -65 -547
+rect -31 -581 -15 -547
+rect 111 -581 127 -547
+rect 161 -581 177 -547
+rect -419 -649 -385 -587
+rect 385 -649 419 -587
+rect -419 -683 -323 -649
+rect 323 -683 419 -649
+<< viali >>
+rect -161 547 -127 581
+rect 31 547 65 581
+rect 223 547 257 581
+rect -305 -488 -271 488
+rect -209 -488 -175 488
+rect -113 -488 -79 488
+rect -17 -488 17 488
+rect 79 -488 113 488
+rect 175 -488 209 488
+rect 271 -488 305 488
+rect -257 -581 -223 -547
+rect -65 -581 -31 -547
+rect 127 -581 161 -547
+<< metal1 >>
+rect -173 581 -115 587
+rect -173 547 -161 581
+rect -127 547 -115 581
+rect -173 541 -115 547
+rect 19 581 77 587
+rect 19 547 31 581
+rect 65 547 77 581
+rect 19 541 77 547
+rect 211 581 269 587
+rect 211 547 223 581
+rect 257 547 269 581
+rect 211 541 269 547
+rect -311 488 -265 500
+rect -311 -488 -305 488
+rect -271 -488 -265 488
+rect -311 -500 -265 -488
+rect -215 488 -169 500
+rect -215 -488 -209 488
+rect -175 -488 -169 488
+rect -215 -500 -169 -488
+rect -119 488 -73 500
+rect -119 -488 -113 488
+rect -79 -488 -73 488
+rect -119 -500 -73 -488
+rect -23 488 23 500
+rect -23 -488 -17 488
+rect 17 -488 23 488
+rect -23 -500 23 -488
+rect 73 488 119 500
+rect 73 -488 79 488
+rect 113 -488 119 488
+rect 73 -500 119 -488
+rect 169 488 215 500
+rect 169 -488 175 488
+rect 209 -488 215 488
+rect 169 -500 215 -488
+rect 265 488 311 500
+rect 265 -488 271 488
+rect 305 -488 311 488
+rect 265 -500 311 -488
+rect -269 -547 -211 -541
+rect -269 -581 -257 -547
+rect -223 -581 -211 -547
+rect -269 -587 -211 -581
+rect -77 -547 -19 -541
+rect -77 -581 -65 -547
+rect -31 -581 -19 -547
+rect -77 -587 -19 -581
+rect 115 -547 173 -541
+rect 115 -581 127 -547
+rect 161 -581 173 -547
+rect 115 -587 173 -581
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -402 -666 402 666
+string parameters w 5 l 0.15 m 1 nf 6 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_VNEHM9.mag b/mag/sky130_fd_pr__pfet_01v8_VNEHM9.mag
new file mode 100644
index 0000000..02bedb6
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_VNEHM9.mag
@@ -0,0 +1,1147 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627668659
+<< error_p >>
+rect -845 641 -787 647
+rect -653 641 -595 647
+rect -461 641 -403 647
+rect -269 641 -211 647
+rect -77 641 -19 647
+rect 115 641 173 647
+rect 307 641 365 647
+rect 499 641 557 647
+rect 691 641 749 647
+rect -845 607 -833 641
+rect -653 607 -641 641
+rect -461 607 -449 641
+rect -269 607 -257 641
+rect -77 607 -65 641
+rect 115 607 127 641
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+rect 499 607 511 641
+rect 691 607 703 641
+rect -845 601 -787 607
+rect -653 601 -595 607
+rect -461 601 -403 607
+rect -269 601 -211 607
+rect -77 601 -19 607
+rect 115 601 173 607
+rect 307 601 365 607
+rect 499 601 557 607
+rect 691 601 749 607
+rect -749 71 -691 77
+rect -557 71 -499 77
+rect -365 71 -307 77
+rect -173 71 -115 77
+rect 19 71 77 77
+rect 211 71 269 77
+rect 403 71 461 77
+rect 595 71 653 77
+rect 787 71 845 77
+rect -749 37 -737 71
+rect -557 37 -545 71
+rect -365 37 -353 71
+rect -173 37 -161 71
+rect 19 37 31 71
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+rect 787 37 799 71
+rect -749 31 -691 37
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+rect 19 31 77 37
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+rect 403 31 461 37
+rect 595 31 653 37
+rect 787 31 845 37
+rect -749 -37 -691 -31
+rect -557 -37 -499 -31
+rect -365 -37 -307 -31
+rect -173 -37 -115 -31
+rect 19 -37 77 -31
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+rect 403 -37 461 -31
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+rect 787 -37 845 -31
+rect -749 -71 -737 -37
+rect -557 -71 -545 -37
+rect -365 -71 -353 -37
+rect -173 -71 -161 -37
+rect 19 -71 31 -37
+rect 211 -71 223 -37
+rect 403 -71 415 -37
+rect 595 -71 607 -37
+rect 787 -71 799 -37
+rect -749 -77 -691 -71
+rect -557 -77 -499 -71
+rect -365 -77 -307 -71
+rect -173 -77 -115 -71
+rect 19 -77 77 -71
+rect 211 -77 269 -71
+rect 403 -77 461 -71
+rect 595 -77 653 -71
+rect 787 -77 845 -71
+rect -845 -607 -787 -601
+rect -653 -607 -595 -601
+rect -461 -607 -403 -601
+rect -269 -607 -211 -601
+rect -77 -607 -19 -601
+rect 115 -607 173 -601
+rect 307 -607 365 -601
+rect 499 -607 557 -601
+rect 691 -607 749 -601
+rect -845 -641 -833 -607
+rect -653 -641 -641 -607
+rect -461 -641 -449 -607
+rect -269 -641 -257 -607
+rect -77 -641 -65 -607
+rect 115 -641 127 -607
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+rect 499 -641 511 -607
+rect 691 -641 703 -607
+rect -845 -647 -787 -641
+rect -653 -647 -595 -641
+rect -461 -647 -403 -641
+rect -269 -647 -211 -641
+rect -77 -647 -19 -641
+rect 115 -647 173 -641
+rect 307 -647 365 -641
+rect 499 -647 557 -641
+rect 691 -647 749 -641
+<< nwell >>
+rect -1031 -779 1031 779
+<< pmos >>
+rect -831 118 -801 560
+rect -735 118 -705 560
+rect -639 118 -609 560
+rect -543 118 -513 560
+rect -447 118 -417 560
+rect -351 118 -321 560
+rect -255 118 -225 560
+rect -159 118 -129 560
+rect -63 118 -33 560
+rect 33 118 63 560
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+rect 225 118 255 560
+rect 321 118 351 560
+rect 417 118 447 560
+rect 513 118 543 560
+rect 609 118 639 560
+rect 705 118 735 560
+rect 801 118 831 560
+rect -831 -560 -801 -118
+rect -735 -560 -705 -118
+rect -639 -560 -609 -118
+rect -543 -560 -513 -118
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+rect -31 -641 -19 -607
+rect -77 -647 -19 -641
+rect 115 -607 173 -601
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+rect 307 -607 365 -601
+rect 307 -641 319 -607
+rect 353 -641 365 -607
+rect 307 -647 365 -641
+rect 499 -607 557 -601
+rect 499 -641 511 -607
+rect 545 -641 557 -607
+rect 499 -647 557 -641
+rect 691 -607 749 -601
+rect 691 -641 703 -607
+rect 737 -641 749 -607
+rect 691 -647 749 -641
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -978 -726 978 726
+string parameters w 2.21 l 0.15 m 2 nf 18 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_XJMZDL.mag b/mag/sky130_fd_pr__pfet_01v8_XJMZDL.mag
new file mode 100644
index 0000000..a3d1505
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_XJMZDL.mag
@@ -0,0 +1,385 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626782926
+<< error_p >>
+rect -29 3671 29 3677
+rect -29 3637 -17 3671
+rect -29 3631 29 3637
+rect -29 2543 29 2549
+rect -29 2509 -17 2543
+rect -29 2503 29 2509
+rect -29 2435 29 2441
+rect -29 2401 -17 2435
+rect -29 2395 29 2401
+rect -29 1307 29 1313
+rect -29 1273 -17 1307
+rect -29 1267 29 1273
+rect -29 1199 29 1205
+rect -29 1165 -17 1199
+rect -29 1159 29 1165
+rect -29 71 29 77
+rect -29 37 -17 71
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+rect -29 -37 29 -31
+rect -29 -71 -17 -37
+rect -29 -77 29 -71
+rect -29 -1165 29 -1159
+rect -29 -1199 -17 -1165
+rect -29 -1205 29 -1199
+rect -29 -1273 29 -1267
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+rect -29 -1313 29 -1307
+rect -29 -2401 29 -2395
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+rect -29 -2441 29 -2435
+rect -29 -2509 29 -2503
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+rect -29 -2549 29 -2543
+rect -29 -3637 29 -3631
+rect -29 -3671 -17 -3637
+rect -29 -3677 29 -3671
+<< nwell >>
+rect -211 -3809 211 3809
+<< pmos >>
+rect -15 2590 15 3590
+rect -15 1354 15 2354
+rect -15 118 15 1118
+rect -15 -1118 15 -118
+rect -15 -2354 15 -1354
+rect -15 -3590 15 -2590
+<< pdiff >>
+rect -73 3578 -15 3590
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+rect -27 2602 -15 3578
+rect -73 2590 -15 2602
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+rect 15 2602 27 3578
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+rect -73 2342 -15 2354
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+rect -27 -1106 -15 -130
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+rect -73 -3590 -15 -3578
+rect 15 -2602 73 -2590
+rect 15 -3578 27 -2602
+rect 61 -3578 73 -2602
+rect 15 -3590 73 -3578
+<< pdiffc >>
+rect -61 2602 -27 3578
+rect 27 2602 61 3578
+rect -61 1366 -27 2342
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+rect -61 130 -27 1106
+rect 27 130 61 1106
+rect -61 -1106 -27 -130
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+rect -61 -2342 -27 -1366
+rect 27 -2342 61 -1366
+rect -61 -3578 -27 -2602
+rect 27 -3578 61 -2602
+<< nsubdiff >>
+rect -175 3739 -79 3773
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+rect -175 3677 -141 3739
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+rect -175 -3739 -141 -3677
+rect 141 -3739 175 -3677
+rect -175 -3773 -79 -3739
+rect 79 -3773 175 -3739
+<< nsubdiffcont >>
+rect -79 3739 79 3773
+rect -175 -3677 -141 3677
+rect 141 -3677 175 3677
+rect -79 -3773 79 -3739
+<< poly >>
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+rect -33 -3637 33 -3621
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+rect 17 -3671 33 -3637
+rect -33 -3687 33 -3671
+<< polycont >>
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+rect -17 -2435 17 -2401
+rect -17 -2543 17 -2509
+rect -17 -3671 17 -3637
+<< locali >>
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+rect -175 3677 -141 3739
+rect 141 3677 175 3739
+rect -33 3637 -17 3671
+rect 17 3637 33 3671
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+rect -33 1165 -17 1199
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+rect -175 -3739 -141 -3677
+rect 141 -3739 175 -3677
+rect -175 -3773 -79 -3739
+rect 79 -3773 175 -3739
+<< viali >>
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+rect -17 2509 17 2543
+rect -17 2401 17 2435
+rect -61 1366 -27 2342
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+rect -61 -3578 -27 -2602
+rect 27 -3578 61 -2602
+rect -17 -3671 17 -3637
+<< metal1 >>
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+rect -29 3637 -17 3671
+rect 17 3637 29 3671
+rect -29 3631 29 3637
+rect -67 3578 -21 3590
+rect -67 2602 -61 3578
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+rect -27 1366 -21 2342
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+rect -29 1307 29 1313
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+rect 17 1273 29 1307
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+rect -67 1106 -21 1118
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+rect 21 1106 67 1118
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+rect 21 118 67 130
+rect -29 71 29 77
+rect -29 37 -17 71
+rect 17 37 29 71
+rect -29 31 29 37
+rect -29 -37 29 -31
+rect -29 -71 -17 -37
+rect 17 -71 29 -37
+rect -29 -77 29 -71
+rect -67 -130 -21 -118
+rect -67 -1106 -61 -130
+rect -27 -1106 -21 -130
+rect -67 -1118 -21 -1106
+rect 21 -130 67 -118
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+rect 61 -1106 67 -130
+rect 21 -1118 67 -1106
+rect -29 -1165 29 -1159
+rect -29 -1199 -17 -1165
+rect 17 -1199 29 -1165
+rect -29 -1205 29 -1199
+rect -29 -1273 29 -1267
+rect -29 -1307 -17 -1273
+rect 17 -1307 29 -1273
+rect -29 -1313 29 -1307
+rect -67 -1366 -21 -1354
+rect -67 -2342 -61 -1366
+rect -27 -2342 -21 -1366
+rect -67 -2354 -21 -2342
+rect 21 -1366 67 -1354
+rect 21 -2342 27 -1366
+rect 61 -2342 67 -1366
+rect 21 -2354 67 -2342
+rect -29 -2401 29 -2395
+rect -29 -2435 -17 -2401
+rect 17 -2435 29 -2401
+rect -29 -2441 29 -2435
+rect -29 -2509 29 -2503
+rect -29 -2543 -17 -2509
+rect 17 -2543 29 -2509
+rect -29 -2549 29 -2543
+rect -67 -2602 -21 -2590
+rect -67 -3578 -61 -2602
+rect -27 -3578 -21 -2602
+rect -67 -3590 -21 -3578
+rect 21 -2602 67 -2590
+rect 21 -3578 27 -2602
+rect 61 -3578 67 -2602
+rect 21 -3590 67 -3578
+rect -29 -3637 29 -3631
+rect -29 -3671 -17 -3637
+rect 17 -3671 29 -3637
+rect -29 -3677 29 -3671
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -3756 158 3756
+string parameters w 5 l 0.15 m 6 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_YAA8Z2.mag b/mag/sky130_fd_pr__pfet_01v8_YAA8Z2.mag
new file mode 100644
index 0000000..72a5873
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_YAA8Z2.mag
@@ -0,0 +1,1195 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626793425
+<< error_p >>
+rect -269 1997 -211 2003
+rect -77 1997 -19 2003
+rect 115 1997 173 2003
+rect -269 1963 -257 1997
+rect -77 1963 -65 1997
+rect 115 1963 127 1997
+rect -269 1957 -211 1963
+rect -77 1957 -19 1963
+rect 115 1957 173 1963
+rect -173 1427 -115 1433
+rect 19 1427 77 1433
+rect 211 1427 269 1433
+rect -173 1393 -161 1427
+rect 19 1393 31 1427
+rect 211 1393 223 1427
+rect -173 1387 -115 1393
+rect 19 1387 77 1393
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+rect -173 1319 -115 1325
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+rect -173 1285 -161 1319
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+rect -173 1279 -115 1285
+rect 19 1279 77 1285
+rect 211 1279 269 1285
+rect -269 749 -211 755
+rect -77 749 -19 755
+rect 115 749 173 755
+rect -269 715 -257 749
+rect -77 715 -65 749
+rect 115 715 127 749
+rect -269 709 -211 715
+rect -77 709 -19 715
+rect 115 709 173 715
+rect -269 641 -211 647
+rect -77 641 -19 647
+rect 115 641 173 647
+rect -269 607 -257 641
+rect -77 607 -65 641
+rect 115 607 127 641
+rect -269 601 -211 607
+rect -77 601 -19 607
+rect 115 601 173 607
+rect -173 71 -115 77
+rect 19 71 77 77
+rect 211 71 269 77
+rect -173 37 -161 71
+rect 19 37 31 71
+rect 211 37 223 71
+rect -173 31 -115 37
+rect 19 31 77 37
+rect 211 31 269 37
+rect -173 -37 -115 -31
+rect 19 -37 77 -31
+rect 211 -37 269 -31
+rect -173 -71 -161 -37
+rect 19 -71 31 -37
+rect 211 -71 223 -37
+rect -173 -77 -115 -71
+rect 19 -77 77 -71
+rect 211 -77 269 -71
+rect -269 -607 -211 -601
+rect -77 -607 -19 -601
+rect 115 -607 173 -601
+rect -269 -641 -257 -607
+rect -77 -641 -65 -607
+rect 115 -641 127 -607
+rect -269 -647 -211 -641
+rect -77 -647 -19 -641
+rect 115 -647 173 -641
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+rect -77 -1997 -65 -1963
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+rect -77 -2003 -19 -1997
+rect 115 -1963 173 -1957
+rect 115 -1997 127 -1963
+rect 161 -1997 173 -1963
+rect 115 -2003 173 -1997
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -402 -2082 402 2082
+string parameters w 2.21 l 0.15 m 6 nf 6 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_generic_po_9GQS7A.mag b/mag/sky130_fd_pr__res_generic_po_9GQS7A.mag
new file mode 100644
index 0000000..c694e55
--- /dev/null
+++ b/mag/sky130_fd_pr__res_generic_po_9GQS7A.mag
@@ -0,0 +1,59 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627814077
+<< nwell >>
+rect -369 -420 369 420
+<< nsubdiff >>
+rect -333 350 -237 384
+rect 237 350 333 384
+rect -333 288 -299 350
+rect 299 288 333 350
+rect -333 -350 -299 -288
+rect 299 -350 333 -288
+rect -333 -384 -237 -350
+rect 237 -384 333 -350
+<< nsubdiffcont >>
+rect -237 350 237 384
+rect -333 -288 -299 288
+rect 299 -288 333 288
+rect -237 -384 237 -350
+<< poly >>
+rect -203 -203 -133 -180
+rect -203 -237 -187 -203
+rect -149 -237 -133 -203
+rect -203 -253 -133 -237
+rect 133 -203 203 -180
+rect 133 -237 149 -203
+rect 187 -237 203 -203
+rect 133 -253 203 -237
+<< polycont >>
+rect -187 -237 -149 -203
+rect 149 -237 187 -203
+<< npolyres >>
+rect -203 184 -21 254
+rect -203 -180 -133 184
+rect -91 -6 -21 184
+rect 21 184 203 254
+rect 21 -6 91 184
+rect -91 -76 91 -6
+rect 133 -180 203 184
+<< locali >>
+rect -333 350 -237 384
+rect 237 350 333 384
+rect -333 288 -299 350
+rect 299 288 333 350
+rect -203 -237 -187 -203
+rect -149 -237 -133 -203
+rect 133 -237 149 -203
+rect 187 -237 203 -203
+rect -333 -350 -299 -288
+rect 299 -350 333 -288
+rect -333 -384 -237 -350
+rect 237 -384 333 -350
+<< properties >>
+string gencell sky130_fd_pr__res_generic_po
+string FIXED_BBOX -316 -367 316 367
+string parameters w 0.35 l 1.650 m 1 nx 4 wmin 0.330 lmin 1.650 rho 48.2 val 1.218k dummy 0 dw 0.0 term 0.0 sterm 0.0 caplen 0.4 snake 1 guard 1 glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 full_metal 1 hv_guard 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_generic_po_9QN27A.mag b/mag/sky130_fd_pr__res_generic_po_9QN27A.mag
new file mode 100644
index 0000000..0cf9614
--- /dev/null
+++ b/mag/sky130_fd_pr__res_generic_po_9QN27A.mag
@@ -0,0 +1,59 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627812750
+<< nwell >>
+rect -373 -420 373 420
+<< nsubdiff >>
+rect -337 350 -241 384
+rect 241 350 337 384
+rect -337 288 -303 350
+rect 303 288 337 350
+rect -337 -350 -303 -288
+rect 303 -350 337 -288
+rect -337 -384 -241 -350
+rect 241 -384 337 -350
+<< nsubdiffcont >>
+rect -241 350 241 384
+rect -337 -288 -303 288
+rect 303 -288 337 288
+rect -241 -384 241 -350
+<< poly >>
+rect -207 -203 -135 -180
+rect -207 -237 -191 -203
+rect -151 -237 -135 -203
+rect -207 -253 -135 -237
+rect 135 -203 207 -180
+rect 135 -237 151 -203
+rect 191 -237 207 -203
+rect 135 -253 207 -237
+<< polycont >>
+rect -191 -237 -151 -203
+rect 151 -237 191 -203
+<< npolyres >>
+rect -207 182 -21 254
+rect -207 -180 -135 182
+rect -93 -4 -21 182
+rect 21 182 207 254
+rect 21 -4 93 182
+rect -93 -76 93 -4
+rect 135 -180 207 182
+<< locali >>
+rect -337 350 -241 384
+rect 241 350 337 384
+rect -337 288 -303 350
+rect 303 288 337 350
+rect -207 -237 -191 -203
+rect -151 -237 -135 -203
+rect 135 -237 151 -203
+rect 191 -237 207 -203
+rect -337 -350 -303 -288
+rect 303 -350 337 -288
+rect -337 -384 -241 -350
+rect 241 -384 337 -350
+<< properties >>
+string gencell sky130_fd_pr__res_generic_po
+string FIXED_BBOX -320 -367 320 367
+string parameters w 0.36 l 1.650 m 1 nx 4 wmin 0.330 lmin 1.650 rho 48.2 val 1.188k dummy 0 dw 0.0 term 0.0 sterm 0.0 caplen 0.4 snake 1 guard 1 glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 full_metal 1 hv_guard 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_generic_po_D56PGQ.mag b/mag/sky130_fd_pr__res_generic_po_D56PGQ.mag
new file mode 100644
index 0000000..0c117cc
--- /dev/null
+++ b/mag/sky130_fd_pr__res_generic_po_D56PGQ.mag
@@ -0,0 +1,59 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627814077
+<< nwell >>
+rect -365 -420 365 420
+<< nsubdiff >>
+rect -329 350 -233 384
+rect 233 350 329 384
+rect -329 288 -295 350
+rect 295 288 329 350
+rect -329 -350 -295 -288
+rect 295 -350 329 -288
+rect -329 -384 -233 -350
+rect 233 -384 329 -350
+<< nsubdiffcont >>
+rect -233 350 233 384
+rect -329 -288 -295 288
+rect 295 -288 329 288
+rect -233 -384 233 -350
+<< poly >>
+rect -199 -203 -131 -180
+rect -199 -237 -183 -203
+rect -147 -237 -131 -203
+rect -199 -253 -131 -237
+rect 131 -203 199 -180
+rect 131 -237 147 -203
+rect 183 -237 199 -203
+rect 131 -253 199 -237
+<< polycont >>
+rect -183 -237 -147 -203
+rect 147 -237 183 -203
+<< npolyres >>
+rect -199 186 -21 254
+rect -199 -180 -131 186
+rect -89 -8 -21 186
+rect 21 186 199 254
+rect 21 -8 89 186
+rect -89 -76 89 -8
+rect 131 -180 199 186
+<< locali >>
+rect -329 350 -233 384
+rect 233 350 329 384
+rect -329 288 -295 350
+rect 295 288 329 350
+rect -199 -237 -183 -203
+rect -147 -237 -131 -203
+rect 131 -237 147 -203
+rect 183 -237 199 -203
+rect -329 -350 -295 -288
+rect 295 -350 329 -288
+rect -329 -384 -233 -350
+rect 233 -384 329 -350
+<< properties >>
+string gencell sky130_fd_pr__res_generic_po
+string FIXED_BBOX -312 -367 312 367
+string parameters w 0.34 l 1.650 m 1 nx 4 wmin 0.330 lmin 1.650 rho 48.2 val 1.25k dummy 0 dw 0.0 term 0.0 sterm 0.0 caplen 0.4 snake 1 guard 1 glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 full_metal 1 hv_guard 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_high_po_0p35_4RFVXF.mag b/mag/sky130_fd_pr__res_high_po_0p35_4RFVXF.mag
new file mode 100644
index 0000000..18b1340
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_0p35_4RFVXF.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627921586
+<< xpolycontact >>
+rect -35 292 35 724
+rect -35 -724 35 -292
+<< ppolyres >>
+rect -35 -292 35 292
+<< viali >>
+rect -19 309 19 706
+rect -19 -706 19 -309
+<< metal1 >>
+rect -25 706 25 718
+rect -25 309 -19 706
+rect 19 309 25 706
+rect -25 297 25 309
+rect -25 -309 25 -297
+rect -25 -706 -19 -309
+rect 19 -706 25 -309
+rect -25 -718 25 -706
+<< res0p35 >>
+rect -37 -294 37 294
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_0p35
+string parameters w 0.350 l 2.92 m 1 nx 1 wmin 0.350 lmin 0.50 rho 319.8 val 2.777k dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 0 wmax 0.350 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_high_po_0p35_8YJL8A.mag b/mag/sky130_fd_pr__res_high_po_0p35_8YJL8A.mag
new file mode 100644
index 0000000..96f5940
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_0p35_8YJL8A.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627923075
+<< xpolycontact >>
+rect -35 605 35 1037
+rect -35 -1037 35 -605
+<< ppolyres >>
+rect -35 -605 35 605
+<< viali >>
+rect -19 622 19 1019
+rect -19 -1019 19 -622
+<< metal1 >>
+rect -25 1019 25 1031
+rect -25 622 -19 1019
+rect 19 622 25 1019
+rect -25 610 25 622
+rect -25 -622 25 -610
+rect -25 -1019 -19 -622
+rect 19 -1019 25 -622
+rect -25 -1031 25 -1019
+<< res0p35 >>
+rect -37 -607 37 607
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_0p35
+string parameters w 0.350 l 6.05 m 1 nx 1 wmin 0.350 lmin 0.50 rho 319.8 val 5.637k dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 0 wmax 0.350 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_high_po_0p35_AXF3YZ.mag b/mag/sky130_fd_pr__res_high_po_0p35_AXF3YZ.mag
new file mode 100644
index 0000000..86cb398
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_0p35_AXF3YZ.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627922418
+<< xpolycontact >>
+rect -35 262 35 694
+rect -35 -694 35 -262
+<< ppolyres >>
+rect -35 -262 35 262
+<< viali >>
+rect -19 279 19 676
+rect -19 -676 19 -279
+<< metal1 >>
+rect -25 676 25 688
+rect -25 279 -19 676
+rect 19 279 25 676
+rect -25 267 25 279
+rect -25 -279 25 -267
+rect -25 -676 -19 -279
+rect 19 -676 25 -279
+rect -25 -688 25 -676
+<< res0p35 >>
+rect -37 -264 37 264
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_0p35
+string parameters w 0.350 l 2.62 m 1 nx 1 wmin 0.350 lmin 0.50 rho 319.8 val 2.503k dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 0 wmax 0.350 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_high_po_0p35_C72MAQ.mag b/mag/sky130_fd_pr__res_high_po_0p35_C72MAQ.mag
new file mode 100644
index 0000000..62d1d59
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_0p35_C72MAQ.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628058135
+<< xpolycontact >>
+rect -35 100 35 532
+rect -35 -532 35 -100
+<< ppolyres >>
+rect -35 -100 35 100
+<< viali >>
+rect -19 117 19 514
+rect -19 -514 19 -117
+<< metal1 >>
+rect -25 514 25 526
+rect -25 117 -19 514
+rect 19 117 25 514
+rect -25 105 25 117
+rect -25 -117 25 -105
+rect -25 -514 -19 -117
+rect 19 -514 25 -117
+rect -25 -526 25 -514
+<< res0p35 >>
+rect -37 -102 37 102
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_0p35
+string parameters w 0.350 l 1 m 1 nx 1 wmin 0.350 lmin 0.50 rho 319.8 val 1.023k dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 0 wmax 0.350 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_high_po_0p35_FBWYB5.mag b/mag/sky130_fd_pr__res_high_po_0p35_FBWYB5.mag
new file mode 100644
index 0000000..abf1b29
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_0p35_FBWYB5.mag
@@ -0,0 +1,54 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627923075
+<< pwell >>
+rect -201 -1133 201 1133
+<< psubdiff >>
+rect -165 1063 -69 1097
+rect 69 1063 165 1097
+rect -165 1001 -131 1063
+rect 131 1001 165 1063
+rect -165 -1063 -131 -1001
+rect 131 -1063 165 -1001
+rect -165 -1097 -69 -1063
+rect 69 -1097 165 -1063
+<< psubdiffcont >>
+rect -69 1063 69 1097
+rect -165 -1001 -131 1001
+rect 131 -1001 165 1001
+rect -69 -1097 69 -1063
+<< xpolycontact >>
+rect -35 535 35 967
+rect -35 -967 35 -535
+<< ppolyres >>
+rect -35 -535 35 535
+<< locali >>
+rect -165 1063 -69 1097
+rect 69 1063 165 1097
+rect -165 1001 -131 1063
+rect 131 1001 165 1063
+rect -165 -1063 -131 -1001
+rect 131 -1063 165 -1001
+rect -165 -1097 -69 -1063
+rect 69 -1097 165 -1063
+<< viali >>
+rect -19 552 19 949
+rect -19 -949 19 -552
+<< metal1 >>
+rect -25 949 25 961
+rect -25 552 -19 949
+rect 19 552 25 949
+rect -25 540 25 552
+rect -25 -552 25 -540
+rect -25 -949 -19 -552
+rect 19 -949 25 -552
+rect -25 -961 25 -949
+<< res0p35 >>
+rect -37 -537 37 537
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_0p35
+string FIXED_BBOX -148 -1080 148 1080
+string parameters w 0.350 l 5.35 m 1 nx 1 wmin 0.350 lmin 0.50 rho 319.8 val 4.998k dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 1 wmax 0.350 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_high_po_0p35_K83A35.mag b/mag/sky130_fd_pr__res_high_po_0p35_K83A35.mag
new file mode 100644
index 0000000..0c9a42c
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_0p35_K83A35.mag
@@ -0,0 +1,54 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627812032
+<< pwell >>
+rect -201 -648 201 648
+<< psubdiff >>
+rect -165 578 -69 612
+rect 69 578 165 612
+rect -165 516 -131 578
+rect 131 516 165 578
+rect -165 -578 -131 -516
+rect 131 -578 165 -516
+rect -165 -612 -69 -578
+rect 69 -612 165 -578
+<< psubdiffcont >>
+rect -69 578 69 612
+rect -165 -516 -131 516
+rect 131 -516 165 516
+rect -69 -612 69 -578
+<< xpolycontact >>
+rect -35 50 35 482
+rect -35 -482 35 -50
+<< ppolyres >>
+rect -35 -50 35 50
+<< locali >>
+rect -165 578 -69 612
+rect 69 578 165 612
+rect -165 516 -131 578
+rect 131 516 165 578
+rect -165 -578 -131 -516
+rect 131 -578 165 -516
+rect -165 -612 -69 -578
+rect 69 -612 165 -578
+<< viali >>
+rect -19 67 19 464
+rect -19 -464 19 -67
+<< metal1 >>
+rect -25 464 25 476
+rect -25 67 -19 464
+rect 19 67 25 464
+rect -25 55 25 67
+rect -25 -67 25 -55
+rect -25 -464 -19 -67
+rect 19 -464 25 -67
+rect -25 -476 25 -464
+<< res0p35 >>
+rect -37 -52 37 52
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_0p35
+string FIXED_BBOX -148 -595 148 595
+string parameters w 0.350 l 0.50 m 1 nx 1 wmin 0.350 lmin 0.50 rho 319.8 val 566.502 dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 1 wmax 0.350 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_high_po_0p35_PMTBZG.mag b/mag/sky130_fd_pr__res_high_po_0p35_PMTBZG.mag
new file mode 100644
index 0000000..f0104c3
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_0p35_PMTBZG.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627923075
+<< xpolycontact >>
+rect -35 535 35 967
+rect -35 -967 35 -535
+<< ppolyres >>
+rect -35 -535 35 535
+<< viali >>
+rect -19 552 19 949
+rect -19 -949 19 -552
+<< metal1 >>
+rect -25 949 25 961
+rect -25 552 -19 949
+rect 19 552 25 949
+rect -25 540 25 552
+rect -25 -552 25 -540
+rect -25 -949 -19 -552
+rect 19 -949 25 -552
+rect -25 -961 25 -949
+<< res0p35 >>
+rect -37 -537 37 537
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_0p35
+string parameters w 0.350 l 5.35 m 1 nx 1 wmin 0.350 lmin 0.50 rho 319.8 val 4.998k dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 0 wmax 0.350 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_high_po_0p35_PNCE83.mag b/mag/sky130_fd_pr__res_high_po_0p35_PNCE83.mag
new file mode 100644
index 0000000..07014f0
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_0p35_PNCE83.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627032624
+<< xpolycontact >>
+rect -35 536 35 968
+rect -35 -968 35 -536
+<< ppolyres >>
+rect -35 -536 35 536
+<< viali >>
+rect -19 553 19 950
+rect -19 -950 19 -553
+<< metal1 >>
+rect -25 950 25 962
+rect -25 553 -19 950
+rect 19 553 25 950
+rect -25 541 25 553
+rect -25 -553 25 -541
+rect -25 -950 -19 -553
+rect 19 -950 25 -553
+rect -25 -962 25 -950
+<< res0p35 >>
+rect -37 -538 37 538
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_0p35
+string parameters w 0.350 l 5.36 m 1 nx 1 wmin 0.350 lmin 0.50 rho 319.8 val 5.007k dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 0 glc 0 grc 0 gtc 0 gbc 1 compatible {sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 0 wmax 0.350 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_high_po_0p35_PSYNU6.mag b/mag/sky130_fd_pr__res_high_po_0p35_PSYNU6.mag
new file mode 100644
index 0000000..c431166
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_0p35_PSYNU6.mag
@@ -0,0 +1,68 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627812032
+<< pwell >>
+rect -360 -648 360 648
+<< psubdiff >>
+rect -324 578 -228 612
+rect 228 578 324 612
+rect -324 516 -290 578
+rect 290 516 324 578
+rect -324 -578 -290 -516
+rect 290 -578 324 -516
+rect -324 -612 -228 -578
+rect 228 -612 324 -578
+<< psubdiffcont >>
+rect -228 578 228 612
+rect -324 -516 -290 516
+rect 290 -516 324 516
+rect -228 -612 228 -578
+<< xpolycontact >>
+rect -194 50 -124 482
+rect -194 -482 -124 -50
+rect 124 50 194 482
+rect 124 -482 194 -50
+<< ppolyres >>
+rect -194 -50 -124 50
+rect 124 -50 194 50
+<< locali >>
+rect -324 578 -228 612
+rect 228 578 324 612
+rect -324 516 -290 578
+rect 290 516 324 578
+rect -324 -578 -290 -516
+rect 290 -578 324 -516
+rect -324 -612 -228 -578
+rect 228 -612 324 -578
+<< viali >>
+rect -178 67 -140 464
+rect 140 67 178 464
+rect -178 -464 -140 -67
+rect 140 -464 178 -67
+<< metal1 >>
+rect -184 464 -134 476
+rect -184 67 -178 464
+rect -140 67 -134 464
+rect -184 55 -134 67
+rect 134 464 184 476
+rect 134 67 140 464
+rect 178 67 184 464
+rect 134 55 184 67
+rect -184 -67 -134 -55
+rect -184 -464 -178 -67
+rect -140 -464 -134 -67
+rect -184 -476 -134 -464
+rect 134 -67 184 -55
+rect 134 -464 140 -67
+rect 178 -464 184 -67
+rect 134 -476 184 -464
+<< res0p35 >>
+rect -196 -52 -122 52
+rect 122 -52 196 52
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_0p35
+string FIXED_BBOX -307 -595 307 595
+string parameters w 0.350 l 0.50 m 1 nx 2 wmin 0.350 lmin 0.50 rho 319.8 val 566.502 dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 1 wmax 0.350 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_high_po_0p35_UX2SHW.mag b/mag/sky130_fd_pr__res_high_po_0p35_UX2SHW.mag
new file mode 100644
index 0000000..14902ab
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_0p35_UX2SHW.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627922418
+<< xpolycontact >>
+rect -35 295 35 727
+rect -35 -727 35 -295
+<< ppolyres >>
+rect -35 -295 35 295
+<< viali >>
+rect -19 312 19 709
+rect -19 -709 19 -312
+<< metal1 >>
+rect -25 709 25 721
+rect -25 312 -19 709
+rect 19 312 25 709
+rect -25 300 25 312
+rect -25 -312 25 -300
+rect -25 -709 -19 -312
+rect 19 -709 25 -312
+rect -25 -721 25 -709
+<< res0p35 >>
+rect -37 -297 37 297
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_0p35
+string parameters w 0.350 l 2.95 m 1 nx 1 wmin 0.350 lmin 0.50 rho 319.8 val 2.805k dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 0 wmax 0.350 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_high_po_0p35_YAJMDJ.mag b/mag/sky130_fd_pr__res_high_po_0p35_YAJMDJ.mag
new file mode 100644
index 0000000..27eb47f
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_0p35_YAJMDJ.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628058135
+<< xpolycontact >>
+rect -35 100 35 532
+rect -35 -532 35 -100
+<< ppolyres >>
+rect -35 -100 35 100
+<< viali >>
+rect -19 117 19 514
+rect -19 -514 19 -117
+<< metal1 >>
+rect -25 514 25 526
+rect -25 117 -19 514
+rect 19 117 25 514
+rect -25 105 25 117
+rect -25 -117 25 -105
+rect -25 -514 -19 -117
+rect 19 -514 25 -117
+rect -25 -526 25 -514
+<< res0p35 >>
+rect -37 -102 37 102
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_0p35
+string parameters w 0.350 l 1. m 1 nx 1 wmin 0.350 lmin 0.50 rho 319.8 val 1.023k dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 0 wmax 0.350 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_high_po_0p69_37KMYC.mag b/mag/sky130_fd_pr__res_high_po_0p69_37KMYC.mag
new file mode 100644
index 0000000..adbccdc
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_0p69_37KMYC.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628059316
+<< xpolycontact >>
+rect -69 96 69 528
+rect -69 -528 69 -96
+<< ppolyres >>
+rect -69 -96 69 96
+<< viali >>
+rect -53 113 53 510
+rect -53 -510 53 -113
+<< metal1 >>
+rect -59 510 59 522
+rect -59 113 -53 510
+rect 53 113 59 510
+rect -59 101 59 113
+rect -59 -113 59 -101
+rect -59 -510 -53 -113
+rect 53 -510 59 -113
+rect -59 -522 59 -510
+<< res0p69 >>
+rect -71 -98 71 98
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_0p69
+string parameters w 0.690 l 0.96 m 1 nx 1 wmin 0.690 lmin 0.50 rho 319.8 val 500.556 dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 0 wmax 0.690 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_high_po_0p69_7JPRER.mag b/mag/sky130_fd_pr__res_high_po_0p69_7JPRER.mag
new file mode 100644
index 0000000..7a153c8
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_0p69_7JPRER.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628069922
+<< xpolycontact >>
+rect -69 95 69 527
+rect -69 -527 69 -95
+<< ppolyres >>
+rect -69 -95 69 95
+<< viali >>
+rect -53 112 53 509
+rect -53 -509 53 -112
+<< metal1 >>
+rect -59 509 59 521
+rect -59 112 -53 509
+rect 53 112 59 509
+rect -59 100 59 112
+rect -59 -112 59 -100
+rect -59 -509 -53 -112
+rect 53 -509 59 -112
+rect -59 -521 59 -509
+<< res0p69 >>
+rect -71 -97 71 97
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_0p69
+string parameters w 0.690 l 0.95 m 1 nx 1 wmin 0.690 lmin 0.50 rho 319.8 val 495.921 dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 0 wmax 0.690 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_iso_pw_729TKM.mag b/mag/sky130_fd_pr__res_iso_pw_729TKM.mag
new file mode 100644
index 0000000..ae0e39b
--- /dev/null
+++ b/mag/sky130_fd_pr__res_iso_pw_729TKM.mag
@@ -0,0 +1,81 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627036492
+<< dnwell >>
+rect -471 -3014 471 3014
+<< nwell >>
+rect -551 2808 551 3094
+rect -551 -2808 -265 2808
+rect 265 -2808 551 2808
+rect -551 -3094 551 -2808
+<< pwell >>
+rect -265 2650 265 2808
+rect -265 -2808 265 -2650
+<< rpw >>
+rect -265 -2650 265 2650
+<< psubdiff >>
+rect -225 2650 -201 2756
+rect 201 2650 225 2756
+rect -225 -2756 -201 -2650
+rect 201 -2756 225 -2650
+<< nsubdiff >>
+rect -425 2934 -329 2968
+rect 329 2934 425 2968
+rect -425 2872 -391 2934
+rect 391 2872 425 2934
+rect -425 -2934 -391 -2872
+rect 391 -2934 425 -2872
+rect -425 -2968 -329 -2934
+rect 329 -2968 425 -2934
+<< psubdiffcont >>
+rect -201 2650 201 2756
+rect -201 -2756 201 -2650
+<< nsubdiffcont >>
+rect -329 2934 329 2968
+rect -425 -2872 -391 2872
+rect 391 -2872 425 2872
+rect -329 -2968 329 -2934
+<< locali >>
+rect -425 2934 -329 2968
+rect 329 2934 425 2968
+rect -425 2872 -391 2934
+rect 391 2872 425 2934
+rect -217 2720 -201 2756
+rect 201 2720 217 2756
+rect -217 2667 -213 2720
+rect 213 2667 217 2720
+rect -217 2650 -201 2667
+rect 201 2650 217 2667
+rect -217 -2667 -201 -2650
+rect 201 -2667 217 -2650
+rect -217 -2720 -213 -2667
+rect 213 -2720 217 -2667
+rect -217 -2756 -201 -2720
+rect 201 -2756 217 -2720
+rect -425 -2934 -391 -2872
+rect 391 -2934 425 -2872
+rect -425 -2968 -329 -2934
+rect 329 -2968 425 -2934
+<< viali >>
+rect -213 2667 -201 2720
+rect -201 2667 201 2720
+rect 201 2667 213 2720
+rect -213 -2720 -201 -2667
+rect -201 -2720 201 -2667
+rect 201 -2720 213 -2667
+<< metal1 >>
+rect -225 2720 225 2726
+rect -225 2667 -213 2720
+rect 213 2667 225 2720
+rect -225 2661 225 2667
+rect -225 -2667 225 -2661
+rect -225 -2720 -213 -2667
+rect 213 -2720 225 -2667
+rect -225 -2726 225 -2720
+<< properties >>
+string gencell sky130_fd_pr__res_iso_pw
+string FIXED_BBOX -408 -2951 408 2951
+string parameters w 2.650 l 26.50 m 1 nx 1 wmin 2.650 lmin 26.50 rho 975 val 10.766k dummy 0 dw 0.25 term 1.0 guard 1 endcov 100 full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_2XPN6P.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_2XPN6P.mag
new file mode 100644
index 0000000..8e0a6bd
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_2XPN6P.mag
@@ -0,0 +1,36 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627045530
+<< pwell >>
+rect -201 -674 201 674
+<< psubdiff >>
+rect -165 604 165 638
+rect -165 -604 -131 604
+rect 131 -604 165 604
+rect -165 -638 165 -604
+<< xpolycontact >>
+rect -35 76 35 508
+rect -35 -508 35 -76
+<< xpolyres >>
+rect -35 -76 35 76
+<< viali >>
+rect -19 93 19 490
+rect -19 -490 19 -93
+<< metal1 >>
+rect -25 490 25 502
+rect -25 93 -19 490
+rect 19 93 25 490
+rect -25 81 25 93
+rect -25 -93 25 -81
+rect -25 -490 -19 -93
+rect 19 -490 25 -93
+rect -25 -502 25 -490
+<< res0p35 >>
+rect -37 -78 37 78
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string FIXED_BBOX -148 -621 148 621
+string parameters w 0.350 l 0.76 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 5.028k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 1 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_35JNSN.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_35JNSN.mag
new file mode 100644
index 0000000..2a52d2a
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_35JNSN.mag
@@ -0,0 +1,311 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627036492
+<< pwell >>
+rect -3222 -1286 3222 1286
+<< psubdiff >>
+rect -3186 1216 3186 1250
+rect -3186 -1216 -3152 1216
+rect 3152 -1216 3186 1216
+rect -3186 -1250 -3090 -1216
+rect 3090 -1250 3186 -1216
+<< psubdiffcont >>
+rect -3090 -1250 3090 -1216
+<< xpolycontact >>
+rect -3056 688 -2986 1120
+rect -3056 -1120 -2986 -688
+rect -2738 688 -2668 1120
+rect -2738 -1120 -2668 -688
+rect -2420 688 -2350 1120
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+rect -2102 688 -2032 1120
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+rect -1784 688 -1714 1120
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+rect -1466 688 -1396 1120
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+rect -830 688 -760 1120
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+rect -512 688 -442 1120
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+rect -194 688 -124 1120
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+rect 124 688 194 1120
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+rect 760 688 830 1120
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+rect 2668 688 2738 1120
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+rect 2986 688 3056 1120
+rect 2986 -1120 3056 -688
+<< xpolyres >>
+rect -3056 -688 -2986 688
+rect -2738 -688 -2668 688
+rect -2420 -688 -2350 688
+rect -2102 -688 -2032 688
+rect -1784 -688 -1714 688
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+rect 1714 -688 1784 688
+rect 2032 -688 2102 688
+rect 2350 -688 2420 688
+rect 2668 -688 2738 688
+rect 2986 -688 3056 688
+<< locali >>
+rect -3186 1216 3186 1250
+rect -3186 -1216 -3152 1216
+rect 3152 -1216 3186 1216
+rect -3186 -1250 -3090 -1216
+rect 3090 -1250 3186 -1216
+<< viali >>
+rect -3040 705 -3002 1102
+rect -2722 705 -2684 1102
+rect -2404 705 -2366 1102
+rect -2086 705 -2048 1102
+rect -1768 705 -1730 1102
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+rect 3002 -1102 3040 -705
+<< metal1 >>
+rect -3046 1102 -2996 1114
+rect -3046 705 -3040 1102
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+rect -3046 693 -2996 705
+rect -2728 1102 -2678 1114
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+rect -1412 -1102 -1406 -705
+rect -1456 -1114 -1406 -1102
+rect -1138 -705 -1088 -693
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+rect -1094 -1102 -1088 -705
+rect -1138 -1114 -1088 -1102
+rect -820 -705 -770 -693
+rect -820 -1102 -814 -705
+rect -776 -1102 -770 -705
+rect -820 -1114 -770 -1102
+rect -502 -705 -452 -693
+rect -502 -1102 -496 -705
+rect -458 -1102 -452 -705
+rect -502 -1114 -452 -1102
+rect -184 -705 -134 -693
+rect -184 -1102 -178 -705
+rect -140 -1102 -134 -705
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+rect 134 -705 184 -693
+rect 134 -1102 140 -705
+rect 178 -1102 184 -705
+rect 134 -1114 184 -1102
+rect 452 -705 502 -693
+rect 452 -1102 458 -705
+rect 496 -1102 502 -705
+rect 452 -1114 502 -1102
+rect 770 -705 820 -693
+rect 770 -1102 776 -705
+rect 814 -1102 820 -705
+rect 770 -1114 820 -1102
+rect 1088 -705 1138 -693
+rect 1088 -1102 1094 -705
+rect 1132 -1102 1138 -705
+rect 1088 -1114 1138 -1102
+rect 1406 -705 1456 -693
+rect 1406 -1102 1412 -705
+rect 1450 -1102 1456 -705
+rect 1406 -1114 1456 -1102
+rect 1724 -705 1774 -693
+rect 1724 -1102 1730 -705
+rect 1768 -1102 1774 -705
+rect 1724 -1114 1774 -1102
+rect 2042 -705 2092 -693
+rect 2042 -1102 2048 -705
+rect 2086 -1102 2092 -705
+rect 2042 -1114 2092 -1102
+rect 2360 -705 2410 -693
+rect 2360 -1102 2366 -705
+rect 2404 -1102 2410 -705
+rect 2360 -1114 2410 -1102
+rect 2678 -705 2728 -693
+rect 2678 -1102 2684 -705
+rect 2722 -1102 2728 -705
+rect 2678 -1114 2728 -1102
+rect 2996 -705 3046 -693
+rect 2996 -1102 3002 -705
+rect 3040 -1102 3046 -705
+rect 2996 -1114 3046 -1102
+<< res0p35 >>
+rect -3058 -690 -2984 690
+rect -2740 -690 -2666 690
+rect -2422 -690 -2348 690
+rect -2104 -690 -2030 690
+rect -1786 -690 -1712 690
+rect -1468 -690 -1394 690
+rect -1150 -690 -1076 690
+rect -832 -690 -758 690
+rect -514 -690 -440 690
+rect -196 -690 -122 690
+rect 122 -690 196 690
+rect 440 -690 514 690
+rect 758 -690 832 690
+rect 1076 -690 1150 690
+rect 1394 -690 1468 690
+rect 1712 -690 1786 690
+rect 2030 -690 2104 690
+rect 2348 -690 2422 690
+rect 2666 -690 2740 690
+rect 2984 -690 3058 690
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string FIXED_BBOX -3169 -1233 3169 1233
+string parameters w 0.350 l 6.88 m 1 nx 20 wmin 0.350 lmin 0.50 rho 2000 val 40.0k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 1 glc 0 grc 0 gtc 0 gbc 1 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_3UHKWS.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_3UHKWS.mag
new file mode 100644
index 0000000..8562648
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_3UHKWS.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627037519
+<< xpolycontact >>
+rect -35 688 35 1120
+rect -35 -1120 35 -688
+<< xpolyres >>
+rect -35 -688 35 688
+<< viali >>
+rect -19 705 19 1102
+rect -19 -1102 19 -705
+<< metal1 >>
+rect -25 1102 25 1114
+rect -25 705 -19 1102
+rect 19 705 25 1102
+rect -25 693 25 705
+rect -25 -705 25 -693
+rect -25 -1102 -19 -705
+rect 19 -1102 25 -705
+rect -25 -1114 25 -1102
+<< res0p35 >>
+rect -37 -690 37 690
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 6.88 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 40.0k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_5BVMEJ.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_5BVMEJ.mag
new file mode 100644
index 0000000..525f86f
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_5BVMEJ.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627805142
+<< xpolycontact >>
+rect -35 75 35 507
+rect -35 -507 35 -75
+<< xpolyres >>
+rect -35 -75 35 75
+<< viali >>
+rect -19 92 19 489
+rect -19 -489 19 -92
+<< metal1 >>
+rect -25 489 25 501
+rect -25 92 -19 489
+rect 19 92 25 489
+rect -25 80 25 92
+rect -25 -92 25 -80
+rect -25 -489 -19 -92
+rect 19 -489 25 -92
+rect -25 -501 25 -489
+<< res0p35 >>
+rect -37 -77 37 77
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 0.75 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 4.971k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_7NH2RC.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_7NH2RC.mag
new file mode 100644
index 0000000..464b108
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_7NH2RC.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627923075
+<< xpolycontact >>
+rect -35 280 35 712
+rect -35 -712 35 -280
+<< xpolyres >>
+rect -35 -280 35 280
+<< viali >>
+rect -19 297 19 694
+rect -19 -694 19 -297
+<< metal1 >>
+rect -25 694 25 706
+rect -25 297 -19 694
+rect 19 297 25 694
+rect -25 285 25 297
+rect -25 -297 25 -285
+rect -25 -694 -19 -297
+rect 19 -694 25 -297
+rect -25 -706 25 -694
+<< res0p35 >>
+rect -37 -282 37 282
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 2.8 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 16.685k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_95A2JL.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_95A2JL.mag
new file mode 100644
index 0000000..c75b0db
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_95A2JL.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627921586
+<< xpolycontact >>
+rect -35 893 35 1325
+rect -35 -1325 35 -893
+<< xpolyres >>
+rect -35 -893 35 893
+<< viali >>
+rect -19 910 19 1307
+rect -19 -1307 19 -910
+<< metal1 >>
+rect -25 1307 25 1319
+rect -25 910 -19 1307
+rect 19 910 25 1307
+rect -25 898 25 910
+rect -25 -910 25 -898
+rect -25 -1307 -19 -910
+rect 19 -1307 25 -910
+rect -25 -1319 25 -1307
+<< res0p35 >>
+rect -37 -895 37 895
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 8.93 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 51.714k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_J3RZA8.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_J3RZA8.mag
new file mode 100644
index 0000000..4652f9a
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_J3RZA8.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627805856
+<< xpolycontact >>
+rect -35 77 35 509
+rect -35 -509 35 -77
+<< xpolyres >>
+rect -35 -77 35 77
+<< viali >>
+rect -19 94 19 491
+rect -19 -491 19 -94
+<< metal1 >>
+rect -25 491 25 503
+rect -25 94 -19 491
+rect 19 94 25 491
+rect -25 82 25 94
+rect -25 -94 25 -82
+rect -25 -491 -19 -94
+rect 19 -491 25 -94
+rect -25 -503 25 -491
+<< res0p35 >>
+rect -37 -79 37 79
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 0.77 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 5.085k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_K53MS3.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_K53MS3.mag
new file mode 100644
index 0000000..a2f645a
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_K53MS3.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627996865
+<< xpolycontact >>
+rect -35 251 35 683
+rect -35 -683 35 -251
+<< xpolyres >>
+rect -35 -251 35 251
+<< viali >>
+rect -19 268 19 665
+rect -19 -665 19 -268
+<< metal1 >>
+rect -25 665 25 677
+rect -25 268 -19 665
+rect 19 268 25 665
+rect -25 256 25 268
+rect -25 -268 25 -256
+rect -25 -665 -19 -268
+rect 19 -665 25 -268
+rect -25 -677 25 -665
+<< res0p35 >>
+rect -37 -253 37 253
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 2.51 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 15.028k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_KDN527.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_KDN527.mag
new file mode 100644
index 0000000..d6cc636
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_KDN527.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627923075
+<< xpolycontact >>
+rect -35 251 35 683
+rect -35 -683 35 -251
+<< xpolyres >>
+rect -35 -251 35 251
+<< viali >>
+rect -19 268 19 665
+rect -19 -665 19 -268
+<< metal1 >>
+rect -25 665 25 677
+rect -25 268 -19 665
+rect 19 268 25 665
+rect -25 256 25 268
+rect -25 -268 25 -256
+rect -25 -665 -19 -268
+rect 19 -665 25 -268
+rect -25 -677 25 -665
+<< res0p35 >>
+rect -37 -253 37 253
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 2.51 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 15.028k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 1 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_M9RFTX.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_M9RFTX.mag
new file mode 100644
index 0000000..45e24ce
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_M9RFTX.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627923075
+<< xpolycontact >>
+rect -35 638 35 1070
+rect -35 -1070 35 -638
+<< xpolyres >>
+rect -35 -638 35 638
+<< viali >>
+rect -19 655 19 1052
+rect -19 -1052 19 -655
+<< metal1 >>
+rect -25 1052 25 1064
+rect -25 655 -19 1052
+rect 19 655 25 1052
+rect -25 643 25 655
+rect -25 -655 25 -643
+rect -25 -1052 -19 -655
+rect 19 -1052 25 -655
+rect -25 -1064 25 -1052
+<< res0p35 >>
+rect -37 -640 37 640
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 6.38 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 37.142k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_MLNHE3.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_MLNHE3.mag
new file mode 100644
index 0000000..0679c4c
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_MLNHE3.mag
@@ -0,0 +1,68 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627810895
+<< pwell >>
+rect -360 -677 360 677
+<< psubdiff >>
+rect -324 607 -228 641
+rect 228 607 324 641
+rect -324 545 -290 607
+rect 290 545 324 607
+rect -324 -607 -290 -545
+rect 290 -607 324 -545
+rect -324 -641 -228 -607
+rect 228 -641 324 -607
+<< psubdiffcont >>
+rect -228 607 228 641
+rect -324 -545 -290 545
+rect 290 -545 324 545
+rect -228 -641 228 -607
+<< xpolycontact >>
+rect -194 79 -124 511
+rect -194 -511 -124 -79
+rect 124 79 194 511
+rect 124 -511 194 -79
+<< xpolyres >>
+rect -194 -79 -124 79
+rect 124 -79 194 79
+<< locali >>
+rect -324 607 -228 641
+rect 228 607 324 641
+rect -324 545 -290 607
+rect 290 545 324 607
+rect -324 -607 -290 -545
+rect 290 -607 324 -545
+rect -324 -641 -228 -607
+rect 228 -641 324 -607
+<< viali >>
+rect -178 96 -140 493
+rect 140 96 178 493
+rect -178 -493 -140 -96
+rect 140 -493 178 -96
+<< metal1 >>
+rect -184 493 -134 505
+rect -184 96 -178 493
+rect -140 96 -134 493
+rect -184 84 -134 96
+rect 134 493 184 505
+rect 134 96 140 493
+rect 178 96 184 493
+rect 134 84 184 96
+rect -184 -96 -134 -84
+rect -184 -493 -178 -96
+rect -140 -493 -134 -96
+rect -184 -505 -134 -493
+rect 134 -96 184 -84
+rect 134 -493 140 -96
+rect 178 -493 184 -96
+rect 134 -505 184 -493
+<< res0p35 >>
+rect -196 -81 -122 81
+rect 122 -81 196 81
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string FIXED_BBOX -307 -624 307 624
+string parameters w 0.350 l 0.79 m 1 nx 2 wmin 0.350 lmin 0.50 rho 2000 val 5.2k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_MT7BFK.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_MT7BFK.mag
new file mode 100644
index 0000000..6604741
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_MT7BFK.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627921586
+<< xpolycontact >>
+rect -35 109 35 541
+rect -35 -541 35 -109
+<< xpolyres >>
+rect -35 -109 35 109
+<< viali >>
+rect -19 126 19 523
+rect -19 -523 19 -126
+<< metal1 >>
+rect -25 523 25 535
+rect -25 126 -19 523
+rect 19 126 25 523
+rect -25 114 25 126
+rect -25 -126 25 -114
+rect -25 -523 -19 -126
+rect 19 -523 25 -126
+rect -25 -535 25 -523
+<< res0p35 >>
+rect -37 -111 37 111
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 1.09 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 6.914k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_NETUYW.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_NETUYW.mag
new file mode 100644
index 0000000..4a3f968
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_NETUYW.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627748178
+<< xpolycontact >>
+rect -35 150 35 582
+rect -35 -582 35 -150
+<< xpolyres >>
+rect -35 -150 35 150
+<< viali >>
+rect -19 167 19 564
+rect -19 -564 19 -167
+<< metal1 >>
+rect -25 564 25 576
+rect -25 167 -19 564
+rect 19 167 25 564
+rect -25 155 25 167
+rect -25 -167 25 -155
+rect -25 -564 -19 -167
+rect 19 -564 25 -167
+rect -25 -576 25 -564
+<< res0p35 >>
+rect -37 -152 37 152
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 1.5 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 9.257k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_NR2KWC.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_NR2KWC.mag
new file mode 100644
index 0000000..b570311
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_NR2KWC.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627668659
+<< xpolycontact >>
+rect -35 76 35 508
+rect -35 -508 35 -76
+<< xpolyres >>
+rect -35 -76 35 76
+<< viali >>
+rect -19 93 19 490
+rect -19 -490 19 -93
+<< metal1 >>
+rect -25 490 25 502
+rect -25 93 -19 490
+rect 19 93 25 490
+rect -25 81 25 93
+rect -25 -93 25 -81
+rect -25 -490 -19 -93
+rect 19 -490 25 -93
+rect -25 -502 25 -490
+<< res0p35 >>
+rect -37 -78 37 78
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 0.76 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 5.028k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 1 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_NZHUVC.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_NZHUVC.mag
new file mode 100644
index 0000000..d9cb00d
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_NZHUVC.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627748178
+<< xpolycontact >>
+rect -35 76 35 508
+rect -35 -508 35 -76
+<< xpolyres >>
+rect -35 -76 35 76
+<< viali >>
+rect -19 93 19 490
+rect -19 -490 19 -93
+<< metal1 >>
+rect -25 490 25 502
+rect -25 93 -19 490
+rect 19 93 25 490
+rect -25 81 25 93
+rect -25 -93 25 -81
+rect -25 -490 -19 -93
+rect 19 -490 25 -93
+rect -25 -502 25 -490
+<< res0p35 >>
+rect -37 -78 37 78
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 0.76 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 5.028k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_P8CC5E.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_P8CC5E.mag
new file mode 100644
index 0000000..5494a8f
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_P8CC5E.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628027270
+<< xpolycontact >>
+rect -35 234 35 666
+rect -35 -666 35 -234
+<< xpolyres >>
+rect -35 -234 35 234
+<< viali >>
+rect -19 251 19 648
+rect -19 -648 19 -251
+<< metal1 >>
+rect -25 648 25 660
+rect -25 251 -19 648
+rect 19 251 25 648
+rect -25 239 25 251
+rect -25 -251 25 -239
+rect -25 -648 -19 -251
+rect 19 -648 25 -251
+rect -25 -660 25 -648
+<< res0p35 >>
+rect -37 -236 37 236
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 2.34 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 14.057k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_RG46CN.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_RG46CN.mag
new file mode 100644
index 0000000..f46f447
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_RG46CN.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627922418
+<< xpolycontact >>
+rect -35 343 35 775
+rect -35 -775 35 -343
+<< xpolyres >>
+rect -35 -343 35 343
+<< viali >>
+rect -19 360 19 757
+rect -19 -757 19 -360
+<< metal1 >>
+rect -25 757 25 769
+rect -25 360 -19 757
+rect 19 360 25 757
+rect -25 348 25 360
+rect -25 -360 25 -348
+rect -25 -757 -19 -360
+rect 19 -757 25 -360
+rect -25 -769 25 -757
+<< res0p35 >>
+rect -37 -345 37 345
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 3.43 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 20.285k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_S33692.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_S33692.mag
new file mode 100644
index 0000000..f2542d0
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_S33692.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627921586
+<< xpolycontact >>
+rect -35 99 35 531
+rect -35 -531 35 -99
+<< xpolyres >>
+rect -35 -99 35 99
+<< viali >>
+rect -19 116 19 513
+rect -19 -513 19 -116
+<< metal1 >>
+rect -25 513 25 525
+rect -25 116 -19 513
+rect 19 116 25 513
+rect -25 104 25 116
+rect -25 -116 25 -104
+rect -25 -513 -19 -116
+rect 19 -513 25 -116
+rect -25 -525 25 -513
+<< res0p35 >>
+rect -37 -101 37 101
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 0.99 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 6.342k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_T8PEF7.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_T8PEF7.mag
new file mode 100644
index 0000000..7c56d34
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_T8PEF7.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627922418
+<< xpolycontact >>
+rect -35 383 35 815
+rect -35 -815 35 -383
+<< xpolyres >>
+rect -35 -383 35 383
+<< viali >>
+rect -19 400 19 797
+rect -19 -797 19 -400
+<< metal1 >>
+rect -25 797 25 809
+rect -25 400 -19 797
+rect 19 400 25 797
+rect -25 388 25 400
+rect -25 -400 25 -388
+rect -25 -797 -19 -400
+rect 19 -797 25 -400
+rect -25 -809 25 -797
+<< res0p35 >>
+rect -37 -385 37 385
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 3.83 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 22.571k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_V48BHK.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_V48BHK.mag
new file mode 100644
index 0000000..463ac4f
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_V48BHK.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627050195
+<< xpolycontact >>
+rect -35 73 35 505
+rect -35 -505 35 -73
+<< xpolyres >>
+rect -35 -73 35 73
+<< viali >>
+rect -19 90 19 487
+rect -19 -487 19 -90
+<< metal1 >>
+rect -25 487 25 499
+rect -25 90 -19 487
+rect 19 90 25 487
+rect -25 78 25 90
+rect -25 -90 25 -78
+rect -25 -487 -19 -90
+rect 19 -487 25 -90
+rect -25 -499 25 -487
+<< res0p35 >>
+rect -37 -75 37 75
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 0.73 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 4.857k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_VKZ9MG.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_VKZ9MG.mag
new file mode 100644
index 0000000..1d51ac9
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_VKZ9MG.mag
@@ -0,0 +1,54 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627922418
+<< pwell >>
+rect -201 -981 201 981
+<< psubdiff >>
+rect -165 911 -69 945
+rect 69 911 165 945
+rect -165 849 -131 911
+rect 131 849 165 911
+rect -165 -911 -131 -849
+rect 131 -911 165 -849
+rect -165 -945 -69 -911
+rect 69 -945 165 -911
+<< psubdiffcont >>
+rect -69 911 69 945
+rect -165 -849 -131 849
+rect 131 -849 165 849
+rect -69 -945 69 -911
+<< xpolycontact >>
+rect -35 383 35 815
+rect -35 -815 35 -383
+<< xpolyres >>
+rect -35 -383 35 383
+<< locali >>
+rect -165 911 -69 945
+rect 69 911 165 945
+rect -165 849 -131 911
+rect 131 849 165 911
+rect -165 -911 -131 -849
+rect 131 -911 165 -849
+rect -165 -945 -69 -911
+rect 69 -945 165 -911
+<< viali >>
+rect -19 400 19 797
+rect -19 -797 19 -400
+<< metal1 >>
+rect -25 797 25 809
+rect -25 400 -19 797
+rect 19 400 25 797
+rect -25 388 25 400
+rect -25 -400 25 -388
+rect -25 -797 -19 -400
+rect 19 -797 25 -400
+rect -25 -809 25 -797
+<< res0p35 >>
+rect -37 -385 37 385
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string FIXED_BBOX -148 -928 148 928
+string parameters w 0.350 l 3.83 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 22.571k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_WLHZTT.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_WLHZTT.mag
new file mode 100644
index 0000000..da12a5a
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_WLHZTT.mag
@@ -0,0 +1,54 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627810895
+<< pwell >>
+rect -201 -677 201 677
+<< psubdiff >>
+rect -165 607 -69 641
+rect 69 607 165 641
+rect -165 545 -131 607
+rect 131 545 165 607
+rect -165 -607 -131 -545
+rect 131 -607 165 -545
+rect -165 -641 -69 -607
+rect 69 -641 165 -607
+<< psubdiffcont >>
+rect -69 607 69 641
+rect -165 -545 -131 545
+rect 131 -545 165 545
+rect -69 -641 69 -607
+<< xpolycontact >>
+rect -35 79 35 511
+rect -35 -511 35 -79
+<< xpolyres >>
+rect -35 -79 35 79
+<< locali >>
+rect -165 607 -69 641
+rect 69 607 165 641
+rect -165 545 -131 607
+rect 131 545 165 607
+rect -165 -607 -131 -545
+rect 131 -607 165 -545
+rect -165 -641 -69 -607
+rect 69 -641 165 -607
+<< viali >>
+rect -19 96 19 493
+rect -19 -493 19 -96
+<< metal1 >>
+rect -25 493 25 505
+rect -25 96 -19 493
+rect 19 96 25 493
+rect -25 84 25 96
+rect -25 -96 25 -84
+rect -25 -493 -19 -96
+rect 19 -493 25 -96
+rect -25 -505 25 -493
+<< res0p35 >>
+rect -37 -81 37 81
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string FIXED_BBOX -148 -624 148 624
+string parameters w 0.350 l 0.79 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 5.2k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_X3XLR2.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_X3XLR2.mag
new file mode 100644
index 0000000..eeeda3e
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_X3XLR2.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627921586
+<< xpolycontact >>
+rect -35 835 35 1267
+rect -35 -1267 35 -835
+<< xpolyres >>
+rect -35 -835 35 835
+<< viali >>
+rect -19 852 19 1249
+rect -19 -1249 19 -852
+<< metal1 >>
+rect -25 1249 25 1261
+rect -25 852 -19 1249
+rect 19 852 25 1249
+rect -25 840 25 852
+rect -25 -852 25 -840
+rect -25 -1249 -19 -852
+rect 19 -1249 25 -852
+rect -25 -1261 25 -1249
+<< res0p35 >>
+rect -37 -837 37 837
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 8.35 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 48.4k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p35_XBU5ZB.mag b/mag/sky130_fd_pr__res_xhigh_po_0p35_XBU5ZB.mag
new file mode 100644
index 0000000..4ac5b29
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p35_XBU5ZB.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627834371
+<< xpolycontact >>
+rect -35 79 35 511
+rect -35 -511 35 -79
+<< xpolyres >>
+rect -35 -79 35 79
+<< viali >>
+rect -19 96 19 493
+rect -19 -493 19 -96
+<< metal1 >>
+rect -25 493 25 505
+rect -25 96 -19 493
+rect 19 96 25 493
+rect -25 84 25 96
+rect -25 -96 25 -84
+rect -25 -493 -19 -96
+rect 19 -493 25 -96
+rect -25 -505 25 -493
+<< res0p35 >>
+rect -37 -81 37 81
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p35
+string parameters w 0.350 l 0.79 m 1 nx 1 wmin 0.350 lmin 0.50 rho 2000 val 5.2k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.350 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_1p41_AHSSYP.mag b/mag/sky130_fd_pr__res_xhigh_po_1p41_AHSSYP.mag
new file mode 100644
index 0000000..9a6b3b7
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_1p41_AHSSYP.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627111729
+<< xpolycontact >>
+rect -141 165 141 597
+rect -141 -597 141 -165
+<< xpolyres >>
+rect -141 -165 141 165
+<< viali >>
+rect -125 182 125 579
+rect -125 -579 125 -182
+<< metal1 >>
+rect -131 579 131 591
+rect -131 182 -125 579
+rect 125 182 131 579
+rect -131 170 131 182
+rect -131 -182 131 -170
+rect -131 -579 -125 -182
+rect 125 -579 131 -182
+rect -131 -591 131 -579
+<< res1p41 >>
+rect -143 -167 143 167
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_1p41
+string parameters w 1.410 l 1.65 m 1 nx 1 wmin 1.410 lmin 0.50 rho 2000 val 2.51k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 1.410 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_1p41_FS8TWK.mag b/mag/sky130_fd_pr__res_xhigh_po_1p41_FS8TWK.mag
new file mode 100644
index 0000000..347a8ff
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_1p41_FS8TWK.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1627111729
+<< xpolycontact >>
+rect -141 59 141 491
+rect -141 -491 141 -59
+<< xpolyres >>
+rect -141 -59 141 59
+<< viali >>
+rect -125 76 125 473
+rect -125 -473 125 -76
+<< metal1 >>
+rect -131 473 131 485
+rect -131 76 -125 473
+rect 125 76 131 473
+rect -131 64 131 76
+rect -131 -76 131 -64
+rect -131 -473 -125 -76
+rect 125 -473 131 -76
+rect -131 -485 131 -473
+<< res1p41 >>
+rect -143 -61 143 61
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_1p41
+string parameters w 1.410 l 0.59 m 1 nx 1 wmin 1.410 lmin 0.50 rho 2000 val 1.007k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 1.410 guard 0 glc 0 grc 0 gtc 0 gbc 0 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/user_analog_project_wrapper.gds b/mag/user_analog_project_wrapper.gds
new file mode 100644
index 0000000..f0959a4
--- /dev/null
+++ b/mag/user_analog_project_wrapper.gds
Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
new file mode 100644
index 0000000..640da11
--- /dev/null
+++ b/mag/user_analog_project_wrapper.mag
@@ -0,0 +1,2204 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1628083528
+<< metal1 >>
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+rect 483960 675530 491654 675810
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+<< via1 >>
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+rect 510006 673098 510688 673476
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+rect 540698 -800 540810 480
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+rect 545426 -800 545538 480
+rect 546608 -800 546720 480
+rect 547790 -800 547902 480
+rect 548972 -800 549084 480
+rect 550154 -800 550266 480
+rect 551336 -800 551448 480
+rect 552518 -800 552630 480
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+rect 556064 -800 556176 480
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+rect 558428 -800 558540 480
+rect 559610 -800 559722 480
+rect 560792 -800 560904 480
+rect 561974 -800 562086 480
+rect 563156 -800 563268 480
+rect 564338 -800 564450 480
+rect 565520 -800 565632 480
+rect 566702 -800 566814 480
+rect 567884 -800 567996 480
+rect 569066 -800 569178 480
+rect 570248 -800 570360 480
+rect 571430 -800 571542 480
+rect 572612 -800 572724 480
+rect 573794 -800 573906 480
+rect 574976 -800 575088 480
+rect 576158 -800 576270 480
+rect 577340 -800 577452 480
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+rect 579704 -800 579816 480
+rect 580886 -800 580998 480
+rect 582068 -800 582180 480
+rect 583250 -800 583362 480
+<< via2 >>
+rect 483176 675530 483960 675810
+rect 502036 674696 504502 675944
+rect 510006 673098 510688 673476
+rect 486634 672642 487384 672906
+rect 489910 669880 490702 670160
+rect 502380 669808 507200 671230
+<< metal3 >>
+rect 16194 702300 21194 704800
+rect 68194 702300 73194 704800
+rect 120194 702300 125194 704800
+rect 165594 702300 170594 704800
+rect 170894 702300 173094 704800
+rect 173394 702300 175594 704800
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+rect 326794 702300 328994 704800
+rect 329294 702300 334294 704800
+rect 413394 702300 418394 704800
+rect 465394 702300 470394 704800
+rect 510594 702340 515394 704800
+rect 520594 702340 525394 704800
+rect -800 680242 1700 685242
+rect -800 643842 1660 648642
+rect 228210 644394 232594 702300
+rect 329978 656706 334294 702300
+rect 414038 661808 418176 702300
+rect 466154 666304 470314 702300
+rect 510594 702006 513054 702340
+rect 566594 702300 571594 704800
+rect 502048 699546 513054 702006
+rect 502048 675949 504508 699546
+rect 567072 691859 571475 702300
+rect 509988 688359 571475 691859
+rect 502026 675944 504512 675949
+rect 483166 675812 483970 675815
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+rect 582300 681627 584800 682984
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+rect 494639 666304 494910 669002
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+rect 495257 661808 495617 669214
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+rect 495257 660232 495617 660264
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+rect 329978 654774 496579 656706
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+rect 228210 640021 498362 644394
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+rect -800 633842 1660 638642
+rect -800 559442 1660 564242
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+rect 583520 589472 584800 589584
+rect 583520 588290 584800 588402
+rect 583520 587108 584800 587220
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+rect 575452 583054 575462 584022
+rect 576392 583674 576402 584022
+rect 576392 583562 584800 583674
+rect 576392 583054 576402 583562
+rect -800 549442 1660 554242
+rect 502416 550562 584800 555362
+rect 582340 540562 584800 545362
+rect -800 511530 480 511642
+rect -800 510348 480 510460
+rect -800 509166 480 509278
+rect -800 507984 480 508096
+rect -800 506802 480 506914
+rect -800 505620 480 505732
+rect 583520 500050 584800 500162
+rect 583520 498868 584800 498980
+rect 583520 497686 584800 497798
+rect 583520 496504 584800 496616
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+rect 578768 493816 578778 494618
+rect 579516 494252 579526 494618
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+rect -800 468308 480 468420
+rect -800 467126 480 467238
+rect -800 465944 480 466056
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+rect -800 463580 480 463692
+rect -800 462398 480 462510
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+rect 579274 449364 579284 450184
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+rect -800 423904 480 424016
+rect -800 422722 480 422834
+rect -800 421540 480 421652
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+rect 583520 411206 584800 411318
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+rect -800 381864 480 381976
+rect -800 380682 480 380794
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+rect -800 378318 480 378430
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+rect -800 375954 480 376066
+rect 583520 364784 584800 364896
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+rect 583520 361238 584800 361350
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+rect -800 338642 480 338754
+rect -800 337460 480 337572
+rect -800 336278 480 336390
+rect -800 335096 480 335208
+rect -800 333914 480 334026
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+rect 583520 319562 584800 319674
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+rect -800 290692 480 290804
+rect -800 289510 480 289622
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+rect -800 252398 480 252510
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+rect -800 250034 480 250146
+rect -800 248852 480 248964
+rect -800 247670 480 247782
+rect -800 246488 480 246600
+rect 582340 235230 584800 240030
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+rect -800 214888 1660 219688
+rect -800 204888 1660 209688
+rect 582340 191430 584800 196230
+rect 582340 181430 584800 186230
+rect -800 172888 1660 177688
+rect -800 162888 1660 167688
+rect 582340 146830 584800 151630
+rect 582340 136830 584800 141630
+rect -800 124776 480 124888
+rect -800 123594 480 123706
+rect -800 122412 480 122524
+rect -800 121230 480 121342
+rect -800 120048 480 120160
+rect -800 118866 480 118978
+rect 583520 95118 584800 95230
+rect 583520 93936 584800 94048
+rect 583520 92754 584800 92866
+rect 583520 91572 584800 91684
+rect -800 81554 480 81666
+rect -800 80372 480 80484
+rect -800 79190 480 79302
+rect -800 78008 480 78120
+rect -800 76826 480 76938
+rect -800 75644 480 75756
+rect 583520 50460 584800 50572
+rect 583520 49278 584800 49390
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+rect -800 38332 480 38444
+rect -800 37150 480 37262
+rect -800 35968 480 36080
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+rect -800 33604 480 33716
+rect -800 32422 480 32534
+rect 583520 24002 584800 24114
+rect 583520 22820 584800 22932
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+rect -800 15728 480 15840
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+rect -800 14546 480 14658
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+rect -800 13364 480 13476
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+rect -800 12182 480 12294
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+rect -800 11000 480 11112
+rect 583520 11000 584800 11112
+rect -800 9818 480 9930
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+rect -800 8636 480 8748
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+rect -800 7454 480 7566
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+rect -800 3908 480 4020
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+rect -800 2726 480 2838
+rect 583520 2726 584800 2838
+rect -800 1544 480 1656
+rect 583520 1544 584800 1656
+<< via3 >>
+rect 483176 675810 483956 675812
+rect 483176 675530 483956 675810
+rect 483176 675516 483956 675530
+rect 486634 672642 487384 672906
+rect 489910 669880 490702 670160
+rect 575462 583054 576392 584022
+rect 578778 493816 579516 494618
+rect 579284 449364 580126 450184
+<< metal4 >>
+rect 483175 675812 483957 675813
+rect 483175 675516 483176 675812
+rect 483956 675516 483957 675812
+rect 483175 675515 483957 675516
+rect 483176 450159 483946 675515
+rect 486633 672906 487385 672907
+rect 486633 672642 486634 672906
+rect 487384 672642 487385 672906
+rect 486633 672641 487385 672642
+rect 486634 494572 487346 672641
+rect 489882 670160 490744 670198
+rect 489882 669880 489910 670160
+rect 490702 669880 490744 670160
+rect 489882 583963 490744 669880
+rect 575461 584022 576393 584023
+rect 575461 583963 575462 584022
+rect 489882 583101 575462 583963
+rect 575461 583054 575462 583101
+rect 576392 583054 576393 584022
+rect 575461 583053 576393 583054
+rect 578777 494618 579517 494619
+rect 578777 494572 578778 494618
+rect 486634 493860 578778 494572
+rect 578777 493816 578778 493860
+rect 579516 493816 579517 494618
+rect 578777 493815 579517 493816
+rect 579283 450184 580127 450185
+rect 579283 450159 579284 450184
+rect 483176 449389 579284 450159
+rect 579283 449364 579284 449389
+rect 580126 449364 580127 450184
+rect 579283 449363 580127 449364
+<< comment >>
+rect -100 704000 584100 704100
+rect -100 0 0 704000
+rect 584000 0 584100 704000
+rect -100 -100 584100 0
+use neuron_s neuron_s_0
+timestamp 1628080429
+transform 1 0 497290 0 -1 674534
+box -6200 -3042 13048 5990
+<< labels >>
+flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -800 381864 480 381976 0 FreeSans 1120 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -800 338642 480 338754 0 FreeSans 1120 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -800 295420 480 295532 0 FreeSans 1120 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -800 252398 480 252510 0 FreeSans 1120 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -800 124776 480 124888 0 FreeSans 1120 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -800 81554 480 81666 0 FreeSans 1120 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -800 38332 480 38444 0 FreeSans 1120 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -800 16910 480 17022 0 FreeSans 1120 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 583520 313652 584800 313764 0 FreeSans 1120 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 583520 358874 584800 358986 0 FreeSans 1120 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 583520 405296 584800 405408 0 FreeSans 1120 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 583520 449718 584800 449830 0 FreeSans 1120 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 583520 494140 584800 494252 0 FreeSans 1120 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 583520 583562 584800 583674 0 FreeSans 1120 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -800 511530 480 511642 0 FreeSans 1120 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -800 468308 480 468420 0 FreeSans 1120 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -800 425086 480 425198 0 FreeSans 1120 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 583520 270412 584800 270524 0 FreeSans 1120 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -800 380682 480 380794 0 FreeSans 1120 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -800 337460 480 337572 0 FreeSans 1120 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -800 294238 480 294350 0 FreeSans 1120 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -800 251216 480 251328 0 FreeSans 1120 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -800 123594 480 123706 0 FreeSans 1120 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -800 80372 480 80484 0 FreeSans 1120 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -800 37150 480 37262 0 FreeSans 1120 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -800 15728 480 15840 0 FreeSans 1120 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 583520 314834 584800 314946 0 FreeSans 1120 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 583520 360056 584800 360168 0 FreeSans 1120 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 583520 406478 584800 406590 0 FreeSans 1120 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 583520 450900 584800 451012 0 FreeSans 1120 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 583520 495322 584800 495434 0 FreeSans 1120 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 583520 584744 584800 584856 0 FreeSans 1120 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -800 510348 480 510460 0 FreeSans 1120 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -800 467126 480 467238 0 FreeSans 1120 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -800 423904 480 424016 0 FreeSans 1120 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 582300 677984 584800 682984 0 FreeSans 1120 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 680242 1700 685242 0 FreeSans 1120 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 566594 702300 571594 704800 0 FreeSans 1920 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 465394 702300 470394 704800 0 FreeSans 1920 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 413394 702300 418394 704800 0 FreeSans 1920 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 120194 702300 125194 704800 0 FreeSans 1920 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 68194 702300 73194 704800 0 FreeSans 1920 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 16194 702300 21194 704800 0 FreeSans 1920 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal3 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 326794 702300 328994 704800 0 FreeSans 1920 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 225094 702300 227294 704800 0 FreeSans 1920 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 173394 702300 175594 704800 0 FreeSans 1920 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 324294 702300 326494 704800 0 FreeSans 1920 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 222594 702300 224794 704800 0 FreeSans 1920 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 170894 702300 173094 704800 0 FreeSans 1920 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 583520 2726 584800 2838 0 FreeSans 1120 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 583520 408842 584800 408954 0 FreeSans 1120 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 583520 453264 584800 453376 0 FreeSans 1120 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 583520 497686 584800 497798 0 FreeSans 1120 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 583520 587108 584800 587220 0 FreeSans 1120 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -800 507984 480 508096 0 FreeSans 1120 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -800 464762 480 464874 0 FreeSans 1120 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -800 421540 480 421652 0 FreeSans 1120 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -800 378318 480 378430 0 FreeSans 1120 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -800 335096 480 335208 0 FreeSans 1120 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -800 291874 480 291986 0 FreeSans 1120 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 583520 7454 584800 7566 0 FreeSans 1120 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -800 248852 480 248964 0 FreeSans 1120 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -800 121230 480 121342 0 FreeSans 1120 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -800 78008 480 78120 0 FreeSans 1120 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -800 34786 480 34898 0 FreeSans 1120 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -800 13364 480 13476 0 FreeSans 1120 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -800 8636 480 8748 0 FreeSans 1120 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -800 3908 480 4020 0 FreeSans 1120 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 583520 12182 584800 12294 0 FreeSans 1120 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 583520 16910 584800 17022 0 FreeSans 1120 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 583520 21638 584800 21750 0 FreeSans 1120 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 583520 48096 584800 48208 0 FreeSans 1120 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 583520 92754 584800 92866 0 FreeSans 1120 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 583520 272776 584800 272888 0 FreeSans 1120 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 583520 317198 584800 317310 0 FreeSans 1120 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 583520 362420 584800 362532 0 FreeSans 1120 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 583520 1544 584800 1656 0 FreeSans 1120 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 583520 407660 584800 407772 0 FreeSans 1120 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 583520 452082 584800 452194 0 FreeSans 1120 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 583520 496504 584800 496616 0 FreeSans 1120 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 583520 585926 584800 586038 0 FreeSans 1120 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -800 509166 480 509278 0 FreeSans 1120 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -800 465944 480 466056 0 FreeSans 1120 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -800 422722 480 422834 0 FreeSans 1120 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -800 379500 480 379612 0 FreeSans 1120 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -800 336278 480 336390 0 FreeSans 1120 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -800 293056 480 293168 0 FreeSans 1120 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 583520 6272 584800 6384 0 FreeSans 1120 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -800 250034 480 250146 0 FreeSans 1120 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -800 122412 480 122524 0 FreeSans 1120 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -800 79190 480 79302 0 FreeSans 1120 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -800 35968 480 36080 0 FreeSans 1120 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -800 14546 480 14658 0 FreeSans 1120 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -800 9818 480 9930 0 FreeSans 1120 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -800 5090 480 5202 0 FreeSans 1120 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 583520 11000 584800 11112 0 FreeSans 1120 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 583520 15728 584800 15840 0 FreeSans 1120 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 583520 20456 584800 20568 0 FreeSans 1120 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 583520 46914 584800 47026 0 FreeSans 1120 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 583520 91572 584800 91684 0 FreeSans 1120 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 583520 271594 584800 271706 0 FreeSans 1120 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 583520 316016 584800 316128 0 FreeSans 1120 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 583520 361238 584800 361350 0 FreeSans 1120 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 583520 5090 584800 5202 0 FreeSans 1120 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 583520 411206 584800 411318 0 FreeSans 1120 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 583520 455628 584800 455740 0 FreeSans 1120 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 583520 500050 584800 500162 0 FreeSans 1120 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 583520 589472 584800 589584 0 FreeSans 1120 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -800 505620 480 505732 0 FreeSans 1120 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -800 462398 480 462510 0 FreeSans 1120 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -800 419176 480 419288 0 FreeSans 1120 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -800 375954 480 376066 0 FreeSans 1120 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -800 332732 480 332844 0 FreeSans 1120 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -800 289510 480 289622 0 FreeSans 1120 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 583520 9818 584800 9930 0 FreeSans 1120 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -800 246488 480 246600 0 FreeSans 1120 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -800 118866 480 118978 0 FreeSans 1120 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -800 75644 480 75756 0 FreeSans 1120 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -800 32422 480 32534 0 FreeSans 1120 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -800 11000 480 11112 0 FreeSans 1120 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -800 6272 480 6384 0 FreeSans 1120 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -800 1544 480 1656 0 FreeSans 1120 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 583520 14546 584800 14658 0 FreeSans 1120 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 583520 19274 584800 19386 0 FreeSans 1120 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 583520 24002 584800 24114 0 FreeSans 1120 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 583520 50460 584800 50572 0 FreeSans 1120 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 583520 95118 584800 95230 0 FreeSans 1120 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 583520 275140 584800 275252 0 FreeSans 1120 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 583520 319562 584800 319674 0 FreeSans 1120 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 583520 364784 584800 364896 0 FreeSans 1120 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 583520 3908 584800 4020 0 FreeSans 1120 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 583520 410024 584800 410136 0 FreeSans 1120 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 583520 454446 584800 454558 0 FreeSans 1120 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 583520 498868 584800 498980 0 FreeSans 1120 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 583520 588290 584800 588402 0 FreeSans 1120 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -800 506802 480 506914 0 FreeSans 1120 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -800 463580 480 463692 0 FreeSans 1120 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -800 420358 480 420470 0 FreeSans 1120 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -800 377136 480 377248 0 FreeSans 1120 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -800 333914 480 334026 0 FreeSans 1120 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -800 290692 480 290804 0 FreeSans 1120 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 583520 8636 584800 8748 0 FreeSans 1120 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -800 247670 480 247782 0 FreeSans 1120 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -800 120048 480 120160 0 FreeSans 1120 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -800 76826 480 76938 0 FreeSans 1120 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -800 33604 480 33716 0 FreeSans 1120 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -800 12182 480 12294 0 FreeSans 1120 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -800 7454 480 7566 0 FreeSans 1120 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -800 2726 480 2838 0 FreeSans 1120 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 583520 13364 584800 13476 0 FreeSans 1120 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 583520 18092 584800 18204 0 FreeSans 1120 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 583520 22820 584800 22932 0 FreeSans 1120 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 583520 49278 584800 49390 0 FreeSans 1120 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 583520 93936 584800 94048 0 FreeSans 1120 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 583520 273958 584800 274070 0 FreeSans 1120 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 583520 318380 584800 318492 0 FreeSans 1120 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 583520 363602 584800 363714 0 FreeSans 1120 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 125816 -800 125928 480 0 FreeSans 1120 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 480416 -800 480528 480 0 FreeSans 1120 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 483962 -800 484074 480 0 FreeSans 1120 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 487508 -800 487620 480 0 FreeSans 1120 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 491054 -800 491166 480 0 FreeSans 1120 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 494600 -800 494712 480 0 FreeSans 1120 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 498146 -800 498258 480 0 FreeSans 1120 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 501692 -800 501804 480 0 FreeSans 1120 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 505238 -800 505350 480 0 FreeSans 1120 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 508784 -800 508896 480 0 FreeSans 1120 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 512330 -800 512442 480 0 FreeSans 1120 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 161276 -800 161388 480 0 FreeSans 1120 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 515876 -800 515988 480 0 FreeSans 1120 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 519422 -800 519534 480 0 FreeSans 1120 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 522968 -800 523080 480 0 FreeSans 1120 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 526514 -800 526626 480 0 FreeSans 1120 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 530060 -800 530172 480 0 FreeSans 1120 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 533606 -800 533718 480 0 FreeSans 1120 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 537152 -800 537264 480 0 FreeSans 1120 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 540698 -800 540810 480 0 FreeSans 1120 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 544244 -800 544356 480 0 FreeSans 1120 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 547790 -800 547902 480 0 FreeSans 1120 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 164822 -800 164934 480 0 FreeSans 1120 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 551336 -800 551448 480 0 FreeSans 1120 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 554882 -800 554994 480 0 FreeSans 1120 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 558428 -800 558540 480 0 FreeSans 1120 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 561974 -800 562086 480 0 FreeSans 1120 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 565520 -800 565632 480 0 FreeSans 1120 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 569066 -800 569178 480 0 FreeSans 1120 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 572612 -800 572724 480 0 FreeSans 1120 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 576158 -800 576270 480 0 FreeSans 1120 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 168368 -800 168480 480 0 FreeSans 1120 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 171914 -800 172026 480 0 FreeSans 1120 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 175460 -800 175572 480 0 FreeSans 1120 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 179006 -800 179118 480 0 FreeSans 1120 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 182552 -800 182664 480 0 FreeSans 1120 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 186098 -800 186210 480 0 FreeSans 1120 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 189644 -800 189756 480 0 FreeSans 1120 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 193190 -800 193302 480 0 FreeSans 1120 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 129362 -800 129474 480 0 FreeSans 1120 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 196736 -800 196848 480 0 FreeSans 1120 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 200282 -800 200394 480 0 FreeSans 1120 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 203828 -800 203940 480 0 FreeSans 1120 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 207374 -800 207486 480 0 FreeSans 1120 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 210920 -800 211032 480 0 FreeSans 1120 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 214466 -800 214578 480 0 FreeSans 1120 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 218012 -800 218124 480 0 FreeSans 1120 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 221558 -800 221670 480 0 FreeSans 1120 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 225104 -800 225216 480 0 FreeSans 1120 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 228650 -800 228762 480 0 FreeSans 1120 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 132908 -800 133020 480 0 FreeSans 1120 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 232196 -800 232308 480 0 FreeSans 1120 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 235742 -800 235854 480 0 FreeSans 1120 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 239288 -800 239400 480 0 FreeSans 1120 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 242834 -800 242946 480 0 FreeSans 1120 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 246380 -800 246492 480 0 FreeSans 1120 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 249926 -800 250038 480 0 FreeSans 1120 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 253472 -800 253584 480 0 FreeSans 1120 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 257018 -800 257130 480 0 FreeSans 1120 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 260564 -800 260676 480 0 FreeSans 1120 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 264110 -800 264222 480 0 FreeSans 1120 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 136454 -800 136566 480 0 FreeSans 1120 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 267656 -800 267768 480 0 FreeSans 1120 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 271202 -800 271314 480 0 FreeSans 1120 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 274748 -800 274860 480 0 FreeSans 1120 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 278294 -800 278406 480 0 FreeSans 1120 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 281840 -800 281952 480 0 FreeSans 1120 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 285386 -800 285498 480 0 FreeSans 1120 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 288932 -800 289044 480 0 FreeSans 1120 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 292478 -800 292590 480 0 FreeSans 1120 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 296024 -800 296136 480 0 FreeSans 1120 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 299570 -800 299682 480 0 FreeSans 1120 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 140000 -800 140112 480 0 FreeSans 1120 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 303116 -800 303228 480 0 FreeSans 1120 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 306662 -800 306774 480 0 FreeSans 1120 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 310208 -800 310320 480 0 FreeSans 1120 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 313754 -800 313866 480 0 FreeSans 1120 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 317300 -800 317412 480 0 FreeSans 1120 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 320846 -800 320958 480 0 FreeSans 1120 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 324392 -800 324504 480 0 FreeSans 1120 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 327938 -800 328050 480 0 FreeSans 1120 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 331484 -800 331596 480 0 FreeSans 1120 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 335030 -800 335142 480 0 FreeSans 1120 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 143546 -800 143658 480 0 FreeSans 1120 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 338576 -800 338688 480 0 FreeSans 1120 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 342122 -800 342234 480 0 FreeSans 1120 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 345668 -800 345780 480 0 FreeSans 1120 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 349214 -800 349326 480 0 FreeSans 1120 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 352760 -800 352872 480 0 FreeSans 1120 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 356306 -800 356418 480 0 FreeSans 1120 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 359852 -800 359964 480 0 FreeSans 1120 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 363398 -800 363510 480 0 FreeSans 1120 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 366944 -800 367056 480 0 FreeSans 1120 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 370490 -800 370602 480 0 FreeSans 1120 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 147092 -800 147204 480 0 FreeSans 1120 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 374036 -800 374148 480 0 FreeSans 1120 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 377582 -800 377694 480 0 FreeSans 1120 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 381128 -800 381240 480 0 FreeSans 1120 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 384674 -800 384786 480 0 FreeSans 1120 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 388220 -800 388332 480 0 FreeSans 1120 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 391766 -800 391878 480 0 FreeSans 1120 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 395312 -800 395424 480 0 FreeSans 1120 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 398858 -800 398970 480 0 FreeSans 1120 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 402404 -800 402516 480 0 FreeSans 1120 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 405950 -800 406062 480 0 FreeSans 1120 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 150638 -800 150750 480 0 FreeSans 1120 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 409496 -800 409608 480 0 FreeSans 1120 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 413042 -800 413154 480 0 FreeSans 1120 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 416588 -800 416700 480 0 FreeSans 1120 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 420134 -800 420246 480 0 FreeSans 1120 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 423680 -800 423792 480 0 FreeSans 1120 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 427226 -800 427338 480 0 FreeSans 1120 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 430772 -800 430884 480 0 FreeSans 1120 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 434318 -800 434430 480 0 FreeSans 1120 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 437864 -800 437976 480 0 FreeSans 1120 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 441410 -800 441522 480 0 FreeSans 1120 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 154184 -800 154296 480 0 FreeSans 1120 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 444956 -800 445068 480 0 FreeSans 1120 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 448502 -800 448614 480 0 FreeSans 1120 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 452048 -800 452160 480 0 FreeSans 1120 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 455594 -800 455706 480 0 FreeSans 1120 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 459140 -800 459252 480 0 FreeSans 1120 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 462686 -800 462798 480 0 FreeSans 1120 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 466232 -800 466344 480 0 FreeSans 1120 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 469778 -800 469890 480 0 FreeSans 1120 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 473324 -800 473436 480 0 FreeSans 1120 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 476870 -800 476982 480 0 FreeSans 1120 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 157730 -800 157842 480 0 FreeSans 1120 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 126998 -800 127110 480 0 FreeSans 1120 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 481598 -800 481710 480 0 FreeSans 1120 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 485144 -800 485256 480 0 FreeSans 1120 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 488690 -800 488802 480 0 FreeSans 1120 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 492236 -800 492348 480 0 FreeSans 1120 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 495782 -800 495894 480 0 FreeSans 1120 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 499328 -800 499440 480 0 FreeSans 1120 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 502874 -800 502986 480 0 FreeSans 1120 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 506420 -800 506532 480 0 FreeSans 1120 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 509966 -800 510078 480 0 FreeSans 1120 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 513512 -800 513624 480 0 FreeSans 1120 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 162458 -800 162570 480 0 FreeSans 1120 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 517058 -800 517170 480 0 FreeSans 1120 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 520604 -800 520716 480 0 FreeSans 1120 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 524150 -800 524262 480 0 FreeSans 1120 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 527696 -800 527808 480 0 FreeSans 1120 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 531242 -800 531354 480 0 FreeSans 1120 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 534788 -800 534900 480 0 FreeSans 1120 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 538334 -800 538446 480 0 FreeSans 1120 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 541880 -800 541992 480 0 FreeSans 1120 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 545426 -800 545538 480 0 FreeSans 1120 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 548972 -800 549084 480 0 FreeSans 1120 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 166004 -800 166116 480 0 FreeSans 1120 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 552518 -800 552630 480 0 FreeSans 1120 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 556064 -800 556176 480 0 FreeSans 1120 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 559610 -800 559722 480 0 FreeSans 1120 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 563156 -800 563268 480 0 FreeSans 1120 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 566702 -800 566814 480 0 FreeSans 1120 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 570248 -800 570360 480 0 FreeSans 1120 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 573794 -800 573906 480 0 FreeSans 1120 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 577340 -800 577452 480 0 FreeSans 1120 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 169550 -800 169662 480 0 FreeSans 1120 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 173096 -800 173208 480 0 FreeSans 1120 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 176642 -800 176754 480 0 FreeSans 1120 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 180188 -800 180300 480 0 FreeSans 1120 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 183734 -800 183846 480 0 FreeSans 1120 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 187280 -800 187392 480 0 FreeSans 1120 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 190826 -800 190938 480 0 FreeSans 1120 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 194372 -800 194484 480 0 FreeSans 1120 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 130544 -800 130656 480 0 FreeSans 1120 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 197918 -800 198030 480 0 FreeSans 1120 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 201464 -800 201576 480 0 FreeSans 1120 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 205010 -800 205122 480 0 FreeSans 1120 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 208556 -800 208668 480 0 FreeSans 1120 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 212102 -800 212214 480 0 FreeSans 1120 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 215648 -800 215760 480 0 FreeSans 1120 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 219194 -800 219306 480 0 FreeSans 1120 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 222740 -800 222852 480 0 FreeSans 1120 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 226286 -800 226398 480 0 FreeSans 1120 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 229832 -800 229944 480 0 FreeSans 1120 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 134090 -800 134202 480 0 FreeSans 1120 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 233378 -800 233490 480 0 FreeSans 1120 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 236924 -800 237036 480 0 FreeSans 1120 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 240470 -800 240582 480 0 FreeSans 1120 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 244016 -800 244128 480 0 FreeSans 1120 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 247562 -800 247674 480 0 FreeSans 1120 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 251108 -800 251220 480 0 FreeSans 1120 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 254654 -800 254766 480 0 FreeSans 1120 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 258200 -800 258312 480 0 FreeSans 1120 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 261746 -800 261858 480 0 FreeSans 1120 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 265292 -800 265404 480 0 FreeSans 1120 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 137636 -800 137748 480 0 FreeSans 1120 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 268838 -800 268950 480 0 FreeSans 1120 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 272384 -800 272496 480 0 FreeSans 1120 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 275930 -800 276042 480 0 FreeSans 1120 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 279476 -800 279588 480 0 FreeSans 1120 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 283022 -800 283134 480 0 FreeSans 1120 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 286568 -800 286680 480 0 FreeSans 1120 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 290114 -800 290226 480 0 FreeSans 1120 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 293660 -800 293772 480 0 FreeSans 1120 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 297206 -800 297318 480 0 FreeSans 1120 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 300752 -800 300864 480 0 FreeSans 1120 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 141182 -800 141294 480 0 FreeSans 1120 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 304298 -800 304410 480 0 FreeSans 1120 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 307844 -800 307956 480 0 FreeSans 1120 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 311390 -800 311502 480 0 FreeSans 1120 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 314936 -800 315048 480 0 FreeSans 1120 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 318482 -800 318594 480 0 FreeSans 1120 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 322028 -800 322140 480 0 FreeSans 1120 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 325574 -800 325686 480 0 FreeSans 1120 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 329120 -800 329232 480 0 FreeSans 1120 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 332666 -800 332778 480 0 FreeSans 1120 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 336212 -800 336324 480 0 FreeSans 1120 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 144728 -800 144840 480 0 FreeSans 1120 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 339758 -800 339870 480 0 FreeSans 1120 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 343304 -800 343416 480 0 FreeSans 1120 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 346850 -800 346962 480 0 FreeSans 1120 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 350396 -800 350508 480 0 FreeSans 1120 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 353942 -800 354054 480 0 FreeSans 1120 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 357488 -800 357600 480 0 FreeSans 1120 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 361034 -800 361146 480 0 FreeSans 1120 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 364580 -800 364692 480 0 FreeSans 1120 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 368126 -800 368238 480 0 FreeSans 1120 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 371672 -800 371784 480 0 FreeSans 1120 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 148274 -800 148386 480 0 FreeSans 1120 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 375218 -800 375330 480 0 FreeSans 1120 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 378764 -800 378876 480 0 FreeSans 1120 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 382310 -800 382422 480 0 FreeSans 1120 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 385856 -800 385968 480 0 FreeSans 1120 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 389402 -800 389514 480 0 FreeSans 1120 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 392948 -800 393060 480 0 FreeSans 1120 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 396494 -800 396606 480 0 FreeSans 1120 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 400040 -800 400152 480 0 FreeSans 1120 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 403586 -800 403698 480 0 FreeSans 1120 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 407132 -800 407244 480 0 FreeSans 1120 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 151820 -800 151932 480 0 FreeSans 1120 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 410678 -800 410790 480 0 FreeSans 1120 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 414224 -800 414336 480 0 FreeSans 1120 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 417770 -800 417882 480 0 FreeSans 1120 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 421316 -800 421428 480 0 FreeSans 1120 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 424862 -800 424974 480 0 FreeSans 1120 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 428408 -800 428520 480 0 FreeSans 1120 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 431954 -800 432066 480 0 FreeSans 1120 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 435500 -800 435612 480 0 FreeSans 1120 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 439046 -800 439158 480 0 FreeSans 1120 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 442592 -800 442704 480 0 FreeSans 1120 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 155366 -800 155478 480 0 FreeSans 1120 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 446138 -800 446250 480 0 FreeSans 1120 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 449684 -800 449796 480 0 FreeSans 1120 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 453230 -800 453342 480 0 FreeSans 1120 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 456776 -800 456888 480 0 FreeSans 1120 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 460322 -800 460434 480 0 FreeSans 1120 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 463868 -800 463980 480 0 FreeSans 1120 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 467414 -800 467526 480 0 FreeSans 1120 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 470960 -800 471072 480 0 FreeSans 1120 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 474506 -800 474618 480 0 FreeSans 1120 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 478052 -800 478164 480 0 FreeSans 1120 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 158912 -800 159024 480 0 FreeSans 1120 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 128180 -800 128292 480 0 FreeSans 1120 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 482780 -800 482892 480 0 FreeSans 1120 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 486326 -800 486438 480 0 FreeSans 1120 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 489872 -800 489984 480 0 FreeSans 1120 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 493418 -800 493530 480 0 FreeSans 1120 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 496964 -800 497076 480 0 FreeSans 1120 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 500510 -800 500622 480 0 FreeSans 1120 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 504056 -800 504168 480 0 FreeSans 1120 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 507602 -800 507714 480 0 FreeSans 1120 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 511148 -800 511260 480 0 FreeSans 1120 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 514694 -800 514806 480 0 FreeSans 1120 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 163640 -800 163752 480 0 FreeSans 1120 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 518240 -800 518352 480 0 FreeSans 1120 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 521786 -800 521898 480 0 FreeSans 1120 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 525332 -800 525444 480 0 FreeSans 1120 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 528878 -800 528990 480 0 FreeSans 1120 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 532424 -800 532536 480 0 FreeSans 1120 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 535970 -800 536082 480 0 FreeSans 1120 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 539516 -800 539628 480 0 FreeSans 1120 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 543062 -800 543174 480 0 FreeSans 1120 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 546608 -800 546720 480 0 FreeSans 1120 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 550154 -800 550266 480 0 FreeSans 1120 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 167186 -800 167298 480 0 FreeSans 1120 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 553700 -800 553812 480 0 FreeSans 1120 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 557246 -800 557358 480 0 FreeSans 1120 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 560792 -800 560904 480 0 FreeSans 1120 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 564338 -800 564450 480 0 FreeSans 1120 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 567884 -800 567996 480 0 FreeSans 1120 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 571430 -800 571542 480 0 FreeSans 1120 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 574976 -800 575088 480 0 FreeSans 1120 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 578522 -800 578634 480 0 FreeSans 1120 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 170732 -800 170844 480 0 FreeSans 1120 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 174278 -800 174390 480 0 FreeSans 1120 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 177824 -800 177936 480 0 FreeSans 1120 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 181370 -800 181482 480 0 FreeSans 1120 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 184916 -800 185028 480 0 FreeSans 1120 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 188462 -800 188574 480 0 FreeSans 1120 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 192008 -800 192120 480 0 FreeSans 1120 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 195554 -800 195666 480 0 FreeSans 1120 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 131726 -800 131838 480 0 FreeSans 1120 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 199100 -800 199212 480 0 FreeSans 1120 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 202646 -800 202758 480 0 FreeSans 1120 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 206192 -800 206304 480 0 FreeSans 1120 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 209738 -800 209850 480 0 FreeSans 1120 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 213284 -800 213396 480 0 FreeSans 1120 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 216830 -800 216942 480 0 FreeSans 1120 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 220376 -800 220488 480 0 FreeSans 1120 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 223922 -800 224034 480 0 FreeSans 1120 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 227468 -800 227580 480 0 FreeSans 1120 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 231014 -800 231126 480 0 FreeSans 1120 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 135272 -800 135384 480 0 FreeSans 1120 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 234560 -800 234672 480 0 FreeSans 1120 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 238106 -800 238218 480 0 FreeSans 1120 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 241652 -800 241764 480 0 FreeSans 1120 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 245198 -800 245310 480 0 FreeSans 1120 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 248744 -800 248856 480 0 FreeSans 1120 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 252290 -800 252402 480 0 FreeSans 1120 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 255836 -800 255948 480 0 FreeSans 1120 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 259382 -800 259494 480 0 FreeSans 1120 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 262928 -800 263040 480 0 FreeSans 1120 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 266474 -800 266586 480 0 FreeSans 1120 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 138818 -800 138930 480 0 FreeSans 1120 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 270020 -800 270132 480 0 FreeSans 1120 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 273566 -800 273678 480 0 FreeSans 1120 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 277112 -800 277224 480 0 FreeSans 1120 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 280658 -800 280770 480 0 FreeSans 1120 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 284204 -800 284316 480 0 FreeSans 1120 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 287750 -800 287862 480 0 FreeSans 1120 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 291296 -800 291408 480 0 FreeSans 1120 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 294842 -800 294954 480 0 FreeSans 1120 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 298388 -800 298500 480 0 FreeSans 1120 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 301934 -800 302046 480 0 FreeSans 1120 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 142364 -800 142476 480 0 FreeSans 1120 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 305480 -800 305592 480 0 FreeSans 1120 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 309026 -800 309138 480 0 FreeSans 1120 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 312572 -800 312684 480 0 FreeSans 1120 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 316118 -800 316230 480 0 FreeSans 1120 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 319664 -800 319776 480 0 FreeSans 1120 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 323210 -800 323322 480 0 FreeSans 1120 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 326756 -800 326868 480 0 FreeSans 1120 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 330302 -800 330414 480 0 FreeSans 1120 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 333848 -800 333960 480 0 FreeSans 1120 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 337394 -800 337506 480 0 FreeSans 1120 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 145910 -800 146022 480 0 FreeSans 1120 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 340940 -800 341052 480 0 FreeSans 1120 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 344486 -800 344598 480 0 FreeSans 1120 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 348032 -800 348144 480 0 FreeSans 1120 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 351578 -800 351690 480 0 FreeSans 1120 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 355124 -800 355236 480 0 FreeSans 1120 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 358670 -800 358782 480 0 FreeSans 1120 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 362216 -800 362328 480 0 FreeSans 1120 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 365762 -800 365874 480 0 FreeSans 1120 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 369308 -800 369420 480 0 FreeSans 1120 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 372854 -800 372966 480 0 FreeSans 1120 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 149456 -800 149568 480 0 FreeSans 1120 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 376400 -800 376512 480 0 FreeSans 1120 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 379946 -800 380058 480 0 FreeSans 1120 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 383492 -800 383604 480 0 FreeSans 1120 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 387038 -800 387150 480 0 FreeSans 1120 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 390584 -800 390696 480 0 FreeSans 1120 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 394130 -800 394242 480 0 FreeSans 1120 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 397676 -800 397788 480 0 FreeSans 1120 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 401222 -800 401334 480 0 FreeSans 1120 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 404768 -800 404880 480 0 FreeSans 1120 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 408314 -800 408426 480 0 FreeSans 1120 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 153002 -800 153114 480 0 FreeSans 1120 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 411860 -800 411972 480 0 FreeSans 1120 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 415406 -800 415518 480 0 FreeSans 1120 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 418952 -800 419064 480 0 FreeSans 1120 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 422498 -800 422610 480 0 FreeSans 1120 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 426044 -800 426156 480 0 FreeSans 1120 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 429590 -800 429702 480 0 FreeSans 1120 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 433136 -800 433248 480 0 FreeSans 1120 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 436682 -800 436794 480 0 FreeSans 1120 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 440228 -800 440340 480 0 FreeSans 1120 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 443774 -800 443886 480 0 FreeSans 1120 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 156548 -800 156660 480 0 FreeSans 1120 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 447320 -800 447432 480 0 FreeSans 1120 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 450866 -800 450978 480 0 FreeSans 1120 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 454412 -800 454524 480 0 FreeSans 1120 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 457958 -800 458070 480 0 FreeSans 1120 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 461504 -800 461616 480 0 FreeSans 1120 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 465050 -800 465162 480 0 FreeSans 1120 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 468596 -800 468708 480 0 FreeSans 1120 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 472142 -800 472254 480 0 FreeSans 1120 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 475688 -800 475800 480 0 FreeSans 1120 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 479234 -800 479346 480 0 FreeSans 1120 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 160094 -800 160206 480 0 FreeSans 1120 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 579704 -800 579816 480 0 FreeSans 1120 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 580886 -800 580998 480 0 FreeSans 1120 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 582068 -800 582180 480 0 FreeSans 1120 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 583250 -800 583362 480 0 FreeSans 1120 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 582340 639784 584800 644584 0 FreeSans 1120 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 582340 629784 584800 634584 0 FreeSans 1120 0 0 0 vccd1
+port 553 nsew signal bidirectional
+flabel metal3 s 0 643842 1660 648642 0 FreeSans 1120 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 633842 1660 638642 0 FreeSans 1120 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 582340 540562 584800 545362 0 FreeSans 1120 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 582340 550562 584800 555362 0 FreeSans 1120 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 582340 235230 584800 240030 0 FreeSans 1120 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 582340 225230 584800 230030 0 FreeSans 1120 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 204888 1660 209688 0 FreeSans 1120 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 214888 1660 219688 0 FreeSans 1120 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 520594 702340 525394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 510594 702340 515394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 582340 146830 584800 151630 0 FreeSans 1120 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 582340 136830 584800 141630 0 FreeSans 1120 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 559442 1660 564242 0 FreeSans 1120 0 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 0 549442 1660 554242 0 FreeSans 1120 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 582340 191430 584800 196230 0 FreeSans 1120 0 0 0 vssd1
+port 568 nsew signal bidirectional
+flabel metal3 s 582340 181430 584800 186230 0 FreeSans 1120 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 0 172888 1660 177688 0 FreeSans 1120 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 162888 1660 167688 0 FreeSans 1120 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 524 -800 636 480 0 FreeSans 1120 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 1706 -800 1818 480 0 FreeSans 1120 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 2888 -800 3000 480 0 FreeSans 1120 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 7616 -800 7728 480 0 FreeSans 1120 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 47804 -800 47916 480 0 FreeSans 1120 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 51350 -800 51462 480 0 FreeSans 1120 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 54896 -800 55008 480 0 FreeSans 1120 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 58442 -800 58554 480 0 FreeSans 1120 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 61988 -800 62100 480 0 FreeSans 1120 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 65534 -800 65646 480 0 FreeSans 1120 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 69080 -800 69192 480 0 FreeSans 1120 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 72626 -800 72738 480 0 FreeSans 1120 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 76172 -800 76284 480 0 FreeSans 1120 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 79718 -800 79830 480 0 FreeSans 1120 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 12344 -800 12456 480 0 FreeSans 1120 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 83264 -800 83376 480 0 FreeSans 1120 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 86810 -800 86922 480 0 FreeSans 1120 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 90356 -800 90468 480 0 FreeSans 1120 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 93902 -800 94014 480 0 FreeSans 1120 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 97448 -800 97560 480 0 FreeSans 1120 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 100994 -800 101106 480 0 FreeSans 1120 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 104540 -800 104652 480 0 FreeSans 1120 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 108086 -800 108198 480 0 FreeSans 1120 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 111632 -800 111744 480 0 FreeSans 1120 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 115178 -800 115290 480 0 FreeSans 1120 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 17072 -800 17184 480 0 FreeSans 1120 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 118724 -800 118836 480 0 FreeSans 1120 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 122270 -800 122382 480 0 FreeSans 1120 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 21800 -800 21912 480 0 FreeSans 1120 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 26528 -800 26640 480 0 FreeSans 1120 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 30074 -800 30186 480 0 FreeSans 1120 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 33620 -800 33732 480 0 FreeSans 1120 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 37166 -800 37278 480 0 FreeSans 1120 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 40712 -800 40824 480 0 FreeSans 1120 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 44258 -800 44370 480 0 FreeSans 1120 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 4070 -800 4182 480 0 FreeSans 1120 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 8798 -800 8910 480 0 FreeSans 1120 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 48986 -800 49098 480 0 FreeSans 1120 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 52532 -800 52644 480 0 FreeSans 1120 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 56078 -800 56190 480 0 FreeSans 1120 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 59624 -800 59736 480 0 FreeSans 1120 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 63170 -800 63282 480 0 FreeSans 1120 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 66716 -800 66828 480 0 FreeSans 1120 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 70262 -800 70374 480 0 FreeSans 1120 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 73808 -800 73920 480 0 FreeSans 1120 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 77354 -800 77466 480 0 FreeSans 1120 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 80900 -800 81012 480 0 FreeSans 1120 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 13526 -800 13638 480 0 FreeSans 1120 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 84446 -800 84558 480 0 FreeSans 1120 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 87992 -800 88104 480 0 FreeSans 1120 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 91538 -800 91650 480 0 FreeSans 1120 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 95084 -800 95196 480 0 FreeSans 1120 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 98630 -800 98742 480 0 FreeSans 1120 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 102176 -800 102288 480 0 FreeSans 1120 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 105722 -800 105834 480 0 FreeSans 1120 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 109268 -800 109380 480 0 FreeSans 1120 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 112814 -800 112926 480 0 FreeSans 1120 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 116360 -800 116472 480 0 FreeSans 1120 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 18254 -800 18366 480 0 FreeSans 1120 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 119906 -800 120018 480 0 FreeSans 1120 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 123452 -800 123564 480 0 FreeSans 1120 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 22982 -800 23094 480 0 FreeSans 1120 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 27710 -800 27822 480 0 FreeSans 1120 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 31256 -800 31368 480 0 FreeSans 1120 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 34802 -800 34914 480 0 FreeSans 1120 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 38348 -800 38460 480 0 FreeSans 1120 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 41894 -800 42006 480 0 FreeSans 1120 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 45440 -800 45552 480 0 FreeSans 1120 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 9980 -800 10092 480 0 FreeSans 1120 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 50168 -800 50280 480 0 FreeSans 1120 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 53714 -800 53826 480 0 FreeSans 1120 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 57260 -800 57372 480 0 FreeSans 1120 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 60806 -800 60918 480 0 FreeSans 1120 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
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+port 645 nsew signal tristate
+flabel metal2 s 67898 -800 68010 480 0 FreeSans 1120 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
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+port 647 nsew signal tristate
+flabel metal2 s 74990 -800 75102 480 0 FreeSans 1120 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 78536 -800 78648 480 0 FreeSans 1120 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 82082 -800 82194 480 0 FreeSans 1120 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 14708 -800 14820 480 0 FreeSans 1120 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 85628 -800 85740 480 0 FreeSans 1120 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 89174 -800 89286 480 0 FreeSans 1120 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
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+port 654 nsew signal tristate
+flabel metal2 s 96266 -800 96378 480 0 FreeSans 1120 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 99812 -800 99924 480 0 FreeSans 1120 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 103358 -800 103470 480 0 FreeSans 1120 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 106904 -800 107016 480 0 FreeSans 1120 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 110450 -800 110562 480 0 FreeSans 1120 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 113996 -800 114108 480 0 FreeSans 1120 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 117542 -800 117654 480 0 FreeSans 1120 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 19436 -800 19548 480 0 FreeSans 1120 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 121088 -800 121200 480 0 FreeSans 1120 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 124634 -800 124746 480 0 FreeSans 1120 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 24164 -800 24276 480 0 FreeSans 1120 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 28892 -800 29004 480 0 FreeSans 1120 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 32438 -800 32550 480 0 FreeSans 1120 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 35984 -800 36096 480 0 FreeSans 1120 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 39530 -800 39642 480 0 FreeSans 1120 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 43076 -800 43188 480 0 FreeSans 1120 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 46622 -800 46734 480 0 FreeSans 1120 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 11162 -800 11274 480 0 FreeSans 1120 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 15890 -800 16002 480 0 FreeSans 1120 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 20618 -800 20730 480 0 FreeSans 1120 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 25346 -800 25458 480 0 FreeSans 1120 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 5252 -800 5364 480 0 FreeSans 1120 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 6434 -800 6546 480 0 FreeSans 1120 90 0 0 wbs_we_i
+port 677 nsew signal input
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>
diff --git a/mag/user_analog_project_wrapper_empty.mag b/mag/user_analog_project_wrapper_empty.mag
new file mode 100644
index 0000000..053243c
--- /dev/null
+++ b/mag/user_analog_project_wrapper_empty.mag
@@ -0,0 +1,2053 @@
+magic
+tech sky130A
+timestamp 1620244087
+<< checkpaint >>
+rect -680 351370 292680 352680
+rect -680 630 630 351370
+rect 291370 630 292680 351370
+rect -680 -680 292680 630
+<< metal2 >>
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+<< metal3 >>
+rect 8097 351150 10597 352400
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+rect 291760 292372 292400 292428
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+rect -400 167548 240 167604
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+rect -400 166366 240 166422
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+rect -400 147710 240 147766
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+rect -400 146528 240 146584
+rect -400 145937 240 145993
+rect -400 145346 240 145402
+rect -400 144755 240 144811
+rect 291760 137570 292400 137626
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+rect -400 126199 240 126255
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+rect -400 125017 240 125073
+rect -400 124426 240 124482
+rect -400 123835 240 123891
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+rect 291170 117615 292400 120015
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+rect -400 107444 830 109844
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+rect -400 86444 830 88844
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+rect 291170 73415 292400 75815
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+rect -400 62388 240 62444
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+rect -400 60615 240 60671
+rect -400 60024 240 60080
+rect -400 59433 240 59489
+rect 291760 47559 292400 47615
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+rect -400 40777 240 40833
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+rect -400 39595 240 39651
+rect -400 39004 240 39060
+rect -400 38413 240 38469
+rect -400 37822 240 37878
+rect 291760 25230 292400 25286
+rect 291760 24639 292400 24695
+rect 291760 24048 292400 24104
+rect 291760 23457 292400 23513
+rect -400 19166 240 19222
+rect -400 18575 240 18631
+rect -400 17984 240 18040
+rect -400 17393 240 17449
+rect -400 16802 240 16858
+rect -400 16211 240 16267
+rect 291760 12001 292400 12057
+rect 291760 11410 292400 11466
+rect 291760 10819 292400 10875
+rect 291760 10228 292400 10284
+rect 291760 9637 292400 9693
+rect 291760 9046 292400 9102
+rect -400 8455 240 8511
+rect 291760 8455 292400 8511
+rect -400 7864 240 7920
+rect 291760 7864 292400 7920
+rect -400 7273 240 7329
+rect 291760 7273 292400 7329
+rect -400 6682 240 6738
+rect 291760 6682 292400 6738
+rect -400 6091 240 6147
+rect 291760 6091 292400 6147
+rect -400 5500 240 5556
+rect 291760 5500 292400 5556
+rect -400 4909 240 4965
+rect 291760 4909 292400 4965
+rect -400 4318 240 4374
+rect 291760 4318 292400 4374
+rect -400 3727 240 3783
+rect 291760 3727 292400 3783
+rect -400 3136 240 3192
+rect 291760 3136 292400 3192
+rect -400 2545 240 2601
+rect 291760 2545 292400 2601
+rect -400 1954 240 2010
+rect 291760 1954 292400 2010
+rect -400 1363 240 1419
+rect 291760 1363 292400 1419
+rect -400 772 240 828
+rect 291760 772 292400 828
+<< comment >>
+rect -50 352000 292050 352050
+rect -50 0 0 352000
+rect 292000 0 292050 352000
+rect -50 -50 292050 0
+<< labels >>
+flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -400 190932 240 190988 0 FreeSans 560 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -400 169321 240 169377 0 FreeSans 560 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -400 147710 240 147766 0 FreeSans 560 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -400 126199 240 126255 0 FreeSans 560 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -400 62388 240 62444 0 FreeSans 560 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -400 40777 240 40833 0 FreeSans 560 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -400 19166 240 19222 0 FreeSans 560 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -400 8455 240 8511 0 FreeSans 560 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 291760 156826 292400 156882 0 FreeSans 560 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 291760 179437 292400 179493 0 FreeSans 560 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 291760 202648 292400 202704 0 FreeSans 560 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 291760 224859 292400 224915 0 FreeSans 560 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 291760 247070 292400 247126 0 FreeSans 560 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 291760 291781 292400 291837 0 FreeSans 560 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -400 255765 240 255821 0 FreeSans 560 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -400 234154 240 234210 0 FreeSans 560 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -400 212543 240 212599 0 FreeSans 560 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 291760 135206 292400 135262 0 FreeSans 560 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -400 190341 240 190397 0 FreeSans 560 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -400 168730 240 168786 0 FreeSans 560 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -400 147119 240 147175 0 FreeSans 560 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -400 125608 240 125664 0 FreeSans 560 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -400 61797 240 61853 0 FreeSans 560 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -400 40186 240 40242 0 FreeSans 560 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -400 18575 240 18631 0 FreeSans 560 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -400 7864 240 7920 0 FreeSans 560 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 291760 157417 292400 157473 0 FreeSans 560 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 291760 180028 292400 180084 0 FreeSans 560 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 291760 203239 292400 203295 0 FreeSans 560 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 291760 225450 292400 225506 0 FreeSans 560 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 291760 247661 292400 247717 0 FreeSans 560 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 291760 292372 292400 292428 0 FreeSans 560 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -400 255174 240 255230 0 FreeSans 560 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -400 233563 240 233619 0 FreeSans 560 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -400 211952 240 212008 0 FreeSans 560 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 291150 338992 292400 341492 0 FreeSans 560 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 340121 850 342621 0 FreeSans 560 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 283297 351150 285797 352400 0 FreeSans 960 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 232697 351150 235197 352400 0 FreeSans 960 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 206697 351150 209197 352400 0 FreeSans 960 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 60097 351150 62597 352400 0 FreeSans 960 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 34097 351150 36597 352400 0 FreeSans 960 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 8097 351150 10597 352400 0 FreeSans 960 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal3 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 163397 351150 164497 352400 0 FreeSans 960 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 112547 351150 113647 352400 0 FreeSans 960 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 86697 351150 87797 352400 0 FreeSans 960 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 162147 351150 163247 352400 0 FreeSans 960 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 111297 351150 112397 352400 0 FreeSans 960 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 85447 351150 86547 352400 0 FreeSans 960 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 291760 1363 292400 1419 0 FreeSans 560 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 291760 204421 292400 204477 0 FreeSans 560 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 291760 226632 292400 226688 0 FreeSans 560 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 291760 248843 292400 248899 0 FreeSans 560 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 291760 293554 292400 293610 0 FreeSans 560 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -400 253992 240 254048 0 FreeSans 560 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -400 232381 240 232437 0 FreeSans 560 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -400 210770 240 210826 0 FreeSans 560 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -400 189159 240 189215 0 FreeSans 560 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -400 167548 240 167604 0 FreeSans 560 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -400 145937 240 145993 0 FreeSans 560 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 291760 3727 292400 3783 0 FreeSans 560 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -400 124426 240 124482 0 FreeSans 560 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -400 60615 240 60671 0 FreeSans 560 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -400 39004 240 39060 0 FreeSans 560 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -400 17393 240 17449 0 FreeSans 560 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -400 6682 240 6738 0 FreeSans 560 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -400 4318 240 4374 0 FreeSans 560 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -400 1954 240 2010 0 FreeSans 560 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 291760 6091 292400 6147 0 FreeSans 560 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 291760 8455 292400 8511 0 FreeSans 560 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 291760 10819 292400 10875 0 FreeSans 560 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 291760 24048 292400 24104 0 FreeSans 560 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 291760 46377 292400 46433 0 FreeSans 560 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 291760 136388 292400 136444 0 FreeSans 560 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 291760 158599 292400 158655 0 FreeSans 560 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 291760 181210 292400 181266 0 FreeSans 560 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 291760 772 292400 828 0 FreeSans 560 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 291760 203830 292400 203886 0 FreeSans 560 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 291760 226041 292400 226097 0 FreeSans 560 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 291760 248252 292400 248308 0 FreeSans 560 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 291760 292963 292400 293019 0 FreeSans 560 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -400 254583 240 254639 0 FreeSans 560 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -400 232972 240 233028 0 FreeSans 560 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -400 211361 240 211417 0 FreeSans 560 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -400 189750 240 189806 0 FreeSans 560 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -400 168139 240 168195 0 FreeSans 560 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -400 146528 240 146584 0 FreeSans 560 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 291760 3136 292400 3192 0 FreeSans 560 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -400 125017 240 125073 0 FreeSans 560 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -400 61206 240 61262 0 FreeSans 560 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -400 39595 240 39651 0 FreeSans 560 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -400 17984 240 18040 0 FreeSans 560 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -400 7273 240 7329 0 FreeSans 560 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -400 4909 240 4965 0 FreeSans 560 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -400 2545 240 2601 0 FreeSans 560 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 291760 5500 292400 5556 0 FreeSans 560 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 291760 7864 292400 7920 0 FreeSans 560 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 291760 10228 292400 10284 0 FreeSans 560 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 291760 23457 292400 23513 0 FreeSans 560 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 291760 45786 292400 45842 0 FreeSans 560 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 291760 135797 292400 135853 0 FreeSans 560 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 291760 158008 292400 158064 0 FreeSans 560 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 291760 180619 292400 180675 0 FreeSans 560 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 291760 2545 292400 2601 0 FreeSans 560 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 291760 205603 292400 205659 0 FreeSans 560 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 291760 227814 292400 227870 0 FreeSans 560 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 291760 250025 292400 250081 0 FreeSans 560 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 291760 294736 292400 294792 0 FreeSans 560 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -400 252810 240 252866 0 FreeSans 560 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -400 231199 240 231255 0 FreeSans 560 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -400 209588 240 209644 0 FreeSans 560 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -400 187977 240 188033 0 FreeSans 560 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -400 166366 240 166422 0 FreeSans 560 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -400 144755 240 144811 0 FreeSans 560 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 291760 4909 292400 4965 0 FreeSans 560 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -400 123244 240 123300 0 FreeSans 560 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -400 59433 240 59489 0 FreeSans 560 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -400 37822 240 37878 0 FreeSans 560 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -400 16211 240 16267 0 FreeSans 560 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -400 5500 240 5556 0 FreeSans 560 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -400 3136 240 3192 0 FreeSans 560 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -400 772 240 828 0 FreeSans 560 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 291760 7273 292400 7329 0 FreeSans 560 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 291760 9637 292400 9693 0 FreeSans 560 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 291760 12001 292400 12057 0 FreeSans 560 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 291760 25230 292400 25286 0 FreeSans 560 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 291760 47559 292400 47615 0 FreeSans 560 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 291760 137570 292400 137626 0 FreeSans 560 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 291760 159781 292400 159837 0 FreeSans 560 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 291760 182392 292400 182448 0 FreeSans 560 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 291760 1954 292400 2010 0 FreeSans 560 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 291760 205012 292400 205068 0 FreeSans 560 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 291760 227223 292400 227279 0 FreeSans 560 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 291760 249434 292400 249490 0 FreeSans 560 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 291760 294145 292400 294201 0 FreeSans 560 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -400 253401 240 253457 0 FreeSans 560 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -400 231790 240 231846 0 FreeSans 560 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -400 210179 240 210235 0 FreeSans 560 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -400 188568 240 188624 0 FreeSans 560 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -400 166957 240 167013 0 FreeSans 560 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -400 145346 240 145402 0 FreeSans 560 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 291760 4318 292400 4374 0 FreeSans 560 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -400 123835 240 123891 0 FreeSans 560 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -400 60024 240 60080 0 FreeSans 560 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -400 38413 240 38469 0 FreeSans 560 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -400 16802 240 16858 0 FreeSans 560 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -400 6091 240 6147 0 FreeSans 560 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -400 3727 240 3783 0 FreeSans 560 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -400 1363 240 1419 0 FreeSans 560 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 291760 6682 292400 6738 0 FreeSans 560 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 291760 9046 292400 9102 0 FreeSans 560 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 291760 11410 292400 11466 0 FreeSans 560 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 291760 24639 292400 24695 0 FreeSans 560 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 291760 46968 292400 47024 0 FreeSans 560 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 291760 136979 292400 137035 0 FreeSans 560 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 291760 159190 292400 159246 0 FreeSans 560 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 291760 181801 292400 181857 0 FreeSans 560 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 62908 -400 62964 240 0 FreeSans 560 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 240208 -400 240264 240 0 FreeSans 560 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 241981 -400 242037 240 0 FreeSans 560 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 243754 -400 243810 240 0 FreeSans 560 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 245527 -400 245583 240 0 FreeSans 560 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 247300 -400 247356 240 0 FreeSans 560 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 249073 -400 249129 240 0 FreeSans 560 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 250846 -400 250902 240 0 FreeSans 560 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 252619 -400 252675 240 0 FreeSans 560 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 254392 -400 254448 240 0 FreeSans 560 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 256165 -400 256221 240 0 FreeSans 560 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 80638 -400 80694 240 0 FreeSans 560 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 257938 -400 257994 240 0 FreeSans 560 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 259711 -400 259767 240 0 FreeSans 560 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 261484 -400 261540 240 0 FreeSans 560 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 263257 -400 263313 240 0 FreeSans 560 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 265030 -400 265086 240 0 FreeSans 560 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 266803 -400 266859 240 0 FreeSans 560 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 268576 -400 268632 240 0 FreeSans 560 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 270349 -400 270405 240 0 FreeSans 560 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 272122 -400 272178 240 0 FreeSans 560 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 273895 -400 273951 240 0 FreeSans 560 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 82411 -400 82467 240 0 FreeSans 560 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 275668 -400 275724 240 0 FreeSans 560 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 277441 -400 277497 240 0 FreeSans 560 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 279214 -400 279270 240 0 FreeSans 560 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 280987 -400 281043 240 0 FreeSans 560 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 282760 -400 282816 240 0 FreeSans 560 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 284533 -400 284589 240 0 FreeSans 560 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 286306 -400 286362 240 0 FreeSans 560 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 288079 -400 288135 240 0 FreeSans 560 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 84184 -400 84240 240 0 FreeSans 560 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 85957 -400 86013 240 0 FreeSans 560 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 87730 -400 87786 240 0 FreeSans 560 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 89503 -400 89559 240 0 FreeSans 560 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 91276 -400 91332 240 0 FreeSans 560 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 93049 -400 93105 240 0 FreeSans 560 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 94822 -400 94878 240 0 FreeSans 560 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 96595 -400 96651 240 0 FreeSans 560 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 64681 -400 64737 240 0 FreeSans 560 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 98368 -400 98424 240 0 FreeSans 560 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 100141 -400 100197 240 0 FreeSans 560 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 101914 -400 101970 240 0 FreeSans 560 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 103687 -400 103743 240 0 FreeSans 560 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 105460 -400 105516 240 0 FreeSans 560 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 107233 -400 107289 240 0 FreeSans 560 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 109006 -400 109062 240 0 FreeSans 560 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 110779 -400 110835 240 0 FreeSans 560 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 112552 -400 112608 240 0 FreeSans 560 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 114325 -400 114381 240 0 FreeSans 560 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 66454 -400 66510 240 0 FreeSans 560 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 116098 -400 116154 240 0 FreeSans 560 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 117871 -400 117927 240 0 FreeSans 560 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 119644 -400 119700 240 0 FreeSans 560 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 121417 -400 121473 240 0 FreeSans 560 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 123190 -400 123246 240 0 FreeSans 560 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 124963 -400 125019 240 0 FreeSans 560 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 126736 -400 126792 240 0 FreeSans 560 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 128509 -400 128565 240 0 FreeSans 560 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 130282 -400 130338 240 0 FreeSans 560 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 132055 -400 132111 240 0 FreeSans 560 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 68227 -400 68283 240 0 FreeSans 560 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 133828 -400 133884 240 0 FreeSans 560 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 135601 -400 135657 240 0 FreeSans 560 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 137374 -400 137430 240 0 FreeSans 560 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 139147 -400 139203 240 0 FreeSans 560 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 140920 -400 140976 240 0 FreeSans 560 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 142693 -400 142749 240 0 FreeSans 560 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 144466 -400 144522 240 0 FreeSans 560 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 146239 -400 146295 240 0 FreeSans 560 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 148012 -400 148068 240 0 FreeSans 560 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 149785 -400 149841 240 0 FreeSans 560 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 70000 -400 70056 240 0 FreeSans 560 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 151558 -400 151614 240 0 FreeSans 560 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 153331 -400 153387 240 0 FreeSans 560 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 155104 -400 155160 240 0 FreeSans 560 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 156877 -400 156933 240 0 FreeSans 560 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 158650 -400 158706 240 0 FreeSans 560 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 160423 -400 160479 240 0 FreeSans 560 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 162196 -400 162252 240 0 FreeSans 560 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 163969 -400 164025 240 0 FreeSans 560 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 165742 -400 165798 240 0 FreeSans 560 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 167515 -400 167571 240 0 FreeSans 560 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 71773 -400 71829 240 0 FreeSans 560 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 169288 -400 169344 240 0 FreeSans 560 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 171061 -400 171117 240 0 FreeSans 560 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 172834 -400 172890 240 0 FreeSans 560 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 174607 -400 174663 240 0 FreeSans 560 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 176380 -400 176436 240 0 FreeSans 560 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 178153 -400 178209 240 0 FreeSans 560 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 179926 -400 179982 240 0 FreeSans 560 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 181699 -400 181755 240 0 FreeSans 560 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 183472 -400 183528 240 0 FreeSans 560 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 185245 -400 185301 240 0 FreeSans 560 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 73546 -400 73602 240 0 FreeSans 560 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 187018 -400 187074 240 0 FreeSans 560 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 188791 -400 188847 240 0 FreeSans 560 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 190564 -400 190620 240 0 FreeSans 560 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 192337 -400 192393 240 0 FreeSans 560 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 194110 -400 194166 240 0 FreeSans 560 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 195883 -400 195939 240 0 FreeSans 560 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 197656 -400 197712 240 0 FreeSans 560 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 199429 -400 199485 240 0 FreeSans 560 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 201202 -400 201258 240 0 FreeSans 560 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 202975 -400 203031 240 0 FreeSans 560 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 75319 -400 75375 240 0 FreeSans 560 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 204748 -400 204804 240 0 FreeSans 560 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 206521 -400 206577 240 0 FreeSans 560 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 208294 -400 208350 240 0 FreeSans 560 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 210067 -400 210123 240 0 FreeSans 560 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 211840 -400 211896 240 0 FreeSans 560 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 213613 -400 213669 240 0 FreeSans 560 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 215386 -400 215442 240 0 FreeSans 560 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 217159 -400 217215 240 0 FreeSans 560 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 218932 -400 218988 240 0 FreeSans 560 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 220705 -400 220761 240 0 FreeSans 560 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 77092 -400 77148 240 0 FreeSans 560 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 222478 -400 222534 240 0 FreeSans 560 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 224251 -400 224307 240 0 FreeSans 560 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 226024 -400 226080 240 0 FreeSans 560 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 227797 -400 227853 240 0 FreeSans 560 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 229570 -400 229626 240 0 FreeSans 560 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 231343 -400 231399 240 0 FreeSans 560 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 233116 -400 233172 240 0 FreeSans 560 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 234889 -400 234945 240 0 FreeSans 560 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 236662 -400 236718 240 0 FreeSans 560 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 238435 -400 238491 240 0 FreeSans 560 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 78865 -400 78921 240 0 FreeSans 560 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 63499 -400 63555 240 0 FreeSans 560 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 240799 -400 240855 240 0 FreeSans 560 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 242572 -400 242628 240 0 FreeSans 560 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 244345 -400 244401 240 0 FreeSans 560 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 246118 -400 246174 240 0 FreeSans 560 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 247891 -400 247947 240 0 FreeSans 560 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 249664 -400 249720 240 0 FreeSans 560 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 251437 -400 251493 240 0 FreeSans 560 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 253210 -400 253266 240 0 FreeSans 560 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 254983 -400 255039 240 0 FreeSans 560 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 256756 -400 256812 240 0 FreeSans 560 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 81229 -400 81285 240 0 FreeSans 560 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 258529 -400 258585 240 0 FreeSans 560 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 260302 -400 260358 240 0 FreeSans 560 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 262075 -400 262131 240 0 FreeSans 560 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 263848 -400 263904 240 0 FreeSans 560 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 265621 -400 265677 240 0 FreeSans 560 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 267394 -400 267450 240 0 FreeSans 560 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 269167 -400 269223 240 0 FreeSans 560 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 270940 -400 270996 240 0 FreeSans 560 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 272713 -400 272769 240 0 FreeSans 560 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 274486 -400 274542 240 0 FreeSans 560 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 83002 -400 83058 240 0 FreeSans 560 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 276259 -400 276315 240 0 FreeSans 560 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 278032 -400 278088 240 0 FreeSans 560 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 279805 -400 279861 240 0 FreeSans 560 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 281578 -400 281634 240 0 FreeSans 560 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 283351 -400 283407 240 0 FreeSans 560 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 285124 -400 285180 240 0 FreeSans 560 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 286897 -400 286953 240 0 FreeSans 560 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 288670 -400 288726 240 0 FreeSans 560 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 84775 -400 84831 240 0 FreeSans 560 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 86548 -400 86604 240 0 FreeSans 560 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 88321 -400 88377 240 0 FreeSans 560 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 90094 -400 90150 240 0 FreeSans 560 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 91867 -400 91923 240 0 FreeSans 560 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 93640 -400 93696 240 0 FreeSans 560 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 95413 -400 95469 240 0 FreeSans 560 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 97186 -400 97242 240 0 FreeSans 560 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 65272 -400 65328 240 0 FreeSans 560 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 98959 -400 99015 240 0 FreeSans 560 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 100732 -400 100788 240 0 FreeSans 560 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 102505 -400 102561 240 0 FreeSans 560 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 104278 -400 104334 240 0 FreeSans 560 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 106051 -400 106107 240 0 FreeSans 560 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 107824 -400 107880 240 0 FreeSans 560 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 109597 -400 109653 240 0 FreeSans 560 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 111370 -400 111426 240 0 FreeSans 560 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 113143 -400 113199 240 0 FreeSans 560 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 114916 -400 114972 240 0 FreeSans 560 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 67045 -400 67101 240 0 FreeSans 560 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 116689 -400 116745 240 0 FreeSans 560 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 118462 -400 118518 240 0 FreeSans 560 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 120235 -400 120291 240 0 FreeSans 560 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 122008 -400 122064 240 0 FreeSans 560 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 123781 -400 123837 240 0 FreeSans 560 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 125554 -400 125610 240 0 FreeSans 560 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 127327 -400 127383 240 0 FreeSans 560 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 129100 -400 129156 240 0 FreeSans 560 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 130873 -400 130929 240 0 FreeSans 560 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 132646 -400 132702 240 0 FreeSans 560 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 68818 -400 68874 240 0 FreeSans 560 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 134419 -400 134475 240 0 FreeSans 560 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 136192 -400 136248 240 0 FreeSans 560 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 137965 -400 138021 240 0 FreeSans 560 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 139738 -400 139794 240 0 FreeSans 560 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 141511 -400 141567 240 0 FreeSans 560 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 143284 -400 143340 240 0 FreeSans 560 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 145057 -400 145113 240 0 FreeSans 560 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 146830 -400 146886 240 0 FreeSans 560 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 148603 -400 148659 240 0 FreeSans 560 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 150376 -400 150432 240 0 FreeSans 560 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 70591 -400 70647 240 0 FreeSans 560 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 152149 -400 152205 240 0 FreeSans 560 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 153922 -400 153978 240 0 FreeSans 560 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 155695 -400 155751 240 0 FreeSans 560 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 157468 -400 157524 240 0 FreeSans 560 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 159241 -400 159297 240 0 FreeSans 560 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 161014 -400 161070 240 0 FreeSans 560 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 162787 -400 162843 240 0 FreeSans 560 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 164560 -400 164616 240 0 FreeSans 560 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 166333 -400 166389 240 0 FreeSans 560 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 168106 -400 168162 240 0 FreeSans 560 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 72364 -400 72420 240 0 FreeSans 560 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 169879 -400 169935 240 0 FreeSans 560 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 171652 -400 171708 240 0 FreeSans 560 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 173425 -400 173481 240 0 FreeSans 560 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 175198 -400 175254 240 0 FreeSans 560 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 176971 -400 177027 240 0 FreeSans 560 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 178744 -400 178800 240 0 FreeSans 560 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 180517 -400 180573 240 0 FreeSans 560 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 182290 -400 182346 240 0 FreeSans 560 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 184063 -400 184119 240 0 FreeSans 560 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 185836 -400 185892 240 0 FreeSans 560 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 74137 -400 74193 240 0 FreeSans 560 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 187609 -400 187665 240 0 FreeSans 560 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 189382 -400 189438 240 0 FreeSans 560 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 191155 -400 191211 240 0 FreeSans 560 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 192928 -400 192984 240 0 FreeSans 560 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 194701 -400 194757 240 0 FreeSans 560 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 196474 -400 196530 240 0 FreeSans 560 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 198247 -400 198303 240 0 FreeSans 560 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 200020 -400 200076 240 0 FreeSans 560 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 201793 -400 201849 240 0 FreeSans 560 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 203566 -400 203622 240 0 FreeSans 560 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 75910 -400 75966 240 0 FreeSans 560 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 205339 -400 205395 240 0 FreeSans 560 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 207112 -400 207168 240 0 FreeSans 560 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 208885 -400 208941 240 0 FreeSans 560 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 210658 -400 210714 240 0 FreeSans 560 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 212431 -400 212487 240 0 FreeSans 560 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 214204 -400 214260 240 0 FreeSans 560 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 215977 -400 216033 240 0 FreeSans 560 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 217750 -400 217806 240 0 FreeSans 560 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 219523 -400 219579 240 0 FreeSans 560 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 221296 -400 221352 240 0 FreeSans 560 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 77683 -400 77739 240 0 FreeSans 560 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 223069 -400 223125 240 0 FreeSans 560 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 224842 -400 224898 240 0 FreeSans 560 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 226615 -400 226671 240 0 FreeSans 560 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 228388 -400 228444 240 0 FreeSans 560 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 230161 -400 230217 240 0 FreeSans 560 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 231934 -400 231990 240 0 FreeSans 560 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 233707 -400 233763 240 0 FreeSans 560 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 235480 -400 235536 240 0 FreeSans 560 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 237253 -400 237309 240 0 FreeSans 560 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 239026 -400 239082 240 0 FreeSans 560 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 79456 -400 79512 240 0 FreeSans 560 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 64090 -400 64146 240 0 FreeSans 560 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 241390 -400 241446 240 0 FreeSans 560 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 243163 -400 243219 240 0 FreeSans 560 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 244936 -400 244992 240 0 FreeSans 560 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 246709 -400 246765 240 0 FreeSans 560 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 248482 -400 248538 240 0 FreeSans 560 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 250255 -400 250311 240 0 FreeSans 560 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 252028 -400 252084 240 0 FreeSans 560 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 253801 -400 253857 240 0 FreeSans 560 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 255574 -400 255630 240 0 FreeSans 560 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 257347 -400 257403 240 0 FreeSans 560 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 81820 -400 81876 240 0 FreeSans 560 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 259120 -400 259176 240 0 FreeSans 560 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 260893 -400 260949 240 0 FreeSans 560 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 262666 -400 262722 240 0 FreeSans 560 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 264439 -400 264495 240 0 FreeSans 560 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 266212 -400 266268 240 0 FreeSans 560 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 267985 -400 268041 240 0 FreeSans 560 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 269758 -400 269814 240 0 FreeSans 560 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 271531 -400 271587 240 0 FreeSans 560 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 273304 -400 273360 240 0 FreeSans 560 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 275077 -400 275133 240 0 FreeSans 560 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 83593 -400 83649 240 0 FreeSans 560 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 276850 -400 276906 240 0 FreeSans 560 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 278623 -400 278679 240 0 FreeSans 560 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 280396 -400 280452 240 0 FreeSans 560 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 282169 -400 282225 240 0 FreeSans 560 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 283942 -400 283998 240 0 FreeSans 560 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 285715 -400 285771 240 0 FreeSans 560 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 287488 -400 287544 240 0 FreeSans 560 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 289261 -400 289317 240 0 FreeSans 560 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 85366 -400 85422 240 0 FreeSans 560 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 87139 -400 87195 240 0 FreeSans 560 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 88912 -400 88968 240 0 FreeSans 560 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 90685 -400 90741 240 0 FreeSans 560 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 92458 -400 92514 240 0 FreeSans 560 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 94231 -400 94287 240 0 FreeSans 560 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 96004 -400 96060 240 0 FreeSans 560 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 97777 -400 97833 240 0 FreeSans 560 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 65863 -400 65919 240 0 FreeSans 560 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 99550 -400 99606 240 0 FreeSans 560 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 101323 -400 101379 240 0 FreeSans 560 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 103096 -400 103152 240 0 FreeSans 560 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 104869 -400 104925 240 0 FreeSans 560 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 106642 -400 106698 240 0 FreeSans 560 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 108415 -400 108471 240 0 FreeSans 560 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 110188 -400 110244 240 0 FreeSans 560 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 111961 -400 112017 240 0 FreeSans 560 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 113734 -400 113790 240 0 FreeSans 560 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 115507 -400 115563 240 0 FreeSans 560 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 67636 -400 67692 240 0 FreeSans 560 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 117280 -400 117336 240 0 FreeSans 560 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 119053 -400 119109 240 0 FreeSans 560 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 120826 -400 120882 240 0 FreeSans 560 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 122599 -400 122655 240 0 FreeSans 560 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 124372 -400 124428 240 0 FreeSans 560 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 126145 -400 126201 240 0 FreeSans 560 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 127918 -400 127974 240 0 FreeSans 560 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 129691 -400 129747 240 0 FreeSans 560 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 131464 -400 131520 240 0 FreeSans 560 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 133237 -400 133293 240 0 FreeSans 560 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 69409 -400 69465 240 0 FreeSans 560 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 135010 -400 135066 240 0 FreeSans 560 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 136783 -400 136839 240 0 FreeSans 560 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 138556 -400 138612 240 0 FreeSans 560 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 140329 -400 140385 240 0 FreeSans 560 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 142102 -400 142158 240 0 FreeSans 560 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 143875 -400 143931 240 0 FreeSans 560 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 145648 -400 145704 240 0 FreeSans 560 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 147421 -400 147477 240 0 FreeSans 560 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 149194 -400 149250 240 0 FreeSans 560 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 150967 -400 151023 240 0 FreeSans 560 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 71182 -400 71238 240 0 FreeSans 560 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 152740 -400 152796 240 0 FreeSans 560 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 154513 -400 154569 240 0 FreeSans 560 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 156286 -400 156342 240 0 FreeSans 560 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 158059 -400 158115 240 0 FreeSans 560 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 159832 -400 159888 240 0 FreeSans 560 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 161605 -400 161661 240 0 FreeSans 560 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 163378 -400 163434 240 0 FreeSans 560 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 165151 -400 165207 240 0 FreeSans 560 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 166924 -400 166980 240 0 FreeSans 560 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 168697 -400 168753 240 0 FreeSans 560 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 72955 -400 73011 240 0 FreeSans 560 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 170470 -400 170526 240 0 FreeSans 560 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 172243 -400 172299 240 0 FreeSans 560 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 174016 -400 174072 240 0 FreeSans 560 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 175789 -400 175845 240 0 FreeSans 560 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 177562 -400 177618 240 0 FreeSans 560 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 179335 -400 179391 240 0 FreeSans 560 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 181108 -400 181164 240 0 FreeSans 560 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 182881 -400 182937 240 0 FreeSans 560 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 184654 -400 184710 240 0 FreeSans 560 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 186427 -400 186483 240 0 FreeSans 560 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 74728 -400 74784 240 0 FreeSans 560 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 188200 -400 188256 240 0 FreeSans 560 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 189973 -400 190029 240 0 FreeSans 560 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 191746 -400 191802 240 0 FreeSans 560 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 193519 -400 193575 240 0 FreeSans 560 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 195292 -400 195348 240 0 FreeSans 560 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 197065 -400 197121 240 0 FreeSans 560 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 198838 -400 198894 240 0 FreeSans 560 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 200611 -400 200667 240 0 FreeSans 560 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 202384 -400 202440 240 0 FreeSans 560 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 204157 -400 204213 240 0 FreeSans 560 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 76501 -400 76557 240 0 FreeSans 560 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 205930 -400 205986 240 0 FreeSans 560 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 207703 -400 207759 240 0 FreeSans 560 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 209476 -400 209532 240 0 FreeSans 560 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 211249 -400 211305 240 0 FreeSans 560 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 213022 -400 213078 240 0 FreeSans 560 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 214795 -400 214851 240 0 FreeSans 560 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 216568 -400 216624 240 0 FreeSans 560 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 218341 -400 218397 240 0 FreeSans 560 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 220114 -400 220170 240 0 FreeSans 560 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 221887 -400 221943 240 0 FreeSans 560 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 78274 -400 78330 240 0 FreeSans 560 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 223660 -400 223716 240 0 FreeSans 560 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 225433 -400 225489 240 0 FreeSans 560 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 227206 -400 227262 240 0 FreeSans 560 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 228979 -400 229035 240 0 FreeSans 560 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 230752 -400 230808 240 0 FreeSans 560 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 232525 -400 232581 240 0 FreeSans 560 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 234298 -400 234354 240 0 FreeSans 560 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 236071 -400 236127 240 0 FreeSans 560 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 237844 -400 237900 240 0 FreeSans 560 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 239617 -400 239673 240 0 FreeSans 560 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 80047 -400 80103 240 0 FreeSans 560 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 289852 -400 289908 240 0 FreeSans 560 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 290443 -400 290499 240 0 FreeSans 560 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 291034 -400 291090 240 0 FreeSans 560 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 291625 -400 291681 240 0 FreeSans 560 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 291170 319892 292400 322292 0 FreeSans 560 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 291170 314892 292400 317292 0 FreeSans 560 0 0 0 vccd1
+port 553 nsew signal bidirectional
+flabel metal3 s 0 321921 830 324321 0 FreeSans 560 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 316921 830 319321 0 FreeSans 560 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 291170 270281 292400 272681 0 FreeSans 560 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 291170 275281 292400 277681 0 FreeSans 560 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 291170 117615 292400 120015 0 FreeSans 560 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 291170 112615 292400 115015 0 FreeSans 560 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 102444 830 104844 0 FreeSans 560 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 107444 830 109844 0 FreeSans 560 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 260297 351170 262697 352400 0 FreeSans 960 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 255297 351170 257697 352400 0 FreeSans 960 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 291170 73415 292400 75815 0 FreeSans 560 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 291170 68415 292400 70815 0 FreeSans 560 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 279721 830 282121 0 FreeSans 560 0 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 0 274721 830 277121 0 FreeSans 560 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 291170 95715 292400 98115 0 FreeSans 560 0 0 0 vssd1
+port 568 nsew signal bidirectional
+flabel metal3 s 291170 90715 292400 93115 0 FreeSans 560 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 0 86444 830 88844 0 FreeSans 560 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 81444 830 83844 0 FreeSans 560 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 262 -400 318 240 0 FreeSans 560 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 853 -400 909 240 0 FreeSans 560 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 1444 -400 1500 240 0 FreeSans 560 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 3808 -400 3864 240 0 FreeSans 560 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 23902 -400 23958 240 0 FreeSans 560 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 25675 -400 25731 240 0 FreeSans 560 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 27448 -400 27504 240 0 FreeSans 560 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 29221 -400 29277 240 0 FreeSans 560 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 30994 -400 31050 240 0 FreeSans 560 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 32767 -400 32823 240 0 FreeSans 560 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 34540 -400 34596 240 0 FreeSans 560 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 36313 -400 36369 240 0 FreeSans 560 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 38086 -400 38142 240 0 FreeSans 560 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 39859 -400 39915 240 0 FreeSans 560 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 6172 -400 6228 240 0 FreeSans 560 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 41632 -400 41688 240 0 FreeSans 560 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 43405 -400 43461 240 0 FreeSans 560 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 45178 -400 45234 240 0 FreeSans 560 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 46951 -400 47007 240 0 FreeSans 560 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 48724 -400 48780 240 0 FreeSans 560 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 50497 -400 50553 240 0 FreeSans 560 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 52270 -400 52326 240 0 FreeSans 560 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 54043 -400 54099 240 0 FreeSans 560 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 55816 -400 55872 240 0 FreeSans 560 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 57589 -400 57645 240 0 FreeSans 560 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 8536 -400 8592 240 0 FreeSans 560 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 59362 -400 59418 240 0 FreeSans 560 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 61135 -400 61191 240 0 FreeSans 560 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 10900 -400 10956 240 0 FreeSans 560 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 13264 -400 13320 240 0 FreeSans 560 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 15037 -400 15093 240 0 FreeSans 560 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 16810 -400 16866 240 0 FreeSans 560 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 18583 -400 18639 240 0 FreeSans 560 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 20356 -400 20412 240 0 FreeSans 560 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 22129 -400 22185 240 0 FreeSans 560 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 2035 -400 2091 240 0 FreeSans 560 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 4399 -400 4455 240 0 FreeSans 560 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 24493 -400 24549 240 0 FreeSans 560 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 26266 -400 26322 240 0 FreeSans 560 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 28039 -400 28095 240 0 FreeSans 560 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 29812 -400 29868 240 0 FreeSans 560 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 31585 -400 31641 240 0 FreeSans 560 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 33358 -400 33414 240 0 FreeSans 560 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 35131 -400 35187 240 0 FreeSans 560 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 36904 -400 36960 240 0 FreeSans 560 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 38677 -400 38733 240 0 FreeSans 560 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 40450 -400 40506 240 0 FreeSans 560 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 6763 -400 6819 240 0 FreeSans 560 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 42223 -400 42279 240 0 FreeSans 560 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 43996 -400 44052 240 0 FreeSans 560 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 45769 -400 45825 240 0 FreeSans 560 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 47542 -400 47598 240 0 FreeSans 560 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 49315 -400 49371 240 0 FreeSans 560 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 51088 -400 51144 240 0 FreeSans 560 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 52861 -400 52917 240 0 FreeSans 560 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 54634 -400 54690 240 0 FreeSans 560 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 56407 -400 56463 240 0 FreeSans 560 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 58180 -400 58236 240 0 FreeSans 560 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 9127 -400 9183 240 0 FreeSans 560 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 59953 -400 60009 240 0 FreeSans 560 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 61726 -400 61782 240 0 FreeSans 560 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 11491 -400 11547 240 0 FreeSans 560 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 13855 -400 13911 240 0 FreeSans 560 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 15628 -400 15684 240 0 FreeSans 560 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 17401 -400 17457 240 0 FreeSans 560 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 19174 -400 19230 240 0 FreeSans 560 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 20947 -400 21003 240 0 FreeSans 560 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 22720 -400 22776 240 0 FreeSans 560 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 4990 -400 5046 240 0 FreeSans 560 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 25084 -400 25140 240 0 FreeSans 560 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 26857 -400 26913 240 0 FreeSans 560 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 28630 -400 28686 240 0 FreeSans 560 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 30403 -400 30459 240 0 FreeSans 560 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 32176 -400 32232 240 0 FreeSans 560 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 33949 -400 34005 240 0 FreeSans 560 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 35722 -400 35778 240 0 FreeSans 560 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 37495 -400 37551 240 0 FreeSans 560 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 39268 -400 39324 240 0 FreeSans 560 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 41041 -400 41097 240 0 FreeSans 560 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 7354 -400 7410 240 0 FreeSans 560 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 42814 -400 42870 240 0 FreeSans 560 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 44587 -400 44643 240 0 FreeSans 560 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
+flabel metal2 s 46360 -400 46416 240 0 FreeSans 560 90 0 0 wbs_dat_o[22]
+port 654 nsew signal tristate
+flabel metal2 s 48133 -400 48189 240 0 FreeSans 560 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 49906 -400 49962 240 0 FreeSans 560 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 51679 -400 51735 240 0 FreeSans 560 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 53452 -400 53508 240 0 FreeSans 560 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 55225 -400 55281 240 0 FreeSans 560 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 56998 -400 57054 240 0 FreeSans 560 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 58771 -400 58827 240 0 FreeSans 560 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 9718 -400 9774 240 0 FreeSans 560 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 60544 -400 60600 240 0 FreeSans 560 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 62317 -400 62373 240 0 FreeSans 560 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 12082 -400 12138 240 0 FreeSans 560 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 14446 -400 14502 240 0 FreeSans 560 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 16219 -400 16275 240 0 FreeSans 560 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 17992 -400 18048 240 0 FreeSans 560 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 19765 -400 19821 240 0 FreeSans 560 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 21538 -400 21594 240 0 FreeSans 560 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 23311 -400 23367 240 0 FreeSans 560 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 5581 -400 5637 240 0 FreeSans 560 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 7945 -400 8001 240 0 FreeSans 560 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 10309 -400 10365 240 0 FreeSans 560 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 12673 -400 12729 240 0 FreeSans 560 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 2626 -400 2682 240 0 FreeSans 560 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 3217 -400 3273 240 0 FreeSans 560 90 0 0 wbs_we_i
+port 677 nsew signal input
+<< properties >>
+string FIXED_BBOX 0 0 292000 352000
+<< end >>
diff --git a/mag/user_project_wrapper_empty.mag b/mag/user_project_wrapper_empty.mag
new file mode 100644
index 0000000..45a281d
--- /dev/null
+++ b/mag/user_project_wrapper_empty.mag
Binary files differ
diff --git a/netgen/comp.out b/netgen/comp.out
new file mode 100644
index 0000000..9955338
--- /dev/null
+++ b/netgen/comp.out
@@ -0,0 +1,2043 @@
+Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_W5U4AW in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_TGFUGS in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_3YBPVB in circuit example_por (0)(4 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YUHPXE in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_PKVMTM in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_1_WRT4AW in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YEUEBV in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YUHPBG in circuit example_por (0)(1 instance)
+Flattening unmatched subcell user_analog_proj_example in circuit user_analog_project_wrapper (0)(1 instance)
+Equate elements: no current cell.
+Equate elements: no current cell.
+Equate elements: no current cell.
+Equate elements: no current cell.
+Equate elements: no current cell.
+Class sky130_fd_sc_hvl__buf_8: Merged 18 devices.
+Equate elements: no current cell.
+Equate elements: no current cell.
+Class sky130_fd_sc_hvl__inv_8: Merged 14 devices.
+Equate elements: no current cell.
+Class example_por: Merged 20 devices.
+
+Subcircuit summary:
+Circuit 1: example_por |Circuit 2: example_por
+------------------------------------------------------------------------|------------------------------------------------------------------------
+sky130_fd_pr__cap_mim_m3_2 (1) |sky130_fd_pr__cap_mim_m3_2 (1)
+sky130_fd_sc_hvl__buf_8 (2) |sky130_fd_sc_hvl__buf_8 (2)
+sky130_fd_pr__pfet_g5v0d10v5 (8) |sky130_fd_pr__pfet_g5v0d10v5 (8)
+sky130_fd_pr__nfet_g5v0d10v5 (3) |sky130_fd_pr__nfet_g5v0d10v5 (3)
+sky130_fd_pr__res_xhigh_po_0p69 (3) |sky130_fd_pr__res_xhigh_po_0p69 (3)
+sky130_fd_sc_hvl__schmittbuf_1 (1) |sky130_fd_sc_hvl__schmittbuf_1 (1)
+sky130_fd_pr__cap_mim_m3_1 (1) |sky130_fd_pr__cap_mim_m3_1 (1)
+sky130_fd_sc_hvl__inv_8 (1) |sky130_fd_sc_hvl__inv_8 (1)
+Number of devices: 20 |Number of devices: 20
+Number of nets: 16 |Number of nets: 16
+-------------------------------------------------------------------------------------------------------------------------------------------------
+Circuits match uniquely.
+Property errors were found.
+Netlists match uniquely.
+There were property errors.
+sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/sky130_fd_pr__res_xhigh_po_0p693 vs. sky130_fd_pr__res_xhigh_po_0p69R1:
+Property W in circuit2 has no matching property in circuit1
+sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/sky130_fd_pr__res_xhigh_po_0p690 vs. sky130_fd_pr__res_xhigh_po_0p69R2:
+Property W in circuit2 has no matching property in circuit1
+sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/sky130_fd_pr__res_xhigh_po_0p6918 vs. sky130_fd_pr__res_xhigh_po_0p69R3:
+Property W in circuit2 has no matching property in circuit1
+
+Subcircuit pins:
+Circuit 1: example_por |Circuit 2: example_por
+------------------------------------------------------------------------|------------------------------------------------------------------------
+vdd3v3 |vdd3v3
+porb_h |porb_h
+porb_l |porb_l
+por_l |por_l
+vdd1v8 |vdd1v8
+vss |vss
+-------------------------------------------------------------------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes example_por and example_por are equivalent.
+
+Cell user_analog_project_wrapper disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[9]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper disconnected node: io_analog[0]
+Cell user_analog_project_wrapper disconnected node: io_analog[10]
+Cell user_analog_project_wrapper disconnected node: io_analog[1]
+Cell user_analog_project_wrapper disconnected node: io_analog[2]
+Cell user_analog_project_wrapper disconnected node: io_analog[3]
+Cell user_analog_project_wrapper disconnected node: io_analog[7]
+Cell user_analog_project_wrapper disconnected node: io_analog[8]
+Cell user_analog_project_wrapper disconnected node: io_analog[9]
+Cell user_analog_project_wrapper disconnected node: io_analog[5]
+Cell user_analog_project_wrapper disconnected node: io_analog[6]
+Cell user_analog_project_wrapper disconnected node: io_in[0]
+Cell user_analog_project_wrapper disconnected node: io_in[10]
+Cell user_analog_project_wrapper disconnected node: io_in[11]
+Cell user_analog_project_wrapper disconnected node: io_in[12]
+Cell user_analog_project_wrapper disconnected node: io_in[13]
+Cell user_analog_project_wrapper disconnected node: io_in[14]
+Cell user_analog_project_wrapper disconnected node: io_in[15]
+Cell user_analog_project_wrapper disconnected node: io_in[16]
+Cell user_analog_project_wrapper disconnected node: io_in[17]
+Cell user_analog_project_wrapper disconnected node: io_in[18]
+Cell user_analog_project_wrapper disconnected node: io_in[19]
+Cell user_analog_project_wrapper disconnected node: io_in[1]
+Cell user_analog_project_wrapper disconnected node: io_in[20]
+Cell user_analog_project_wrapper disconnected node: io_in[21]
+Cell user_analog_project_wrapper disconnected node: io_in[22]
+Cell user_analog_project_wrapper disconnected node: io_in[23]
+Cell user_analog_project_wrapper disconnected node: io_in[24]
+Cell user_analog_project_wrapper disconnected node: io_in[25]
+Cell user_analog_project_wrapper disconnected node: io_in[26]
+Cell user_analog_project_wrapper disconnected node: io_in[2]
+Cell user_analog_project_wrapper disconnected node: io_in[3]
+Cell user_analog_project_wrapper disconnected node: io_in[4]
+Cell user_analog_project_wrapper disconnected node: io_in[5]
+Cell user_analog_project_wrapper disconnected node: io_in[6]
+Cell user_analog_project_wrapper disconnected node: io_in[7]
+Cell user_analog_project_wrapper disconnected node: io_in[8]
+Cell user_analog_project_wrapper disconnected node: io_in[9]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[0]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[10]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[11]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[12]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[13]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[14]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[15]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[16]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[17]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[18]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[19]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[1]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[20]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[21]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[22]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[23]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[24]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[25]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[26]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[2]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[3]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[4]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[5]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[6]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[7]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[8]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[9]
+Cell user_analog_project_wrapper disconnected node: io_oeb[0]
+Cell user_analog_project_wrapper disconnected node: io_oeb[10]
+Cell user_analog_project_wrapper disconnected node: io_oeb[13]
+Cell user_analog_project_wrapper disconnected node: io_oeb[14]
+Cell user_analog_project_wrapper disconnected node: io_oeb[17]
+Cell user_analog_project_wrapper disconnected node: io_oeb[18]
+Cell user_analog_project_wrapper disconnected node: io_oeb[19]
+Cell user_analog_project_wrapper disconnected node: io_oeb[1]
+Cell user_analog_project_wrapper disconnected node: io_oeb[20]
+Cell user_analog_project_wrapper disconnected node: io_oeb[21]
+Cell user_analog_project_wrapper disconnected node: io_oeb[22]
+Cell user_analog_project_wrapper disconnected node: io_oeb[23]
+Cell user_analog_project_wrapper disconnected node: io_oeb[24]
+Cell user_analog_project_wrapper disconnected node: io_oeb[25]
+Cell user_analog_project_wrapper disconnected node: io_oeb[26]
+Cell user_analog_project_wrapper disconnected node: io_oeb[2]
+Cell user_analog_project_wrapper disconnected node: io_oeb[3]
+Cell user_analog_project_wrapper disconnected node: io_oeb[4]
+Cell user_analog_project_wrapper disconnected node: io_oeb[5]
+Cell user_analog_project_wrapper disconnected node: io_oeb[6]
+Cell user_analog_project_wrapper disconnected node: io_oeb[7]
+Cell user_analog_project_wrapper disconnected node: io_oeb[8]
+Cell user_analog_project_wrapper disconnected node: io_oeb[9]
+Cell user_analog_project_wrapper disconnected node: io_out[0]
+Cell user_analog_project_wrapper disconnected node: io_out[10]
+Cell user_analog_project_wrapper disconnected node: io_out[13]
+Cell user_analog_project_wrapper disconnected node: io_out[14]
+Cell user_analog_project_wrapper disconnected node: io_out[17]
+Cell user_analog_project_wrapper disconnected node: io_out[18]
+Cell user_analog_project_wrapper disconnected node: io_out[19]
+Cell user_analog_project_wrapper disconnected node: io_out[1]
+Cell user_analog_project_wrapper disconnected node: io_out[20]
+Cell user_analog_project_wrapper disconnected node: io_out[21]
+Cell user_analog_project_wrapper disconnected node: io_out[22]
+Cell user_analog_project_wrapper disconnected node: io_out[23]
+Cell user_analog_project_wrapper disconnected node: io_out[24]
+Cell user_analog_project_wrapper disconnected node: io_out[25]
+Cell user_analog_project_wrapper disconnected node: io_out[26]
+Cell user_analog_project_wrapper disconnected node: io_out[2]
+Cell user_analog_project_wrapper disconnected node: io_out[3]
+Cell user_analog_project_wrapper disconnected node: io_out[4]
+Cell user_analog_project_wrapper disconnected node: io_out[5]
+Cell user_analog_project_wrapper disconnected node: io_out[6]
+Cell user_analog_project_wrapper disconnected node: io_out[7]
+Cell user_analog_project_wrapper disconnected node: io_out[8]
+Cell user_analog_project_wrapper disconnected node: io_out[9]
+Cell user_analog_project_wrapper disconnected node: la_data_in[0]
+Cell user_analog_project_wrapper disconnected node: la_data_in[100]
+Cell user_analog_project_wrapper disconnected node: la_data_in[101]
+Cell user_analog_project_wrapper disconnected node: la_data_in[102]
+Cell user_analog_project_wrapper disconnected node: la_data_in[103]
+Cell user_analog_project_wrapper disconnected node: la_data_in[104]
+Cell user_analog_project_wrapper disconnected node: la_data_in[105]
+Cell user_analog_project_wrapper disconnected node: la_data_in[106]
+Cell user_analog_project_wrapper disconnected node: la_data_in[107]
+Cell user_analog_project_wrapper disconnected node: la_data_in[108]
+Cell user_analog_project_wrapper disconnected node: la_data_in[109]
+Cell user_analog_project_wrapper disconnected node: la_data_in[10]
+Cell user_analog_project_wrapper disconnected node: la_data_in[110]
+Cell user_analog_project_wrapper disconnected node: la_data_in[111]
+Cell user_analog_project_wrapper disconnected node: la_data_in[112]
+Cell user_analog_project_wrapper disconnected node: la_data_in[113]
+Cell user_analog_project_wrapper disconnected node: la_data_in[114]
+Cell user_analog_project_wrapper disconnected node: la_data_in[115]
+Cell user_analog_project_wrapper disconnected node: la_data_in[116]
+Cell user_analog_project_wrapper disconnected node: la_data_in[117]
+Cell user_analog_project_wrapper disconnected node: la_data_in[118]
+Cell user_analog_project_wrapper disconnected node: la_data_in[119]
+Cell user_analog_project_wrapper disconnected node: la_data_in[11]
+Cell user_analog_project_wrapper disconnected node: la_data_in[120]
+Cell user_analog_project_wrapper disconnected node: la_data_in[121]
+Cell user_analog_project_wrapper disconnected node: la_data_in[122]
+Cell user_analog_project_wrapper disconnected node: la_data_in[123]
+Cell user_analog_project_wrapper disconnected node: la_data_in[124]
+Cell user_analog_project_wrapper disconnected node: la_data_in[125]
+Cell user_analog_project_wrapper disconnected node: la_data_in[126]
+Cell user_analog_project_wrapper disconnected node: la_data_in[127]
+Cell user_analog_project_wrapper disconnected node: la_data_in[12]
+Cell user_analog_project_wrapper disconnected node: la_data_in[13]
+Cell user_analog_project_wrapper disconnected node: la_data_in[14]
+Cell user_analog_project_wrapper disconnected node: la_data_in[15]
+Cell user_analog_project_wrapper disconnected node: la_data_in[16]
+Cell user_analog_project_wrapper disconnected node: la_data_in[17]
+Cell user_analog_project_wrapper disconnected node: la_data_in[18]
+Cell user_analog_project_wrapper disconnected node: la_data_in[19]
+Cell user_analog_project_wrapper disconnected node: la_data_in[1]
+Cell user_analog_project_wrapper disconnected node: la_data_in[20]
+Cell user_analog_project_wrapper disconnected node: la_data_in[21]
+Cell user_analog_project_wrapper disconnected node: la_data_in[22]
+Cell user_analog_project_wrapper disconnected node: la_data_in[23]
+Cell user_analog_project_wrapper disconnected node: la_data_in[24]
+Cell user_analog_project_wrapper disconnected node: la_data_in[25]
+Cell user_analog_project_wrapper disconnected node: la_data_in[26]
+Cell user_analog_project_wrapper disconnected node: la_data_in[27]
+Cell user_analog_project_wrapper disconnected node: la_data_in[28]
+Cell user_analog_project_wrapper disconnected node: la_data_in[29]
+Cell user_analog_project_wrapper disconnected node: la_data_in[2]
+Cell user_analog_project_wrapper disconnected node: la_data_in[30]
+Cell user_analog_project_wrapper disconnected node: la_data_in[31]
+Cell user_analog_project_wrapper disconnected node: la_data_in[32]
+Cell user_analog_project_wrapper disconnected node: la_data_in[33]
+Cell user_analog_project_wrapper disconnected node: la_data_in[34]
+Cell user_analog_project_wrapper disconnected node: la_data_in[35]
+Cell user_analog_project_wrapper disconnected node: la_data_in[36]
+Cell user_analog_project_wrapper disconnected node: la_data_in[37]
+Cell user_analog_project_wrapper disconnected node: la_data_in[38]
+Cell user_analog_project_wrapper disconnected node: la_data_in[39]
+Cell user_analog_project_wrapper disconnected node: la_data_in[3]
+Cell user_analog_project_wrapper disconnected node: la_data_in[40]
+Cell user_analog_project_wrapper disconnected node: la_data_in[41]
+Cell user_analog_project_wrapper disconnected node: la_data_in[42]
+Cell user_analog_project_wrapper disconnected node: la_data_in[43]
+Cell user_analog_project_wrapper disconnected node: la_data_in[44]
+Cell user_analog_project_wrapper disconnected node: la_data_in[45]
+Cell user_analog_project_wrapper disconnected node: la_data_in[46]
+Cell user_analog_project_wrapper disconnected node: la_data_in[47]
+Cell user_analog_project_wrapper disconnected node: la_data_in[48]
+Cell user_analog_project_wrapper disconnected node: la_data_in[49]
+Cell user_analog_project_wrapper disconnected node: la_data_in[4]
+Cell user_analog_project_wrapper disconnected node: la_data_in[50]
+Cell user_analog_project_wrapper disconnected node: la_data_in[51]
+Cell user_analog_project_wrapper disconnected node: la_data_in[52]
+Cell user_analog_project_wrapper disconnected node: la_data_in[53]
+Cell user_analog_project_wrapper disconnected node: la_data_in[54]
+Cell user_analog_project_wrapper disconnected node: la_data_in[55]
+Cell user_analog_project_wrapper disconnected node: la_data_in[56]
+Cell user_analog_project_wrapper disconnected node: la_data_in[57]
+Cell user_analog_project_wrapper disconnected node: la_data_in[58]
+Cell user_analog_project_wrapper disconnected node: la_data_in[59]
+Cell user_analog_project_wrapper disconnected node: la_data_in[5]
+Cell user_analog_project_wrapper disconnected node: la_data_in[60]
+Cell user_analog_project_wrapper disconnected node: la_data_in[61]
+Cell user_analog_project_wrapper disconnected node: la_data_in[62]
+Cell user_analog_project_wrapper disconnected node: la_data_in[63]
+Cell user_analog_project_wrapper disconnected node: la_data_in[64]
+Cell user_analog_project_wrapper disconnected node: la_data_in[65]
+Cell user_analog_project_wrapper disconnected node: la_data_in[66]
+Cell user_analog_project_wrapper disconnected node: la_data_in[67]
+Cell user_analog_project_wrapper disconnected node: la_data_in[68]
+Cell user_analog_project_wrapper disconnected node: la_data_in[69]
+Cell user_analog_project_wrapper disconnected node: la_data_in[6]
+Cell user_analog_project_wrapper disconnected node: la_data_in[70]
+Cell user_analog_project_wrapper disconnected node: la_data_in[71]
+Cell user_analog_project_wrapper disconnected node: la_data_in[72]
+Cell user_analog_project_wrapper disconnected node: la_data_in[73]
+Cell user_analog_project_wrapper disconnected node: la_data_in[74]
+Cell user_analog_project_wrapper disconnected node: la_data_in[75]
+Cell user_analog_project_wrapper disconnected node: la_data_in[76]
+Cell user_analog_project_wrapper disconnected node: la_data_in[77]
+Cell user_analog_project_wrapper disconnected node: la_data_in[78]
+Cell user_analog_project_wrapper disconnected node: la_data_in[79]
+Cell user_analog_project_wrapper disconnected node: la_data_in[7]
+Cell user_analog_project_wrapper disconnected node: la_data_in[80]
+Cell user_analog_project_wrapper disconnected node: la_data_in[81]
+Cell user_analog_project_wrapper disconnected node: la_data_in[82]
+Cell user_analog_project_wrapper disconnected node: la_data_in[83]
+Cell user_analog_project_wrapper disconnected node: la_data_in[84]
+Cell user_analog_project_wrapper disconnected node: la_data_in[85]
+Cell user_analog_project_wrapper disconnected node: la_data_in[86]
+Cell user_analog_project_wrapper disconnected node: la_data_in[87]
+Cell user_analog_project_wrapper disconnected node: la_data_in[88]
+Cell user_analog_project_wrapper disconnected node: la_data_in[89]
+Cell user_analog_project_wrapper disconnected node: la_data_in[8]
+Cell user_analog_project_wrapper disconnected node: la_data_in[90]
+Cell user_analog_project_wrapper disconnected node: la_data_in[91]
+Cell user_analog_project_wrapper disconnected node: la_data_in[92]
+Cell user_analog_project_wrapper disconnected node: la_data_in[93]
+Cell user_analog_project_wrapper disconnected node: la_data_in[94]
+Cell user_analog_project_wrapper disconnected node: la_data_in[95]
+Cell user_analog_project_wrapper disconnected node: la_data_in[96]
+Cell user_analog_project_wrapper disconnected node: la_data_in[97]
+Cell user_analog_project_wrapper disconnected node: la_data_in[98]
+Cell user_analog_project_wrapper disconnected node: la_data_in[99]
+Cell user_analog_project_wrapper disconnected node: la_data_in[9]
+Cell user_analog_project_wrapper disconnected node: la_data_out[0]
+Cell user_analog_project_wrapper disconnected node: la_data_out[100]
+Cell user_analog_project_wrapper disconnected node: la_data_out[101]
+Cell user_analog_project_wrapper disconnected node: la_data_out[102]
+Cell user_analog_project_wrapper disconnected node: la_data_out[103]
+Cell user_analog_project_wrapper disconnected node: la_data_out[104]
+Cell user_analog_project_wrapper disconnected node: la_data_out[105]
+Cell user_analog_project_wrapper disconnected node: la_data_out[106]
+Cell user_analog_project_wrapper disconnected node: la_data_out[107]
+Cell user_analog_project_wrapper disconnected node: la_data_out[108]
+Cell user_analog_project_wrapper disconnected node: la_data_out[109]
+Cell user_analog_project_wrapper disconnected node: la_data_out[10]
+Cell user_analog_project_wrapper disconnected node: la_data_out[110]
+Cell user_analog_project_wrapper disconnected node: la_data_out[111]
+Cell user_analog_project_wrapper disconnected node: la_data_out[112]
+Cell user_analog_project_wrapper disconnected node: la_data_out[113]
+Cell user_analog_project_wrapper disconnected node: la_data_out[114]
+Cell user_analog_project_wrapper disconnected node: la_data_out[115]
+Cell user_analog_project_wrapper disconnected node: la_data_out[116]
+Cell user_analog_project_wrapper disconnected node: la_data_out[117]
+Cell user_analog_project_wrapper disconnected node: la_data_out[118]
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+Cell user_analog_project_wrapper disconnected node: wbs_stb_i
+Cell user_analog_project_wrapper disconnected node: wbs_we_i
+
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+Cell user_analog_project_wrapper disconnected node: la_data_out[16]
+Cell user_analog_project_wrapper disconnected node: la_data_out[15]
+Cell user_analog_project_wrapper disconnected node: la_data_out[14]
+Cell user_analog_project_wrapper disconnected node: la_data_out[13]
+Cell user_analog_project_wrapper disconnected node: la_data_out[12]
+Cell user_analog_project_wrapper disconnected node: la_data_out[11]
+Cell user_analog_project_wrapper disconnected node: la_data_out[10]
+Cell user_analog_project_wrapper disconnected node: la_data_out[9]
+Cell user_analog_project_wrapper disconnected node: la_data_out[8]
+Cell user_analog_project_wrapper disconnected node: la_data_out[7]
+Cell user_analog_project_wrapper disconnected node: la_data_out[6]
+Cell user_analog_project_wrapper disconnected node: la_data_out[5]
+Cell user_analog_project_wrapper disconnected node: la_data_out[4]
+Cell user_analog_project_wrapper disconnected node: la_data_out[3]
+Cell user_analog_project_wrapper disconnected node: la_data_out[2]
+Cell user_analog_project_wrapper disconnected node: la_data_out[1]
+Cell user_analog_project_wrapper disconnected node: la_data_out[0]
+Cell user_analog_project_wrapper disconnected node: la_oenb[127]
+Cell user_analog_project_wrapper disconnected node: la_oenb[126]
+Cell user_analog_project_wrapper disconnected node: la_oenb[125]
+Cell user_analog_project_wrapper disconnected node: la_oenb[124]
+Cell user_analog_project_wrapper disconnected node: la_oenb[123]
+Cell user_analog_project_wrapper disconnected node: la_oenb[122]
+Cell user_analog_project_wrapper disconnected node: la_oenb[121]
+Cell user_analog_project_wrapper disconnected node: la_oenb[120]
+Cell user_analog_project_wrapper disconnected node: la_oenb[119]
+Cell user_analog_project_wrapper disconnected node: la_oenb[118]
+Cell user_analog_project_wrapper disconnected node: la_oenb[117]
+Cell user_analog_project_wrapper disconnected node: la_oenb[116]
+Cell user_analog_project_wrapper disconnected node: la_oenb[115]
+Cell user_analog_project_wrapper disconnected node: la_oenb[114]
+Cell user_analog_project_wrapper disconnected node: la_oenb[113]
+Cell user_analog_project_wrapper disconnected node: la_oenb[112]
+Cell user_analog_project_wrapper disconnected node: la_oenb[111]
+Cell user_analog_project_wrapper disconnected node: la_oenb[110]
+Cell user_analog_project_wrapper disconnected node: la_oenb[109]
+Cell user_analog_project_wrapper disconnected node: la_oenb[108]
+Cell user_analog_project_wrapper disconnected node: la_oenb[107]
+Cell user_analog_project_wrapper disconnected node: la_oenb[106]
+Cell user_analog_project_wrapper disconnected node: la_oenb[105]
+Cell user_analog_project_wrapper disconnected node: la_oenb[104]
+Cell user_analog_project_wrapper disconnected node: la_oenb[103]
+Cell user_analog_project_wrapper disconnected node: la_oenb[102]
+Cell user_analog_project_wrapper disconnected node: la_oenb[101]
+Cell user_analog_project_wrapper disconnected node: la_oenb[100]
+Cell user_analog_project_wrapper disconnected node: la_oenb[99]
+Cell user_analog_project_wrapper disconnected node: la_oenb[98]
+Cell user_analog_project_wrapper disconnected node: la_oenb[97]
+Cell user_analog_project_wrapper disconnected node: la_oenb[96]
+Cell user_analog_project_wrapper disconnected node: la_oenb[95]
+Cell user_analog_project_wrapper disconnected node: la_oenb[94]
+Cell user_analog_project_wrapper disconnected node: la_oenb[93]
+Cell user_analog_project_wrapper disconnected node: la_oenb[92]
+Cell user_analog_project_wrapper disconnected node: la_oenb[91]
+Cell user_analog_project_wrapper disconnected node: la_oenb[90]
+Cell user_analog_project_wrapper disconnected node: la_oenb[89]
+Cell user_analog_project_wrapper disconnected node: la_oenb[88]
+Cell user_analog_project_wrapper disconnected node: la_oenb[87]
+Cell user_analog_project_wrapper disconnected node: la_oenb[86]
+Cell user_analog_project_wrapper disconnected node: la_oenb[85]
+Cell user_analog_project_wrapper disconnected node: la_oenb[84]
+Cell user_analog_project_wrapper disconnected node: la_oenb[83]
+Cell user_analog_project_wrapper disconnected node: la_oenb[82]
+Cell user_analog_project_wrapper disconnected node: la_oenb[81]
+Cell user_analog_project_wrapper disconnected node: la_oenb[80]
+Cell user_analog_project_wrapper disconnected node: la_oenb[79]
+Cell user_analog_project_wrapper disconnected node: la_oenb[78]
+Cell user_analog_project_wrapper disconnected node: la_oenb[77]
+Cell user_analog_project_wrapper disconnected node: la_oenb[76]
+Cell user_analog_project_wrapper disconnected node: la_oenb[75]
+Cell user_analog_project_wrapper disconnected node: la_oenb[74]
+Cell user_analog_project_wrapper disconnected node: la_oenb[73]
+Cell user_analog_project_wrapper disconnected node: la_oenb[72]
+Cell user_analog_project_wrapper disconnected node: la_oenb[71]
+Cell user_analog_project_wrapper disconnected node: la_oenb[70]
+Cell user_analog_project_wrapper disconnected node: la_oenb[69]
+Cell user_analog_project_wrapper disconnected node: la_oenb[68]
+Cell user_analog_project_wrapper disconnected node: la_oenb[67]
+Cell user_analog_project_wrapper disconnected node: la_oenb[66]
+Cell user_analog_project_wrapper disconnected node: la_oenb[65]
+Cell user_analog_project_wrapper disconnected node: la_oenb[64]
+Cell user_analog_project_wrapper disconnected node: la_oenb[63]
+Cell user_analog_project_wrapper disconnected node: la_oenb[62]
+Cell user_analog_project_wrapper disconnected node: la_oenb[61]
+Cell user_analog_project_wrapper disconnected node: la_oenb[60]
+Cell user_analog_project_wrapper disconnected node: la_oenb[59]
+Cell user_analog_project_wrapper disconnected node: la_oenb[58]
+Cell user_analog_project_wrapper disconnected node: la_oenb[57]
+Cell user_analog_project_wrapper disconnected node: la_oenb[56]
+Cell user_analog_project_wrapper disconnected node: la_oenb[55]
+Cell user_analog_project_wrapper disconnected node: la_oenb[54]
+Cell user_analog_project_wrapper disconnected node: la_oenb[53]
+Cell user_analog_project_wrapper disconnected node: la_oenb[52]
+Cell user_analog_project_wrapper disconnected node: la_oenb[51]
+Cell user_analog_project_wrapper disconnected node: la_oenb[50]
+Cell user_analog_project_wrapper disconnected node: la_oenb[49]
+Cell user_analog_project_wrapper disconnected node: la_oenb[48]
+Cell user_analog_project_wrapper disconnected node: la_oenb[47]
+Cell user_analog_project_wrapper disconnected node: la_oenb[46]
+Cell user_analog_project_wrapper disconnected node: la_oenb[45]
+Cell user_analog_project_wrapper disconnected node: la_oenb[44]
+Cell user_analog_project_wrapper disconnected node: la_oenb[43]
+Cell user_analog_project_wrapper disconnected node: la_oenb[42]
+Cell user_analog_project_wrapper disconnected node: la_oenb[41]
+Cell user_analog_project_wrapper disconnected node: la_oenb[40]
+Cell user_analog_project_wrapper disconnected node: la_oenb[39]
+Cell user_analog_project_wrapper disconnected node: la_oenb[38]
+Cell user_analog_project_wrapper disconnected node: la_oenb[37]
+Cell user_analog_project_wrapper disconnected node: la_oenb[36]
+Cell user_analog_project_wrapper disconnected node: la_oenb[35]
+Cell user_analog_project_wrapper disconnected node: la_oenb[34]
+Cell user_analog_project_wrapper disconnected node: la_oenb[33]
+Cell user_analog_project_wrapper disconnected node: la_oenb[32]
+Cell user_analog_project_wrapper disconnected node: la_oenb[31]
+Cell user_analog_project_wrapper disconnected node: la_oenb[30]
+Cell user_analog_project_wrapper disconnected node: la_oenb[29]
+Cell user_analog_project_wrapper disconnected node: la_oenb[28]
+Cell user_analog_project_wrapper disconnected node: la_oenb[27]
+Cell user_analog_project_wrapper disconnected node: la_oenb[26]
+Cell user_analog_project_wrapper disconnected node: la_oenb[25]
+Cell user_analog_project_wrapper disconnected node: la_oenb[24]
+Cell user_analog_project_wrapper disconnected node: la_oenb[23]
+Cell user_analog_project_wrapper disconnected node: la_oenb[22]
+Cell user_analog_project_wrapper disconnected node: la_oenb[21]
+Cell user_analog_project_wrapper disconnected node: la_oenb[20]
+Cell user_analog_project_wrapper disconnected node: la_oenb[19]
+Cell user_analog_project_wrapper disconnected node: la_oenb[18]
+Cell user_analog_project_wrapper disconnected node: la_oenb[17]
+Cell user_analog_project_wrapper disconnected node: la_oenb[16]
+Cell user_analog_project_wrapper disconnected node: la_oenb[15]
+Cell user_analog_project_wrapper disconnected node: la_oenb[14]
+Cell user_analog_project_wrapper disconnected node: la_oenb[13]
+Cell user_analog_project_wrapper disconnected node: la_oenb[12]
+Cell user_analog_project_wrapper disconnected node: la_oenb[11]
+Cell user_analog_project_wrapper disconnected node: la_oenb[10]
+Cell user_analog_project_wrapper disconnected node: la_oenb[9]
+Cell user_analog_project_wrapper disconnected node: la_oenb[8]
+Cell user_analog_project_wrapper disconnected node: la_oenb[7]
+Cell user_analog_project_wrapper disconnected node: la_oenb[6]
+Cell user_analog_project_wrapper disconnected node: la_oenb[5]
+Cell user_analog_project_wrapper disconnected node: la_oenb[4]
+Cell user_analog_project_wrapper disconnected node: la_oenb[3]
+Cell user_analog_project_wrapper disconnected node: la_oenb[2]
+Cell user_analog_project_wrapper disconnected node: la_oenb[1]
+Cell user_analog_project_wrapper disconnected node: la_oenb[0]
+Cell user_analog_project_wrapper disconnected node: io_in[26]
+Cell user_analog_project_wrapper disconnected node: io_in[25]
+Cell user_analog_project_wrapper disconnected node: io_in[24]
+Cell user_analog_project_wrapper disconnected node: io_in[23]
+Cell user_analog_project_wrapper disconnected node: io_in[22]
+Cell user_analog_project_wrapper disconnected node: io_in[21]
+Cell user_analog_project_wrapper disconnected node: io_in[20]
+Cell user_analog_project_wrapper disconnected node: io_in[19]
+Cell user_analog_project_wrapper disconnected node: io_in[18]
+Cell user_analog_project_wrapper disconnected node: io_in[17]
+Cell user_analog_project_wrapper disconnected node: io_in[16]
+Cell user_analog_project_wrapper disconnected node: io_in[15]
+Cell user_analog_project_wrapper disconnected node: io_in[14]
+Cell user_analog_project_wrapper disconnected node: io_in[13]
+Cell user_analog_project_wrapper disconnected node: io_in[12]
+Cell user_analog_project_wrapper disconnected node: io_in[11]
+Cell user_analog_project_wrapper disconnected node: io_in[10]
+Cell user_analog_project_wrapper disconnected node: io_in[9]
+Cell user_analog_project_wrapper disconnected node: io_in[8]
+Cell user_analog_project_wrapper disconnected node: io_in[7]
+Cell user_analog_project_wrapper disconnected node: io_in[6]
+Cell user_analog_project_wrapper disconnected node: io_in[5]
+Cell user_analog_project_wrapper disconnected node: io_in[4]
+Cell user_analog_project_wrapper disconnected node: io_in[3]
+Cell user_analog_project_wrapper disconnected node: io_in[2]
+Cell user_analog_project_wrapper disconnected node: io_in[1]
+Cell user_analog_project_wrapper disconnected node: io_in[0]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[26]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[25]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[24]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[23]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[22]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[21]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[20]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[19]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[18]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[17]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[16]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[15]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[14]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[13]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[12]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[11]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[10]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[9]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[8]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[7]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[6]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[5]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[4]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[3]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[2]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[1]
+Cell user_analog_project_wrapper disconnected node: io_in_3v3[0]
+Cell user_analog_project_wrapper disconnected node: io_out[26]
+Cell user_analog_project_wrapper disconnected node: io_out[25]
+Cell user_analog_project_wrapper disconnected node: io_out[24]
+Cell user_analog_project_wrapper disconnected node: io_out[23]
+Cell user_analog_project_wrapper disconnected node: io_out[22]
+Cell user_analog_project_wrapper disconnected node: io_out[21]
+Cell user_analog_project_wrapper disconnected node: io_out[20]
+Cell user_analog_project_wrapper disconnected node: io_out[19]
+Cell user_analog_project_wrapper disconnected node: io_out[18]
+Cell user_analog_project_wrapper disconnected node: io_out[17]
+Cell user_analog_project_wrapper disconnected node: io_out[14]
+Cell user_analog_project_wrapper disconnected node: io_out[13]
+Cell user_analog_project_wrapper disconnected node: io_out[10]
+Cell user_analog_project_wrapper disconnected node: io_out[9]
+Cell user_analog_project_wrapper disconnected node: io_out[8]
+Cell user_analog_project_wrapper disconnected node: io_out[7]
+Cell user_analog_project_wrapper disconnected node: io_out[6]
+Cell user_analog_project_wrapper disconnected node: io_out[5]
+Cell user_analog_project_wrapper disconnected node: io_out[4]
+Cell user_analog_project_wrapper disconnected node: io_out[3]
+Cell user_analog_project_wrapper disconnected node: io_out[2]
+Cell user_analog_project_wrapper disconnected node: io_out[1]
+Cell user_analog_project_wrapper disconnected node: io_out[0]
+Cell user_analog_project_wrapper disconnected node: io_oeb[26]
+Cell user_analog_project_wrapper disconnected node: io_oeb[25]
+Cell user_analog_project_wrapper disconnected node: io_oeb[24]
+Cell user_analog_project_wrapper disconnected node: io_oeb[23]
+Cell user_analog_project_wrapper disconnected node: io_oeb[22]
+Cell user_analog_project_wrapper disconnected node: io_oeb[21]
+Cell user_analog_project_wrapper disconnected node: io_oeb[20]
+Cell user_analog_project_wrapper disconnected node: io_oeb[19]
+Cell user_analog_project_wrapper disconnected node: io_oeb[18]
+Cell user_analog_project_wrapper disconnected node: io_oeb[17]
+Cell user_analog_project_wrapper disconnected node: io_oeb[16]
+Cell user_analog_project_wrapper disconnected node: io_oeb[15]
+Cell user_analog_project_wrapper disconnected node: io_oeb[14]
+Cell user_analog_project_wrapper disconnected node: io_oeb[13]
+Cell user_analog_project_wrapper disconnected node: io_oeb[12]
+Cell user_analog_project_wrapper disconnected node: io_oeb[11]
+Cell user_analog_project_wrapper disconnected node: io_oeb[10]
+Cell user_analog_project_wrapper disconnected node: io_oeb[9]
+Cell user_analog_project_wrapper disconnected node: io_oeb[8]
+Cell user_analog_project_wrapper disconnected node: io_oeb[7]
+Cell user_analog_project_wrapper disconnected node: io_oeb[6]
+Cell user_analog_project_wrapper disconnected node: io_oeb[5]
+Cell user_analog_project_wrapper disconnected node: io_oeb[4]
+Cell user_analog_project_wrapper disconnected node: io_oeb[3]
+Cell user_analog_project_wrapper disconnected node: io_oeb[2]
+Cell user_analog_project_wrapper disconnected node: io_oeb[1]
+Cell user_analog_project_wrapper disconnected node: io_oeb[0]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[9]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper disconnected node: io_analog[10]
+Cell user_analog_project_wrapper disconnected node: io_analog[9]
+Cell user_analog_project_wrapper disconnected node: io_analog[8]
+Cell user_analog_project_wrapper disconnected node: io_analog[7]
+Cell user_analog_project_wrapper disconnected node: io_analog[6]
+Cell user_analog_project_wrapper disconnected node: io_analog[5]
+Cell user_analog_project_wrapper disconnected node: io_analog[3]
+Cell user_analog_project_wrapper disconnected node: io_analog[2]
+Cell user_analog_project_wrapper disconnected node: io_analog[1]
+Cell user_analog_project_wrapper disconnected node: io_analog[0]
+Cell user_analog_project_wrapper disconnected node: io_clamp_high[2]
+Cell user_analog_project_wrapper disconnected node: io_clamp_high[1]
+Cell user_analog_project_wrapper disconnected node: io_clamp_high[0]
+Cell user_analog_project_wrapper disconnected node: io_clamp_low[2]
+Cell user_analog_project_wrapper disconnected node: io_clamp_low[1]
+Cell user_analog_project_wrapper disconnected node: io_clamp_low[0]
+Cell user_analog_project_wrapper disconnected node: user_clock2
+Cell user_analog_project_wrapper disconnected node: user_irq[2]
+Cell user_analog_project_wrapper disconnected node: user_irq[1]
+Cell user_analog_project_wrapper disconnected node: user_irq[0]
+
+Subcircuit summary:
+Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper
+------------------------------------------------------------------------|------------------------------------------------------------------------
+example_por (2) |example_por (2)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 10 |Number of nets: 10
+-------------------------------------------------------------------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+Circuits match correctly.
+
+Subcircuit pins:
+Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper
+------------------------------------------------------------------------|------------------------------------------------------------------------
+vdda1 |vdda1
+io_clamp_high[0] |io_analog[4] **Mismatch**
+gpio_analog[3] |gpio_analog[3]
+gpio_analog[7] |gpio_analog[7]
+io_out[11] |io_out[11]
+io_out[15] |io_out[15]
+io_out[16] |io_out[16]
+io_out[12] |io_out[12]
+vccd1 |vccd1
+vssa1 |vssa1
+gpio_analog[0] |gpio_analog[0]
+gpio_analog[10] |gpio_analog[10]
+gpio_analog[11] |gpio_analog[11]
+gpio_analog[12] |gpio_analog[12]
+gpio_analog[13] |gpio_analog[13]
+gpio_analog[14] |gpio_analog[14]
+gpio_analog[15] |gpio_analog[15]
+gpio_analog[16] |gpio_analog[16]
+gpio_analog[17] |gpio_analog[17]
+gpio_analog[1] |gpio_analog[1]
+gpio_analog[2] |gpio_analog[2]
+gpio_analog[4] |gpio_analog[4]
+gpio_analog[5] |gpio_analog[5]
+gpio_analog[6] |gpio_analog[6]
+gpio_analog[8] |gpio_analog[8]
+gpio_analog[9] |gpio_analog[9]
+gpio_noesd[0] |gpio_noesd[0]
+gpio_noesd[10] |gpio_noesd[10]
+gpio_noesd[11] |gpio_noesd[11]
+gpio_noesd[12] |gpio_noesd[12]
+gpio_noesd[13] |gpio_noesd[13]
+gpio_noesd[14] |gpio_noesd[14]
+gpio_noesd[15] |gpio_noesd[15]
+gpio_noesd[16] |gpio_noesd[16]
+gpio_noesd[17] |gpio_noesd[17]
+gpio_noesd[1] |gpio_noesd[1]
+gpio_noesd[2] |gpio_noesd[2]
+gpio_noesd[3] |gpio_noesd[3]
+gpio_noesd[4] |gpio_noesd[4]
+gpio_noesd[5] |gpio_noesd[5]
+gpio_noesd[6] |gpio_noesd[6]
+gpio_noesd[7] |gpio_noesd[7]
+gpio_noesd[8] |gpio_noesd[8]
+gpio_noesd[9] |gpio_noesd[9]
+io_analog[0] |io_analog[0]
+io_analog[10] |io_analog[10]
+io_analog[1] |io_analog[1]
+io_analog[2] |io_analog[2]
+io_analog[3] |io_analog[3]
+io_analog[7] |io_analog[7]
+io_analog[8] |io_analog[8]
+io_analog[9] |io_analog[9]
+io_analog[5] |io_analog[5]
+io_analog[6] |io_analog[6]
+io_in[0] |io_in[0]
+io_in[10] |io_in[10]
+io_in[11] |io_in[11]
+io_in[12] |io_in[12]
+io_in[13] |io_in[13]
+io_in[14] |io_in[14]
+io_in[15] |io_in[15]
+io_in[16] |io_in[16]
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+la_oenb[41] |la_oenb[41]
+la_oenb[42] |la_oenb[42]
+la_oenb[43] |la_oenb[43]
+la_oenb[44] |la_oenb[44]
+la_oenb[45] |la_oenb[45]
+la_oenb[46] |la_oenb[46]
+la_oenb[47] |la_oenb[47]
+la_oenb[48] |la_oenb[48]
+la_oenb[49] |la_oenb[49]
+la_oenb[4] |la_oenb[4]
+la_oenb[50] |la_oenb[50]
+la_oenb[51] |la_oenb[51]
+la_oenb[52] |la_oenb[52]
+la_oenb[53] |la_oenb[53]
+la_oenb[54] |la_oenb[54]
+la_oenb[55] |la_oenb[55]
+la_oenb[56] |la_oenb[56]
+la_oenb[57] |la_oenb[57]
+la_oenb[58] |la_oenb[58]
+la_oenb[59] |la_oenb[59]
+la_oenb[5] |la_oenb[5]
+la_oenb[60] |la_oenb[60]
+la_oenb[61] |la_oenb[61]
+la_oenb[62] |la_oenb[62]
+la_oenb[63] |la_oenb[63]
+la_oenb[64] |la_oenb[64]
+la_oenb[65] |la_oenb[65]
+la_oenb[66] |la_oenb[66]
+la_oenb[67] |la_oenb[67]
+la_oenb[68] |la_oenb[68]
+la_oenb[69] |la_oenb[69]
+la_oenb[6] |la_oenb[6]
+la_oenb[70] |la_oenb[70]
+la_oenb[71] |la_oenb[71]
+la_oenb[72] |la_oenb[72]
+la_oenb[73] |la_oenb[73]
+la_oenb[74] |la_oenb[74]
+la_oenb[75] |la_oenb[75]
+la_oenb[76] |la_oenb[76]
+la_oenb[77] |la_oenb[77]
+la_oenb[78] |la_oenb[78]
+la_oenb[79] |la_oenb[79]
+la_oenb[7] |la_oenb[7]
+la_oenb[80] |la_oenb[80]
+la_oenb[81] |la_oenb[81]
+la_oenb[82] |la_oenb[82]
+la_oenb[83] |la_oenb[83]
+la_oenb[84] |la_oenb[84]
+la_oenb[85] |la_oenb[85]
+la_oenb[86] |la_oenb[86]
+la_oenb[87] |la_oenb[87]
+la_oenb[88] |la_oenb[88]
+la_oenb[89] |la_oenb[89]
+la_oenb[8] |la_oenb[8]
+la_oenb[90] |la_oenb[90]
+la_oenb[91] |la_oenb[91]
+la_oenb[92] |la_oenb[92]
+la_oenb[93] |la_oenb[93]
+la_oenb[94] |la_oenb[94]
+la_oenb[95] |la_oenb[95]
+la_oenb[96] |la_oenb[96]
+la_oenb[97] |la_oenb[97]
+la_oenb[98] |la_oenb[98]
+la_oenb[99] |la_oenb[99]
+la_oenb[9] |la_oenb[9]
+user_clock2 |user_clock2
+user_irq[0] |user_irq[0]
+user_irq[1] |user_irq[1]
+user_irq[2] |user_irq[2]
+vccd2 |vccd2
+vdda2 |vdda2
+vssa2 |vssa2
+vssd1 |vssd1
+vssd2 |vssd2
+wb_clk_i |wb_clk_i
+wb_rst_i |wb_rst_i
+wbs_ack_o |wbs_ack_o
+wbs_adr_i[0] |wbs_adr_i[0]
+wbs_adr_i[10] |wbs_adr_i[10]
+wbs_adr_i[11] |wbs_adr_i[11]
+wbs_adr_i[12] |wbs_adr_i[12]
+wbs_adr_i[13] |wbs_adr_i[13]
+wbs_adr_i[14] |wbs_adr_i[14]
+wbs_adr_i[15] |wbs_adr_i[15]
+wbs_adr_i[16] |wbs_adr_i[16]
+wbs_adr_i[17] |wbs_adr_i[17]
+wbs_adr_i[18] |wbs_adr_i[18]
+wbs_adr_i[19] |wbs_adr_i[19]
+wbs_adr_i[1] |wbs_adr_i[1]
+wbs_adr_i[20] |wbs_adr_i[20]
+wbs_adr_i[21] |wbs_adr_i[21]
+wbs_adr_i[22] |wbs_adr_i[22]
+wbs_adr_i[23] |wbs_adr_i[23]
+wbs_adr_i[24] |wbs_adr_i[24]
+wbs_adr_i[25] |wbs_adr_i[25]
+wbs_adr_i[26] |wbs_adr_i[26]
+wbs_adr_i[27] |wbs_adr_i[27]
+wbs_adr_i[28] |wbs_adr_i[28]
+wbs_adr_i[29] |wbs_adr_i[29]
+wbs_adr_i[2] |wbs_adr_i[2]
+wbs_adr_i[30] |wbs_adr_i[30]
+wbs_adr_i[31] |wbs_adr_i[31]
+wbs_adr_i[3] |wbs_adr_i[3]
+wbs_adr_i[4] |wbs_adr_i[4]
+wbs_adr_i[5] |wbs_adr_i[5]
+wbs_adr_i[6] |wbs_adr_i[6]
+wbs_adr_i[7] |wbs_adr_i[7]
+wbs_adr_i[8] |wbs_adr_i[8]
+wbs_adr_i[9] |wbs_adr_i[9]
+wbs_cyc_i |wbs_cyc_i
+wbs_dat_i[0] |wbs_dat_i[0]
+wbs_dat_i[10] |wbs_dat_i[10]
+wbs_dat_i[11] |wbs_dat_i[11]
+wbs_dat_i[12] |wbs_dat_i[12]
+wbs_dat_i[13] |wbs_dat_i[13]
+wbs_dat_i[14] |wbs_dat_i[14]
+wbs_dat_i[15] |wbs_dat_i[15]
+wbs_dat_i[16] |wbs_dat_i[16]
+wbs_dat_i[17] |wbs_dat_i[17]
+wbs_dat_i[18] |wbs_dat_i[18]
+wbs_dat_i[19] |wbs_dat_i[19]
+wbs_dat_i[1] |wbs_dat_i[1]
+wbs_dat_i[20] |wbs_dat_i[20]
+wbs_dat_i[21] |wbs_dat_i[21]
+wbs_dat_i[22] |wbs_dat_i[22]
+wbs_dat_i[23] |wbs_dat_i[23]
+wbs_dat_i[24] |wbs_dat_i[24]
+wbs_dat_i[25] |wbs_dat_i[25]
+wbs_dat_i[26] |wbs_dat_i[26]
+wbs_dat_i[27] |wbs_dat_i[27]
+wbs_dat_i[28] |wbs_dat_i[28]
+wbs_dat_i[29] |wbs_dat_i[29]
+wbs_dat_i[2] |wbs_dat_i[2]
+wbs_dat_i[30] |wbs_dat_i[30]
+wbs_dat_i[31] |wbs_dat_i[31]
+wbs_dat_i[3] |wbs_dat_i[3]
+wbs_dat_i[4] |wbs_dat_i[4]
+wbs_dat_i[5] |wbs_dat_i[5]
+wbs_dat_i[6] |wbs_dat_i[6]
+wbs_dat_i[7] |wbs_dat_i[7]
+wbs_dat_i[8] |wbs_dat_i[8]
+wbs_dat_i[9] |wbs_dat_i[9]
+wbs_dat_o[0] |wbs_dat_o[0]
+wbs_dat_o[10] |wbs_dat_o[10]
+wbs_dat_o[11] |wbs_dat_o[11]
+wbs_dat_o[12] |wbs_dat_o[12]
+wbs_dat_o[13] |wbs_dat_o[13]
+wbs_dat_o[14] |wbs_dat_o[14]
+wbs_dat_o[15] |wbs_dat_o[15]
+wbs_dat_o[16] |wbs_dat_o[16]
+wbs_dat_o[17] |wbs_dat_o[17]
+wbs_dat_o[18] |wbs_dat_o[18]
+wbs_dat_o[19] |wbs_dat_o[19]
+wbs_dat_o[1] |wbs_dat_o[1]
+wbs_dat_o[20] |wbs_dat_o[20]
+wbs_dat_o[21] |wbs_dat_o[21]
+wbs_dat_o[22] |wbs_dat_o[22]
+wbs_dat_o[23] |wbs_dat_o[23]
+wbs_dat_o[24] |wbs_dat_o[24]
+wbs_dat_o[25] |wbs_dat_o[25]
+wbs_dat_o[26] |wbs_dat_o[26]
+wbs_dat_o[27] |wbs_dat_o[27]
+wbs_dat_o[28] |wbs_dat_o[28]
+wbs_dat_o[29] |wbs_dat_o[29]
+wbs_dat_o[2] |wbs_dat_o[2]
+wbs_dat_o[30] |wbs_dat_o[30]
+wbs_dat_o[31] |wbs_dat_o[31]
+wbs_dat_o[3] |wbs_dat_o[3]
+wbs_dat_o[4] |wbs_dat_o[4]
+wbs_dat_o[5] |wbs_dat_o[5]
+wbs_dat_o[6] |wbs_dat_o[6]
+wbs_dat_o[7] |wbs_dat_o[7]
+wbs_dat_o[8] |wbs_dat_o[8]
+wbs_dat_o[9] |wbs_dat_o[9]
+wbs_sel_i[0] |wbs_sel_i[0]
+wbs_sel_i[1] |wbs_sel_i[1]
+wbs_sel_i[2] |wbs_sel_i[2]
+wbs_sel_i[3] |wbs_sel_i[3]
+wbs_stb_i |wbs_stb_i
+wbs_we_i |wbs_we_i
+(no matching pin) |io_oeb[16]
+(no matching pin) |io_oeb[15]
+(no matching pin) |io_oeb[12]
+(no matching pin) |io_oeb[11]
+(no matching pin) |io_clamp_high[2]
+(no matching pin) |io_clamp_high[1]
+(no matching pin) |io_clamp_high[0]
+(no matching pin) |io_clamp_low[2]
+(no matching pin) |io_clamp_low[1]
+(no matching pin) |io_clamp_low[0]
+-------------------------------------------------------------------------------------------------------------------------------------------------
+Instance of user_analog_project_wrapper has only 98 of 653 ports
+Cell pin lists for user_analog_project_wrapper and user_analog_project_wrapper altered to match.
+The top level cell failed pin matching.
+The following cells had property errors: example_por
diff --git a/netgen/example_por.spice b/netgen/example_por.spice
new file mode 100644
index 0000000..499f397
--- /dev/null
+++ b/netgen/example_por.spice
@@ -0,0 +1,213 @@
+* NGSPICE file created from example_por.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_2_W5U4AW VSUBS m4_n3179_n3100# c2_n3079_n3000#
+X0 c2_n3079_n3000# m4_n3179_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_sc_hvl__buf_8 A VGND VNB VPB VPWR X
+X0 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=2.9175e+12p pd=2.189e+07u as=8.475e+11p ps=7.13e+06u w=1.5e+06u l=500000u
+X1 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=1.45875e+12p pd=1.289e+07u as=8.4e+11p ps=8.24e+06u w=750000u l=500000u
+X2 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=1.68e+12p ps=1.424e+07u w=1.5e+06u l=500000u
+X3 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X4 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X5 a_45_443# A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=4.2375e+11p pd=4.13e+06u as=0p ps=0u w=750000u l=500000u
+X6 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X7 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X8 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X9 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X10 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X11 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X12 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X13 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X14 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X15 a_45_443# A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X16 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X17 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X18 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X19 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X20 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X21 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ VSUBS a_n465_n200# a_n247_n200# a_n29_n200#
++ a_843_n200# w_n1101_n497# a_n843_n297# a_625_n200# a_683_n297# a_n625_n297# a_407_n200#
++ a_465_n297# a_n407_n297# a_247_n297# a_n901_n200# a_189_n200# a_29_n297# a_n189_n297#
++ a_n683_n200#
+X0 a_407_n200# a_247_n297# a_189_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X1 a_843_n200# a_683_n297# a_625_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X2 a_n465_n200# a_n625_n297# a_n683_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X3 a_189_n200# a_29_n297# a_n29_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X4 a_625_n200# a_465_n297# a_407_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X5 a_n247_n200# a_n407_n297# a_n465_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
+X6 a_n683_n200# a_n843_n297# a_n901_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X7 a_n29_n200# a_n189_n297# a_n247_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_TGFUGS a_n80_n288# a_n574_n200# a_n356_n200#
++ a_n138_n200# a_n734_n288# a_574_n288# a_n516_n288# a_356_n288# a_80_n200# a_n298_n288#
++ a_138_n288# w_n962_n458# a_734_n200# a_516_n200# a_298_n200# a_n792_n200#
+X0 a_516_n200# a_356_n288# a_298_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X1 a_n574_n200# a_n734_n288# a_n792_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X2 a_298_n200# a_138_n288# a_80_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X3 a_80_n200# a_n80_n288# a_n138_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X4 a_734_n200# a_574_n288# a_516_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
+X5 a_n356_n200# a_n516_n288# a_n574_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
+X6 a_n138_n200# a_n298_n288# a_n356_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 a_n2578_n2932# a_5142_2500# a_n1034_n2932#
++ a_n262_2500# a_1668_2500# a_n262_n2932# a_n3736_2500# a_3984_n2932# a_n2192_2500#
++ a_3984_2500# a_2440_n2932# a_2440_2500# a_4370_n2932# a_3598_2500# a_2054_2500#
++ a_n4508_n2932# a_510_2500# a_n4122_2500# a_n2964_n2932# a_124_2500# a_n4894_n2932#
++ a_1282_n2932# a_124_n2932# a_n1420_n2932# a_4370_2500# a_n3350_n2932# a_n648_n2932#
++ a_n648_2500# a_n5280_n2932# a_n1420_2500# a_n2964_2500# a_n2578_2500# a_n1034_2500#
++ a_2826_n2932# a_n2192_n2932# a_2826_2500# a_4756_n2932# w_n5446_n3098# a_1282_2500#
++ a_3212_n2932# a_n4894_2500# a_n3350_2500# a_n4508_2500# a_5142_n2932# a_896_2500#
++ a_510_n2932# a_1668_n2932# a_n1806_n2932# a_4756_2500# a_n3736_n2932# a_3598_n2932#
++ a_3212_2500# a_2054_n2932# a_896_n2932# a_n5280_2500# a_n4122_n2932# a_n1806_2500#
+X0 a_n3350_n2932# a_n3350_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X1 a_n4508_n2932# a_n4508_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X2 a_n2578_n2932# a_n2578_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X3 a_n1420_n2932# a_n1420_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X4 a_n4894_n2932# a_n4894_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X5 a_n3736_n2932# a_n3736_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X6 a_3598_n2932# a_3598_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X7 a_124_n2932# a_124_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X8 a_4756_n2932# a_4756_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X9 a_n2964_n2932# a_n2964_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X10 a_1668_n2932# a_1668_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X11 a_n1806_n2932# a_n1806_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X12 a_n648_n2932# a_n648_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X13 a_3984_n2932# a_3984_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X14 a_2826_n2932# a_2826_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X15 a_510_n2932# a_510_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X16 a_n4122_n2932# a_n4122_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X17 a_n2192_n2932# a_n2192_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X18 a_5142_n2932# a_5142_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X19 a_n1034_n2932# a_n1034_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X20 a_2054_n2932# a_2054_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X21 a_4370_n2932# a_4370_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X22 a_3212_n2932# a_3212_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X23 a_1282_n2932# a_1282_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X24 a_n262_n2932# a_n262_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X25 a_n5280_n2932# a_n5280_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X26 a_2440_n2932# a_2440_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X27 a_896_n2932# a_896_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_3YBPVB VSUBS a_n138_n200# w_n338_n497# a_80_n200#
++ a_n80_n297#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_sc_hvl__schmittbuf_1 A VGND VNB VPB VPWR X
+X0 a_64_207# VPWR VPB sky130_fd_pr__res_generic_pd__hv w=290000u l=3.11e+06u
+X1 a_231_463# A a_117_181# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=4.0875e+11p pd=4.09e+06u as=1.9875e+11p ps=2.03e+06u w=750000u l=500000u
+X2 a_217_207# A a_117_181# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=2.289e+11p pd=2.77e+06u as=1.113e+11p ps=1.37e+06u w=420000u l=500000u
+X3 VPWR A a_231_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=1.02225e+12p pd=5.2e+06u as=0p ps=0u w=750000u l=500000u
+X4 a_217_207# a_117_181# a_64_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=1.113e+11p ps=1.37e+06u w=420000u l=500000u
+X5 X a_117_181# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=1.9875e+11p pd=2.03e+06u as=9.478e+11p ps=4.36e+06u w=750000u l=500000u
+X6 a_78_463# VGND VNB sky130_fd_pr__res_generic_nd__hv w=290000u l=1.355e+06u
+X7 X a_117_181# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=3.975e+11p pd=3.53e+06u as=0p ps=0u w=1.5e+06u l=500000u
+X8 VGND A a_217_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
+X9 a_231_463# a_117_181# a_78_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=1.9875e+11p ps=2.03e+06u w=750000u l=500000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPXE VSUBS a_n138_n200# w_n338_n497# a_80_n200#
++ a_n80_n297#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_PKVMTM a_n80_n288# a_n138_n200# a_80_n200# w_n308_n458#
+X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC a_n80_n288# a_n138_n200# a_80_n200# w_n308_n458#
+X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WRT4AW VSUBS m3_n3136_n3100# c1_n3036_n3000#
+X0 c1_n3036_n3000# m3_n3136_n3100# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YEUEBV VSUBS w_n992_n497# a_n574_n200# a_n356_n200#
++ a_n138_n200# a_80_n200# a_n80_n297# a_734_n200# a_n734_n297# a_516_n200# a_574_n297#
++ a_n516_n297# a_356_n297# a_298_n200# a_n298_n297# a_138_n297# a_n792_n200#
+X0 a_734_n200# a_574_n297# a_516_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X1 a_n356_n200# a_n516_n297# a_n574_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X2 a_n138_n200# a_n298_n297# a_n356_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
+X3 a_516_n200# a_356_n297# a_298_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X4 a_n574_n200# a_n734_n297# a_n792_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X5 a_298_n200# a_138_n297# a_80_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X6 a_80_n200# a_n80_n297# a_n138_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPBG VSUBS a_n138_n200# w_n338_n497# a_80_n200#
++ a_n80_n297#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_sc_hvl__inv_8 A VGND VNB VPB VPWR Y
+X0 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=1.68e+12p pd=1.424e+07u as=2.055e+12p ps=1.774e+07u w=1.5e+06u l=500000u
+X1 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=8.4e+11p pd=8.24e+06u as=1.14e+12p ps=1.054e+07u w=750000u l=500000u
+X2 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X3 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X4 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X5 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X6 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X7 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X8 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X9 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X10 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X11 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X12 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X13 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X14 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X15 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+.ends
+
+.subckt example_por vdd3v3 vdd1v8 vss porb_h por_l porb_l
+Xsky130_fd_pr__cap_mim_m3_2_W5U4AW_0 vss sky130_fd_sc_hvl__schmittbuf_1_0/A vss sky130_fd_pr__cap_mim_m3_2_W5U4AW
+Xsky130_fd_sc_hvl__buf_8_1 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd1v8 vdd1v8 porb_l
++ sky130_fd_sc_hvl__buf_8
+Xsky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0 vss vdd3v3 m1_502_7653# vdd3v3 vdd3v3 vdd3v3
++ m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653#
++ m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653# sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ
+Xsky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0 m1_721_6815# vss m1_721_6815# vss m1_721_6815#
++ m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# vss
++ vss m1_721_6815# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_TGFUGS
+Xsky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0 li_2935_165# vss li_4479_165# li_4866_5813#
++ li_7182_5813# li_5251_165# li_1778_5813# li_9111_165# li_3322_5813# li_9498_5813#
++ li_7567_165# li_7954_5813# li_9883_165# li_8726_5813# li_7182_5813# li_619_165#
++ li_5638_5813# li_1006_5813# li_2163_165# li_5638_5813# li_619_165# li_6795_165#
++ li_5251_165# li_3707_165# li_9498_5813# li_2163_165# li_4479_165# li_4866_5813#
++ vss li_4094_5813# li_2550_5813# li_2550_5813# li_4094_5813# li_8339_165# li_2935_165#
++ li_7954_5813# li_9883_165# vss li_6410_5813# li_8339_165# vss li_1778_5813# li_1006_5813#
++ vss li_6410_5813# li_6023_165# li_6795_165# li_3707_165# vdd3v3 li_1391_165# li_9111_165#
++ li_8726_5813# li_7567_165# li_6023_165# vss li_1391_165# li_3322_5813# sky130_fd_pr__res_xhigh_po_0p69_S5N9F3
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0 vss m1_2993_7658# vdd3v3 m1_721_6815# m1_185_6573#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_sc_hvl__schmittbuf_1_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss vss vdd3v3
++ vdd3v3 sky130_fd_sc_hvl__inv_8_0/A sky130_fd_sc_hvl__schmittbuf_1
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1 vss m1_2756_6573# vdd3v3 m1_4283_8081# m1_2756_6573#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2 vss m1_6249_7690# vdd3v3 sky130_fd_sc_hvl__schmittbuf_1_0/A
++ m1_2756_6573# sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3 vss m1_185_6573# vdd3v3 m1_502_7653# m1_185_6573#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0 vss vdd3v3 vdd3v3 m1_6249_7690# m1_4283_8081#
++ sky130_fd_pr__pfet_g5v0d10v5_YUHPXE
+Xsky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0 m1_721_6815# vss m1_2756_6573# vss sky130_fd_pr__nfet_g5v0d10v5_PKVMTM
+Xsky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1 li_2550_5813# vss m1_185_6573# vss sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC
+Xsky130_fd_pr__cap_mim_m3_1_WRT4AW_0 vss vss sky130_fd_sc_hvl__schmittbuf_1_0/A sky130_fd_pr__cap_mim_m3_1_WRT4AW
+Xsky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0 vss vdd3v3 m1_4283_8081# vdd3v3 m1_4283_8081#
++ vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 m1_4283_8081# m1_4283_8081#
++ m1_4283_8081# m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YEUEBV
+Xsky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0 vss vdd3v3 vdd3v3 m1_2993_7658# m1_502_7653#
++ sky130_fd_pr__pfet_g5v0d10v5_YUHPBG
+Xsky130_fd_sc_hvl__inv_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd1v8 vdd1v8 por_l
++ sky130_fd_sc_hvl__inv_8
+Xsky130_fd_sc_hvl__buf_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd3v3 vdd3v3 porb_h
++ sky130_fd_sc_hvl__buf_8
+.ends
+
diff --git a/netgen/run_lvs_por.sh b/netgen/run_lvs_por.sh
new file mode 100644
index 0000000..1d1ad9f
--- /dev/null
+++ b/netgen/run_lvs_por.sh
@@ -0,0 +1,24 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the example_por layout
+#
+# NOTE: By specifying the testbench for the schematic-side netlist, the proper
+# includes used by the testbench simulation are picked up. Otherwise, the LVS
+# itself compares just the simple_por subcircuit from the testbench.
+#--------------------------------------------------------------------------------
+netgen -batch lvs "example_por.spice example_por" "../xschem/example_por_tb.spice example_por" /usr/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/run_lvs_wrapper_verilog.sh b/netgen/run_lvs_wrapper_verilog.sh
new file mode 100644
index 0000000..e54f6f6
--- /dev/null
+++ b/netgen/run_lvs_wrapper_verilog.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the user_analog_project_wrapper layout, comparing against the
+# top-level verilog module.
+#
+#--------------------------------------------------------------------------------
+netgen -batch lvs "user_analog_project_wrapper.spice user_analog_project_wrapper" "../verilog/rtl/user_analog_project_wrapper.v user_analog_project_wrapper" /usr/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/run_lvs_wrapper_xschem.sh b/netgen/run_lvs_wrapper_xschem.sh
new file mode 100644
index 0000000..2e5828c
--- /dev/null
+++ b/netgen/run_lvs_wrapper_xschem.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the user_analog_project_wrapper layout, comparing against the
+# top-level xschem subcircuit from the wrapper testbench.
+#
+#--------------------------------------------------------------------------------
+netgen -batch lvs "user_analog_project_wrapper.spice user_analog_project_wrapper" "../xschem/analog_wrapper_tb.spice user_analog_project_wrapper" /usr/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..db4f39d
--- /dev/null
+++ b/netgen/user_analog_project_wrapper.spice
@@ -0,0 +1,330 @@
+* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_2_W5U4AW VSUBS m4_n3179_n3100# c2_n3079_n3000#
+X0 c2_n3079_n3000# m4_n3179_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_sc_hvl__buf_8 A VGND VNB VPB VPWR X
+X0 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=2.9175e+12p pd=2.189e+07u as=8.475e+11p ps=7.13e+06u w=1.5e+06u l=500000u
+X1 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=1.45875e+12p pd=1.289e+07u as=8.4e+11p ps=8.24e+06u w=750000u l=500000u
+X2 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=1.68e+12p ps=1.424e+07u w=1.5e+06u l=500000u
+X3 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X4 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X5 a_45_443# A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=4.2375e+11p pd=4.13e+06u as=0p ps=0u w=750000u l=500000u
+X6 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X7 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X8 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X9 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X10 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X11 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X12 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X13 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X14 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X15 a_45_443# A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X16 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X17 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X18 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X19 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X20 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X21 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ VSUBS a_n465_n200# a_n247_n200# a_n29_n200#
++ a_843_n200# w_n1101_n497# a_n843_n297# a_625_n200# a_683_n297# a_n625_n297# a_407_n200#
++ a_465_n297# a_n407_n297# a_247_n297# a_n901_n200# a_189_n200# a_29_n297# a_n189_n297#
++ a_n683_n200#
+X0 a_407_n200# a_247_n297# a_189_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X1 a_843_n200# a_683_n297# a_625_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X2 a_n465_n200# a_n625_n297# a_n683_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X3 a_189_n200# a_29_n297# a_n29_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X4 a_625_n200# a_465_n297# a_407_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X5 a_n247_n200# a_n407_n297# a_n465_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
+X6 a_n683_n200# a_n843_n297# a_n901_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X7 a_n29_n200# a_n189_n297# a_n247_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_TGFUGS a_n80_n288# a_n574_n200# a_n356_n200#
++ a_n138_n200# a_n734_n288# a_574_n288# a_n516_n288# a_356_n288# a_80_n200# a_n298_n288#
++ a_138_n288# w_n962_n458# a_734_n200# a_516_n200# a_298_n200# a_n792_n200#
+X0 a_516_n200# a_356_n288# a_298_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X1 a_n574_n200# a_n734_n288# a_n792_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X2 a_298_n200# a_138_n288# a_80_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X3 a_80_n200# a_n80_n288# a_n138_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X4 a_734_n200# a_574_n288# a_516_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
+X5 a_n356_n200# a_n516_n288# a_n574_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
+X6 a_n138_n200# a_n298_n288# a_n356_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 a_n2578_n2932# a_5142_2500# a_n1034_n2932#
++ a_n262_2500# a_1668_2500# a_n262_n2932# a_n3736_2500# a_3984_n2932# a_n2192_2500#
++ a_3984_2500# a_2440_n2932# a_2440_2500# a_4370_n2932# a_3598_2500# a_2054_2500#
++ a_n4508_n2932# a_510_2500# a_n4122_2500# a_n2964_n2932# a_124_2500# a_n4894_n2932#
++ a_1282_n2932# a_124_n2932# a_n1420_n2932# a_4370_2500# a_n3350_n2932# a_n648_n2932#
++ a_n648_2500# a_n5280_n2932# a_n1420_2500# a_n2964_2500# a_n2578_2500# a_n1034_2500#
++ a_2826_n2932# a_n2192_n2932# a_2826_2500# a_4756_n2932# w_n5446_n3098# a_1282_2500#
++ a_3212_n2932# a_n4894_2500# a_n3350_2500# a_n4508_2500# a_5142_n2932# a_896_2500#
++ a_510_n2932# a_1668_n2932# a_n1806_n2932# a_4756_2500# a_n3736_n2932# a_3598_n2932#
++ a_3212_2500# a_2054_n2932# a_896_n2932# a_n5280_2500# a_n4122_n2932# a_n1806_2500#
+X0 a_n3350_n2932# a_n3350_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X1 a_n4508_n2932# a_n4508_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X2 a_n2578_n2932# a_n2578_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X3 a_n1420_n2932# a_n1420_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X4 a_n4894_n2932# a_n4894_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X5 a_n3736_n2932# a_n3736_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X6 a_3598_n2932# a_3598_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X7 a_124_n2932# a_124_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X8 a_4756_n2932# a_4756_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X9 a_n2964_n2932# a_n2964_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X10 a_1668_n2932# a_1668_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X11 a_n1806_n2932# a_n1806_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X12 a_n648_n2932# a_n648_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X13 a_3984_n2932# a_3984_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X14 a_2826_n2932# a_2826_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X15 a_510_n2932# a_510_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X16 a_n4122_n2932# a_n4122_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X17 a_n2192_n2932# a_n2192_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X18 a_5142_n2932# a_5142_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X19 a_n1034_n2932# a_n1034_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X20 a_2054_n2932# a_2054_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X21 a_4370_n2932# a_4370_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X22 a_3212_n2932# a_3212_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X23 a_1282_n2932# a_1282_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X24 a_n262_n2932# a_n262_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X25 a_n5280_n2932# a_n5280_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X26 a_2440_n2932# a_2440_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X27 a_896_n2932# a_896_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_3YBPVB VSUBS a_n138_n200# w_n338_n497# a_80_n200#
++ a_n80_n297#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_sc_hvl__schmittbuf_1 A VGND VNB VPB VPWR X
+X0 a_64_207# VPWR VPB sky130_fd_pr__res_generic_pd__hv w=290000u l=3.11e+06u
+X1 a_231_463# A a_117_181# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=4.0875e+11p pd=4.09e+06u as=1.9875e+11p ps=2.03e+06u w=750000u l=500000u
+X2 a_217_207# A a_117_181# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=2.289e+11p pd=2.77e+06u as=1.113e+11p ps=1.37e+06u w=420000u l=500000u
+X3 VPWR A a_231_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=1.02225e+12p pd=5.2e+06u as=0p ps=0u w=750000u l=500000u
+X4 a_217_207# a_117_181# a_64_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=1.113e+11p ps=1.37e+06u w=420000u l=500000u
+X5 X a_117_181# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=1.9875e+11p pd=2.03e+06u as=9.478e+11p ps=4.36e+06u w=750000u l=500000u
+X6 a_78_463# VGND VNB sky130_fd_pr__res_generic_nd__hv w=290000u l=1.355e+06u
+X7 X a_117_181# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=3.975e+11p pd=3.53e+06u as=0p ps=0u w=1.5e+06u l=500000u
+X8 VGND A a_217_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
+X9 a_231_463# a_117_181# a_78_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=1.9875e+11p ps=2.03e+06u w=750000u l=500000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPXE VSUBS a_n138_n200# w_n338_n497# a_80_n200#
++ a_n80_n297#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_PKVMTM a_n80_n288# a_n138_n200# a_80_n200# w_n308_n458#
+X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC a_n80_n288# a_n138_n200# a_80_n200# w_n308_n458#
+X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WRT4AW VSUBS m3_n3136_n3100# c1_n3036_n3000#
+X0 c1_n3036_n3000# m3_n3136_n3100# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YEUEBV VSUBS w_n992_n497# a_n574_n200# a_n356_n200#
++ a_n138_n200# a_80_n200# a_n80_n297# a_734_n200# a_n734_n297# a_516_n200# a_574_n297#
++ a_n516_n297# a_356_n297# a_298_n200# a_n298_n297# a_138_n297# a_n792_n200#
+X0 a_734_n200# a_574_n297# a_516_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X1 a_n356_n200# a_n516_n297# a_n574_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X2 a_n138_n200# a_n298_n297# a_n356_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
+X3 a_516_n200# a_356_n297# a_298_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X4 a_n574_n200# a_n734_n297# a_n792_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X5 a_298_n200# a_138_n297# a_80_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X6 a_80_n200# a_n80_n297# a_n138_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPBG VSUBS a_n138_n200# w_n338_n497# a_80_n200#
++ a_n80_n297#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_sc_hvl__inv_8 A VGND VNB VPB VPWR Y
+X0 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=1.68e+12p pd=1.424e+07u as=2.055e+12p ps=1.774e+07u w=1.5e+06u l=500000u
+X1 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=8.4e+11p pd=8.24e+06u as=1.14e+12p ps=1.054e+07u w=750000u l=500000u
+X2 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X3 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X4 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X5 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X6 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X7 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X8 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X9 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X10 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X11 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X12 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X13 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X14 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X15 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+.ends
+
+.subckt example_por vdd3v3 vdd1v8 vss porb_h por_l porb_l
+Xsky130_fd_pr__cap_mim_m3_2_W5U4AW_0 vss sky130_fd_sc_hvl__schmittbuf_1_0/A vss sky130_fd_pr__cap_mim_m3_2_W5U4AW
+Xsky130_fd_sc_hvl__buf_8_1 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd1v8 vdd1v8 porb_l
++ sky130_fd_sc_hvl__buf_8
+Xsky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0 vss vdd3v3 m1_502_7653# vdd3v3 vdd3v3 vdd3v3
++ m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653#
++ m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653# sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ
+Xsky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0 m1_721_6815# vss m1_721_6815# vss m1_721_6815#
++ m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# vss
++ vss m1_721_6815# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_TGFUGS
+Xsky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0 li_2935_165# vss li_4479_165# li_4866_5813#
++ li_7182_5813# li_5251_165# li_1778_5813# li_9111_165# li_3322_5813# li_9498_5813#
++ li_7567_165# li_7954_5813# li_9883_165# li_8726_5813# li_7182_5813# li_619_165#
++ li_5638_5813# li_1006_5813# li_2163_165# li_5638_5813# li_619_165# li_6795_165#
++ li_5251_165# li_3707_165# li_9498_5813# li_2163_165# li_4479_165# li_4866_5813#
++ vss li_4094_5813# li_2550_5813# li_2550_5813# li_4094_5813# li_8339_165# li_2935_165#
++ li_7954_5813# li_9883_165# vss li_6410_5813# li_8339_165# vss li_1778_5813# li_1006_5813#
++ vss li_6410_5813# li_6023_165# li_6795_165# li_3707_165# vdd3v3 li_1391_165# li_9111_165#
++ li_8726_5813# li_7567_165# li_6023_165# vss li_1391_165# li_3322_5813# sky130_fd_pr__res_xhigh_po_0p69_S5N9F3
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0 vss m1_2993_7658# vdd3v3 m1_721_6815# m1_185_6573#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_sc_hvl__schmittbuf_1_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss vss vdd3v3
++ vdd3v3 sky130_fd_sc_hvl__inv_8_0/A sky130_fd_sc_hvl__schmittbuf_1
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1 vss m1_2756_6573# vdd3v3 m1_4283_8081# m1_2756_6573#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2 vss m1_6249_7690# vdd3v3 sky130_fd_sc_hvl__schmittbuf_1_0/A
++ m1_2756_6573# sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3 vss m1_185_6573# vdd3v3 m1_502_7653# m1_185_6573#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0 vss vdd3v3 vdd3v3 m1_6249_7690# m1_4283_8081#
++ sky130_fd_pr__pfet_g5v0d10v5_YUHPXE
+Xsky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0 m1_721_6815# vss m1_2756_6573# vss sky130_fd_pr__nfet_g5v0d10v5_PKVMTM
+Xsky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1 li_2550_5813# vss m1_185_6573# vss sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC
+Xsky130_fd_pr__cap_mim_m3_1_WRT4AW_0 vss vss sky130_fd_sc_hvl__schmittbuf_1_0/A sky130_fd_pr__cap_mim_m3_1_WRT4AW
+Xsky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0 vss vdd3v3 m1_4283_8081# vdd3v3 m1_4283_8081#
++ vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 m1_4283_8081# m1_4283_8081#
++ m1_4283_8081# m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YEUEBV
+Xsky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0 vss vdd3v3 vdd3v3 m1_2993_7658# m1_502_7653#
++ sky130_fd_pr__pfet_g5v0d10v5_YUHPBG
+Xsky130_fd_sc_hvl__inv_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd1v8 vdd1v8 por_l
++ sky130_fd_sc_hvl__inv_8
+Xsky130_fd_sc_hvl__buf_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd3v3 vdd3v3 porb_h
++ sky130_fd_sc_hvl__buf_8
+.ends
+
+.subckt user_analog_proj_example VSUBS example_por_1/vdd1v8 example_por_0/vdd1v8 example_por_0/porb_h
++ example_por_0/porb_l example_por_1/porb_h example_por_0/vdd3v3 example_por_1/porb_l
++ example_por_1/vdd3v3 example_por_1/por_l example_por_0/por_l
+Xexample_por_0 example_por_0/vdd3v3 example_por_0/vdd1v8 VSUBS example_por_0/porb_h
++ example_por_0/por_l example_por_0/porb_l example_por
+Xexample_por_1 example_por_1/vdd3v3 example_por_1/vdd1v8 VSUBS example_por_1/porb_h
++ example_por_1/por_l example_por_1/porb_l example_por
+.ends
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[7] io_analog[8] io_analog[9] io_analog[5]
++ io_analog[6] io_clamp_high[0] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14]
++ io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22]
++ io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] io_in[6]
++ io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[13] io_oeb[14] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21]
++ io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4]
++ io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8] io_oeb[9] io_out[0] io_out[10] io_out[11]
++ io_out[12] io_out[13] io_out[14] io_out[15] io_out[16] io_out[17] io_out[18] io_out[19]
++ io_out[1] io_out[20] io_out[21] io_out[22] io_out[23] io_out[24] io_out[25] io_out[26]
++ io_out[2] io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8] io_out[9]
++ la_data_in[0] la_data_in[100] la_data_in[101] la_data_in[102] la_data_in[103] la_data_in[104]
++ la_data_in[105] la_data_in[106] la_data_in[107] la_data_in[108] la_data_in[109]
++ la_data_in[10] la_data_in[110] la_data_in[111] la_data_in[112] la_data_in[113] la_data_in[114]
++ la_data_in[115] la_data_in[116] la_data_in[117] la_data_in[118] la_data_in[119]
++ la_data_in[11] la_data_in[120] la_data_in[121] la_data_in[122] la_data_in[123] la_data_in[124]
++ la_data_in[125] la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14]
++ la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1]
++ la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25]
++ la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30]
++ la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36]
++ la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41]
++ la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47]
++ la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52]
++ la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58]
++ la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63]
++ la_data_in[64] la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69]
++ la_data_in[6] la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74]
++ la_data_in[75] la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7]
++ la_data_in[80] la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85]
++ la_data_in[86] la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90]
++ la_data_in[91] la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96]
++ la_data_in[97] la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100]
++ la_data_out[101] la_data_out[102] la_data_out[103] la_data_out[104] la_data_out[105]
++ la_data_out[106] la_data_out[107] la_data_out[108] la_data_out[109] la_data_out[10]
++ la_data_out[110] la_data_out[111] la_data_out[112] la_data_out[113] la_data_out[114]
++ la_data_out[115] la_data_out[116] la_data_out[117] la_data_out[118] la_data_out[119]
++ la_data_out[11] la_data_out[120] la_data_out[121] la_data_out[122] la_data_out[123]
++ la_data_out[124] la_data_out[125] la_data_out[126] la_data_out[127] la_data_out[12]
++ la_data_out[13] la_data_out[14] la_data_out[15] la_data_out[16] la_data_out[17]
++ la_data_out[18] la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22]
++ la_data_out[23] la_data_out[24] la_data_out[25] la_data_out[26] la_data_out[27]
++ la_data_out[28] la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32]
++ la_data_out[33] la_data_out[34] la_data_out[35] la_data_out[36] la_data_out[37]
++ la_data_out[38] la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42]
++ la_data_out[43] la_data_out[44] la_data_out[45] la_data_out[46] la_data_out[47]
++ la_data_out[48] la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52]
++ la_data_out[53] la_data_out[54] la_data_out[55] la_data_out[56] la_data_out[57]
++ la_data_out[58] la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62]
++ la_data_out[63] la_data_out[64] la_data_out[65] la_data_out[66] la_data_out[67]
++ la_data_out[68] la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72]
++ la_data_out[73] la_data_out[74] la_data_out[75] la_data_out[76] la_data_out[77]
++ la_data_out[78] la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82]
++ la_data_out[83] la_data_out[84] la_data_out[85] la_data_out[86] la_data_out[87]
++ la_data_out[88] la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92]
++ la_data_out[93] la_data_out[94] la_data_out[95] la_data_out[96] la_data_out[97]
++ la_data_out[98] la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101]
++ la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108]
++ la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114]
++ la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120]
++ la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127]
++ la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18]
++ la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24]
++ la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30]
++ la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37]
++ la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43]
++ la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4]
++ la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56]
++ la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62]
++ la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69]
++ la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75]
++ la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81]
++ la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88]
++ la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94]
++ la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9] user_clock2
++ user_irq[0] user_irq[1] user_irq[2] vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2
++ wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12]
++ wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18]
++ wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23]
++ wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29]
++ wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5]
++ wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10]
++ wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15] wbs_dat_i[16]
++ wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1] wbs_dat_i[20] wbs_dat_i[21]
++ wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26] wbs_dat_i[27]
++ wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30] wbs_dat_i[31] wbs_dat_i[3]
++ wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9] wbs_dat_o[0]
++ wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14] wbs_dat_o[15]
++ wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1] wbs_dat_o[20]
++ wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25] wbs_dat_o[26]
++ wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30] wbs_dat_o[31]
++ wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9]
++ wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
+Xuser_analog_proj_example_0 vssa1 vccd1 vccd1 gpio_analog[7] io_out[15] gpio_analog[3]
++ io_clamp_high[0] io_out[11] vdda1 io_out[12] io_out[16] user_analog_proj_example
+.ends
+
diff --git a/openlane/.gitignore b/openlane/.gitignore
new file mode 100644
index 0000000..e4867d8
--- /dev/null
+++ b/openlane/.gitignore
@@ -0,0 +1,2 @@
+*/runs
+default.cvcrc
diff --git a/openlane/Makefile b/openlane/Makefile
new file mode 100644
index 0000000..0dbb3a1
--- /dev/null
+++ b/openlane/Makefile
@@ -0,0 +1,85 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+BLOCKS = $(shell find * -maxdepth 0 -type d)
+CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
+CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
+
+OPENLANE_TAG ?= v0.15
+OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
+OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
+OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl"
+
+all: $(BLOCKS)
+
+$(CONFIG) :
+ @echo "Missing $@. Please create a configuration for that design"
+ @exit 1
+
+$(BLOCKS) : % : ./%/config.tcl FORCE
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
+ifeq ($(PDK_ROOT),)
+ @echo "Please export PDK_ROOT"
+ @exit 1
+endif
+ @echo "###############################################"
+ @sleep 1
+
+ @if [ -f ./$*/interactive.tcl ]; then\
+ docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -v $(PWD)/..:/project \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
+ else\
+ docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -v $(PWD)/..:/project \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
+ fi
+ mkdir -p ../signoff/$*/
+ cp $*/runs/$*/OPENLANE_VERSION ../signoff/$*/
+ cp $*/runs/$*/PDK_SOURCES ../signoff/$*/
+ cp $*/runs/$*/reports/final_summary_report.csv ../signoff/$*/
+
+.PHONY: openlane
+openlane:
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
+ git clone https://github.com/efabless/openlane.git --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
+ cd $(OPENLANE_ROOT) && \
+ make openlane
+
+FORCE:
+
+clean:
+ @echo "Use clean_all to clean everything :)"
+
+clean_all: $(CLEAN)
+
+$(CLEAN): clean-% :
+ rm -rf runs/$*
+ rm -rf ../gds/$**
+ rm -rf ../mag/$**
+ rm -rf ../lef/$**
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
new file mode 100644
index 0000000..a9c2027
--- /dev/null
+++ b/verilog/dv/Makefile
@@ -0,0 +1,39 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = mprj_por
+
+all: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ done
+
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+$(DV_PATTERNS): verify-% :
+ cd $* && make
+
+clean: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make clean ) ; \
+ done
+ rm -rf *.log
+
+.PHONY: clean all
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
new file mode 100644
index 0000000..6be9cd3
--- /dev/null
+++ b/verilog/dv/README.md
@@ -0,0 +1,131 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+
+# Simulation Environment Setup
+
+There are two options for setting up the simulation environment:
+
+* Pulling a pre-built docker image
+* Installing the dependecies locally
+
+## 1. Docker
+
+There is an available docker setup with the needed tools at [efabless/dockerized-verification-setup](https://github.com/efabless/dockerized-verification-setup)
+
+Run the following to pull the image:
+
+```
+docker pull efabless/dv_setup:latest
+```
+
+## 2. Local Installion (Linux)
+
+You will need to fullfil these dependecies:
+
+* Icarus Verilog (10.2+)
+* RV32I Toolchain
+
+Using apt, you can install Icarus Verilog:
+
+```bash
+sudo apt-get install iverilog
+```
+
+Next, you will need to build the RV32I toolchain. Firstly, export the installation path for the RV32I toolchain,
+
+```bash
+export GCC_PATH=<gcc-installation-path>
+```
+
+Then, run the following:
+
+```bash
+# packages needed:
+sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \
+ libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo \
+ gperf libtool patchutils bc zlib1g-dev git libexpat1-dev
+
+sudo mkdir $GCC_PATH
+sudo chown $USER $GCC_PATH
+
+git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
+cd riscv-gnu-toolchain-rv32i
+git checkout 411d134
+git submodule update --init --recursive
+
+mkdir build; cd build
+../configure --with-arch=rv32i --prefix=$GCC_PATH
+make -j$(nproc)
+```
+
+# Running Simulation
+
+## Docker
+
+First, you will need to export a number of environment variables:
+
+```bash
+export PDK_PATH=<pdk-location/sky130A>
+export CARAVEL_ROOT=<caravel_root>
+export UPRJ_ROOT=<user_project_root>
+```
+
+Then, run the following command to start the docker container :
+
+```
+docker run -it -v $CARAVEL_ROOT:$CARAVEL_ROOT -v $PDK_PATH:$PDK_PATH -v $UPRJ_ROOT:$UPRJ_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -e PDK_PATH=$PDK_PATH -e UPRJ_ROOT=$UPRJ_ROOT -u $(id -u $USER):$(id -g $USER) efabless/dv_setup:latest
+```
+
+Then, navigate to the directory where the DV tests reside :
+
+```bash
+cd $UPRJ_ROOT/verilog/dv/
+```
+
+Then, follow the instructions at [Both](#both) to run RTL/GL simulation.
+
+## Local
+
+You will need to export these environment variables:
+
+```bash
+export GCC_PATH=<gcc-installation-path>
+export PDK_PATH=<pdk-location/sky130A>
+```
+
+Then, follow the instruction at [Both](#both) to run RTL/GL simulation.
+
+## Both
+
+To run RTL simulation for one of the DV tests,
+
+```bash
+cd <dv-test>
+make
+```
+
+To run gate level simulation for one of the DV tests,
+
+```bash
+cd <dv-test>
+SIM=GL make
+```
+
+# User Analog Project Example DV
+
+> :construction: Under construction :construction:
diff --git a/verilog/dv/mprj_por/Makefile b/verilog/dv/mprj_por/Makefile
new file mode 100644
index 0000000..e54380b
--- /dev/null
+++ b/verilog/dv/mprj_por/Makefile
@@ -0,0 +1,78 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mprj_por
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/mprj_por/mprj_por.c b/verilog/dv/mprj_por/mprj_por.c
new file mode 100644
index 0000000..9a51fc5
--- /dev/null
+++ b/verilog/dv/mprj_por/mprj_por.c
@@ -0,0 +1,49 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+
+// --------------------------------------------------------
+
+void main()
+{
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2
+
+ reg_mprj_datal = 0x00000000;
+ reg_mprj_datah = 0x00000000;
+
+ // Configure mprj_io 10 and 25 as analog (digital in/out = off)
+ // Configure mprj_io 11, 12, 26, and 27 as digital output
+ // mprj_io 14 to 24 are analog pads and cannot be configured
+
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_ANALOG;
+
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_ANALOG;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Block until end of test */
+ while (1);
+}
+
diff --git a/verilog/dv/mprj_por/mprj_por_tb.v b/verilog/dv/mprj_por/mprj_por_tb.v
new file mode 100644
index 0000000..39e4a36
--- /dev/null
+++ b/verilog/dv/mprj_por/mprj_por_tb.v
@@ -0,0 +1,170 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_analog_netlists.v"
+`include "caravan_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module mprj_por_tb;
+ // Signals declaration
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg power3;
+
+ wire HIGH;
+ wire LOW;
+ wire TRI;
+ assign HIGH = 1'b1;
+ assign LOW = 1'b0;
+ assign TRI = 1'bz;
+
+ wire gpio;
+ wire uart_tx;
+ wire [37:0] mprj_io;
+ wire [3:0] checkbits;
+ wire [1:0] status;
+
+ // Signals Assignment
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // Power supply for POR
+ assign mprj_io[18] = power3;
+
+ // Readback from POR (digital HV through analog pad connection)
+ assign status = {mprj_io[25], mprj_io[10]};
+
+ // Readback from POR (digital LV)
+ assign checkbits = {mprj_io[27:26], mprj_io[12:11]};
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("mprj_por.vcd");
+ $dumpvars(0, mprj_por_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (150) begin
+ repeat (1000) @(posedge clock);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ wait(status == 2'h1);
+ $display("Monitor: mprj_por test started");
+ #100;
+ if (checkbits != 4'h9) begin
+ $display("Monitor: mprj_por test failed");
+ $finish;
+ end
+ wait(status == 2'h3);
+ #100;
+ if (checkbits != 4'h5) begin
+ $display("Monitor: mprj_por test failed");
+ $finish;
+ end
+ $display("Monitor: mprj_por test Passed");
+ #10000;
+ $finish;
+ end
+
+ // Reset Operation
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ #150000; // Need time to run the managment SoC setup.
+ power3 <= 1'b1; // Power up the 2nd POR.
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire VSS = 1'b0;
+
+ caravan uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+
+ spiflash #(
+ .FILENAME("mprj_por.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/example_por.v b/verilog/rtl/example_por.v
new file mode 100644
index 0000000..d318fba
--- /dev/null
+++ b/verilog/rtl/example_por.v
@@ -0,0 +1,95 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+// This is just a copy of simple_por.v from the Caravel project, used
+// as an analog user project example.
+
+module example_por(
+`ifdef USE_POWER_PINS
+ inout vdd3v3,
+ inout vdd1v8,
+ inout vss,
+`endif
+ output porb_h,
+ output porb_l,
+ output por_l
+);
+
+ wire mid, porb_h;
+ reg inode;
+
+ // This is a behavioral model! Actual circuit is a resitor dumping
+ // current (slowly) from vdd3v3 onto a capacitor, and this fed into
+ // two schmitt triggers for strong hysteresis/glitch tolerance.
+
+ initial begin
+ inode <= 1'b0;
+ end
+
+ // Emulate current source on capacitor as a 500ns delay either up or
+ // down. Note that this is sped way up for verilog simulation; the
+ // actual circuit is set to a 15ms delay.
+
+ always @(posedge vdd3v3) begin
+ #500 inode <= 1'b1;
+ end
+ always @(negedge vdd3v3) begin
+ #500 inode <= 1'b0;
+ end
+
+ // Instantiate two shmitt trigger buffers in series
+
+ sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VGND(vss),
+ .VPB(vdd3v3),
+ .VNB(vss),
+`endif
+ .A(inode),
+ .X(mid)
+ );
+
+ sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VGND(vss),
+ .VPB(vdd3v3),
+ .VNB(vss),
+`endif
+ .A(mid),
+ .X(porb_h)
+ );
+
+ sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VPB(vdd3v3),
+ .LVPWR(vdd1v8),
+ .VNB(vss),
+ .VGND(vss),
+`endif
+ .A(porb_h),
+ .X(porb_l)
+ );
+
+ // since this is behavioral anyway, but this should be
+ // replaced by a proper inverter
+ assign por_l = ~porb_l;
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/uprj_analog_netlists.v b/verilog/rtl/uprj_analog_netlists.v
new file mode 100644
index 0000000..46c2606
--- /dev/null
+++ b/verilog/rtl/uprj_analog_netlists.v
@@ -0,0 +1,37 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130 */
+/* fabrication process and open source PDK */
+/* */
+/* Copyright 2020 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/*--------------------------------------------------------------*/
+
+`include "defines.v"
+`define USE_POWER_PINS
+
+`ifdef GL
+ `default_nettype wire
+ `include "gl/user_analog_project_wrapper.v"
+ `include "gl/user_analog_proj_example.v"
+`else
+ `include "user_analog_project_wrapper.v"
+ `include "user_analog_proj_example.v"
+`endif
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v
new file mode 100644
index 0000000..94412da
--- /dev/null
+++ b/verilog/rtl/user_analog_proj_example.v
@@ -0,0 +1,221 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`include "example_por.v"
+
+/*
+ * I/O mapping for analog
+ *
+ * mprj_io[37] io_in/out/oeb/in_3v3[26] --- ---
+ * mprj_io[36] io_in/out/oeb/in_3v3[25] --- ---
+ * mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] ---
+ * mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] ---
+ * mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] ---
+ * mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] ---
+ * mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] ---
+ * mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] ---
+ * mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] ---
+ * mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] ---
+ * mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] ---
+ * mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] ---
+ * mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] ---
+ * mprj_io[24] --- --- user_analog[10]
+ * mprj_io[23] --- --- user_analog[9]
+ * mprj_io[22] --- --- user_analog[8]
+ * mprj_io[21] --- --- user_analog[7]
+ * mprj_io[20] --- --- user_analog[6] clamp[2]
+ * mprj_io[19] --- --- user_analog[5] clamp[1]
+ * mprj_io[18] --- --- user_analog[4] clamp[0]
+ * mprj_io[17] --- --- user_analog[3]
+ * mprj_io[16] --- --- user_analog[2]
+ * mprj_io[15] --- --- user_analog[1]
+ * mprj_io[14] --- --- user_analog[0]
+ * mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] ---
+ * mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] ---
+ * mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] ---
+ * mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] ---
+ * mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] ---
+ * mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] ---
+ * mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] ---
+ * mprj_io[6] io_in/out/oeb/in_3v3[6] --- ---
+ * mprj_io[5] io_in/out/oeb/in_3v3[5] --- ---
+ * mprj_io[4] io_in/out/oeb/in_3v3[4] --- ---
+ * mprj_io[3] io_in/out/oeb/in_3v3[3] --- ---
+ * mprj_io[2] io_in/out/oeb/in_3v3[2] --- ---
+ * mprj_io[1] io_in/out/oeb/in_3v3[1] --- ---
+ * mprj_io[0] io_in/out/oeb/in_3v3[0] --- ---
+ *
+ */
+
+/*
+ *----------------------------------------------------------------
+ *
+ * user_analog_proj_example
+ *
+ * This is an example of a (trivially simple) analog user project,
+ * showing how the user project can connect to the I/O pads, both
+ * the digital pads, the analog connection on the digital pads,
+ * and the dedicated analog pins used as an additional power supply
+ * input, with a connected ESD clamp.
+ *
+ * See the testbench in directory "mprj_por" for the example
+ * program that drives this user project.
+ *
+ *----------------------------------------------------------------
+ */
+
+module user_analog_proj_example (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ // GPIO-analog
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ // Dedicated analog
+ inout [`ANALOG_PADS-1:0] io_analog,
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Clock
+ input user_clock2,
+
+ // IRQ
+ output [2:0] irq
+);
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
+ wire [`ANALOG_PADS-1:0] io_analog;
+
+ // wire [31:0] rdata;
+ // wire [31:0] wdata;
+
+ // wire valid;
+ // wire [3:0] wstrb;
+
+ wire isupply; // Independent 3.3V supply
+ wire io16, io15, io12, io11;
+
+ // WB MI A
+ // assign valid = wbs_cyc_i && wbs_stb_i;
+ // assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+ // assign wbs_dat_o = rdata;
+ // assign wdata = wbs_dat_i;
+
+ // IO --- unused (no need to connect to anything)
+ // assign io_out[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = 0;
+ // assign io_out[14:13] = 11'b0;
+ // assign io_out[10:0] = 11'b0;
+
+ // assign io_oeb[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = -1;
+ // assign io_oeb[14:13] = 11'b1;
+ // assign io_oeb[10:0] = 11'b1;
+
+ // IO --- enable outputs on 11, 12, 15, and 16
+ assign io_out[12:11] = {io12, io11};
+ assign io_oeb[12:11] = {vssd1, vssd1};
+
+ assign io_out[16:15] = {io16, io15};
+ assign io_oeb[16:15] = {vssd1, vssd1};
+
+ // IRQ
+ assign irq = 3'b000; // Unused
+
+ // LA --- unused (no need to connect to anything)
+ // assign la_data_out = {128{1'b0}}; // Unused
+
+ // Instantiate the POR. Connect the digital power to user area 1
+ // VCCD, and connect the analog power to user area 1 VDDA.
+
+ // Monitor the 3.3V output with mprj_io[10] = gpio_analog[3]
+ // Monitor the 1.8V outputs with mprj_io[11,12] = io_out[11,12]
+
+ example_por por1 (
+ `ifdef USE_POWER_PINS
+ .vdd3v3(vdda1),
+ .vdd1v8(vccd1),
+ .vss(vssa1),
+ `endif
+ .porb_h(gpio_analog[3]), // 3.3V domain output
+ .porb_l(io11), // 1.8V domain output
+ .por_l(io12) // 1.8V domain output
+ );
+
+ // Instantiate 2nd POR with the analog power supply on one of the
+ // analog pins. NOTE: io_analog[4] = mproj_io[18] and is the same
+ // pad with io_clamp_high/low[0].
+
+ `ifdef USE_POWER_PINS
+ assign isupply = io_analog[4];
+ assign io_clamp_high[0] = isupply;
+ assign io_clamp_low[0] = vssa1;
+
+ // Tie off remaining clamps
+ assign io_clamp_high[2:1] = vssa1;
+ assign io_clamp_low[2:1] = vssa1;
+ `endif
+
+ // Monitor the 3.3V output with mprj_io[25] = gpio_analog[7]
+ // Monitor the 1.8V outputs with mprj_io[26,27] = io_out[15,16]
+
+ example_por por2 (
+ `ifdef USE_POWER_PINS
+ .vdd3v3(isupply),
+ .vdd1v8(vccd1),
+ .vss(vssa1),
+ `endif
+ .porb_h(gpio_analog[7]), // 3.3V domain output
+ .porb_l(io15), // 1.8V domain output
+ .por_l(io16) // 1.8V domain output
+ );
+
+endmodule
+
+`default_nettype wire
diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v
new file mode 100644
index 0000000..a4a8c1a
--- /dev/null
+++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -0,0 +1,181 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_analog_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user analog project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_analog_project_wrapper (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ /* GPIOs. There are 27 GPIOs, on either side of the analog.
+ * These have the following mapping to the GPIO padframe pins
+ * and memory-mapped registers, since the numbering remains the
+ * same as caravel but skips over the analog I/O:
+ *
+ * io_in/out/oeb/in_3v3 [26:14] <---> mprj_io[37:25]
+ * io_in/out/oeb/in_3v3 [13:0] <---> mprj_io[13:0]
+ *
+ * When the GPIOs are configured by the Management SoC for
+ * user use, they have three basic bidirectional controls:
+ * in, out, and oeb (output enable, sense inverted). For
+ * analog projects, a 3.3V copy of the signal input is
+ * available. out and oeb must be 1.8V signals.
+ */
+
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ /* Analog (direct connection to GPIO pad---not for high voltage or
+ * high frequency use). The management SoC must turn off both
+ * input and output buffers on these GPIOs to allow analog access.
+ * These signals may drive a voltage up to the value of VDDIO
+ * (3.3V typical, 5.5V maximum).
+ *
+ * Note that analog I/O is not available on the 7 lowest-numbered
+ * GPIO pads, and so the analog_io indexing is offset from the
+ * GPIO indexing by 7, as follows:
+ *
+ * gpio_analog/noesd [17:7] <---> mprj_io[35:25]
+ * gpio_analog/noesd [6:0] <---> mprj_io[13:7]
+ *
+ */
+
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ /* Analog signals, direct through to pad. These have no ESD at all,
+ * so ESD protection is the responsibility of the designer.
+ *
+ * user_analog[10:0] <---> mprj_io[24:14]
+ *
+ */
+ inout [`ANALOG_PADS-1:0] io_analog,
+
+ /* Additional power supply ESD clamps, one per analog pad. The
+ * high side should be connected to a 3.3-5.5V power supply.
+ * The low side should be connected to ground.
+ *
+ * clamp_high[2:0] <---> mprj_io[20:18]
+ * clamp_low[2:0] <---> mprj_io[20:18]
+ *
+ */
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated here */
+/*--------------------------------------*/
+
+user_analog_proj_example mprj (
+ `ifdef USE_POWER_PINS
+ .vdda1(vdda1), // User area 1 3.3V power
+ .vdda2(vdda2), // User area 2 3.3V power
+ .vssa1(vssa1), // User area 1 analog ground
+ .vssa2(vssa2), // User area 2 analog ground
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vccd2(vccd2), // User area 2 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+ .vssd2(vssd2), // User area 2 digital ground
+ `endif
+
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ // MGMT SoC Wishbone Slave
+
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_sel_i(wbs_sel_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+
+ // Logic Analyzer
+
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oenb (la_oenb),
+
+ // IO Pads
+ .io_in (io_in),
+ .io_in_3v3 (io_in_3v3),
+ .io_out(io_out),
+ .io_oeb(io_oeb),
+
+ // GPIO-analog
+ .gpio_analog(gpio_analog),
+ .gpio_noesd(gpio_noesd),
+
+ // Dedicated analog
+ .io_analog(io_analog),
+ .io_clamp_high(io_clamp_high),
+ .io_clamp_low(io_clamp_low),
+
+ // Clock
+ .user_clock2(user_clock2),
+
+ // IRQ
+ .irq(user_irq)
+);
+
+endmodule // user_analog_project_wrapper
+
+`default_nettype wire
diff --git a/xschem/.spiceinit b/xschem/.spiceinit
new file mode 100644
index 0000000..e6a73aa
--- /dev/null
+++ b/xschem/.spiceinit
@@ -0,0 +1,5 @@
+* ngspice initialization for sky130
+* assert BSIM compatibility mode with "nf" vs. "W"
+set ngbehavior=hsa
+* "nomodcheck" speeds up loading time
+set ng_nomodcheck
diff --git a/xschem/analog_wrapper_tb.sch b/xschem/analog_wrapper_tb.sch
new file mode 100644
index 0000000..736a27c
--- /dev/null
+++ b/xschem/analog_wrapper_tb.sch
@@ -0,0 +1,97 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 300 -290 510 -290 { lab=#net1}
+N 590 -290 590 -250 { lab=#net1}
+N 300 -250 430 -250 { lab=GND}
+N 510 -250 510 -150 { lab=GND}
+N 510 -150 780 -150 { lab=GND}
+N 780 -190 780 -150 { lab=GND}
+N 690 -190 690 -150 { lab=GND}
+N 590 -190 590 -150 { lab=GND}
+N 300 -210 400 -210 { lab=#net2}
+N 480 -270 480 -210 { lab=#net2}
+N 480 -270 690 -270 { lab=#net2}
+N 690 -270 690 -250 { lab=#net2}
+N 300 10 450 10 { lab=#net3}
+N 850 -270 850 0 { lab=io_analog[4]}
+N 780 -270 850 -270 { lab=io_analog[4]}
+N 780 -270 780 -250 { lab=io_analog[4]}
+N 300 30 470 30 { lab=io_clamp_high[2:0]}
+N 300 50 410 50 { lab=GND}
+N 550 30 630 30 { lab=io_clamp_high[2:0]}
+N 630 30 630 90 { lab=io_clamp_high[2:0]}
+N 500 160 810 160 { lab=GND}
+N 810 -150 810 160 { lab=GND}
+N 780 -150 810 -150 { lab=GND}
+N 530 10 660 10 { lab=io_analog[10:0]}
+N 510 -290 590 -290 { lab=#net1}
+N 430 -250 510 -250 { lab=GND}
+N 400 -210 480 -210 { lab=#net2}
+N 470 30 550 30 { lab=io_clamp_high[2:0]}
+N 460 10 530 10 { lab=io_analog[10:0]}
+N 410 50 490 50 { lab=io_clamp_low[2:0]}
+N 490 50 490 160 { lab=GND}
+N 490 160 500 160 { lab=GND}
+N 300 -50 620 -50 { lab=io_oeb[26:0]}
+N 300 -70 480 -70 { lab=io_out[26:0]}
+N 520 -150 520 -60 { lab=io_oeb[16:15]}
+N 610 -150 610 -60 { lab=io_oeb[12:11]}
+N 850 -0 850 40 { lab=io_analog[4]}
+N 640 40 810 40 { lab=io_clamp_high[2:1]}
+N 670 0 850 -0 { lab=io_analog[4]}
+N 640 100 850 100 { lab=io_clamp_high[0]}
+N 850 40 850 100 { lab=io_analog[4]}
+N 300 -270 400 -270 { lab=#net4}
+N 300 -230 400 -230 { lab=#net5}
+N 300 -190 400 -190 { lab=#net6}
+N 300 -190 400 -190 { lab=#net6}
+N 300 -170 400 -170 { lab=#net7}
+N 290 -150 390 -150 { lab=#net8}
+N 290 -130 390 -130 { lab=#net9}
+N 290 -110 390 -110 { lab=#net10}
+N 300 -90 400 -90 { lab=#net11}
+N 300 -30 400 -30 { lab=#net12}
+N 300 -10 400 -10 { lab=#net13}
+N 300 70 400 70 { lab=#net14}
+N -60 -290 -0 -290 { lab=#net15}
+N -60 -270 0 -270 { lab=#net16}
+N -60 -250 0 -250 { lab=#net17}
+N -60 -230 0 -230 { lab=#net18}
+N -60 -210 0 -210 { lab=#net19}
+N -60 -210 0 -210 { lab=#net19}
+N -60 -190 0 -190 { lab=#net20}
+N -60 -190 0 -190 { lab=#net20}
+N -60 -170 0 -170 { lab=#net21}
+N -60 -150 0 -150 { lab=#net22}
+N -60 -130 0 -130 { lab=#net23}
+N -60 -110 0 -110 { lab=#net24}
+N -60 -90 0 -90 { lab=#net25}
+N -60 -70 0 -70 { lab=#net26}
+N -60 -50 0 -50 { lab=#net27}
+C {user_analog_project_wrapper.sym} 150 -110 0 0 {name=x1}
+C {devices/vsource.sym} 590 -220 0 0 {name=V1 value="PWL(0.0 0 400u 0 5.4m 3.3)"}
+C {devices/vsource.sym} 690 -220 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3 1.8)"}
+C {devices/vsource.sym} 780 -220 0 0 {name=V3 value="PWL(0.0 0 100u 0 5m 3.3)"}
+C {devices/bus_connect.sym} 660 10 1 1 {name=l1 lab=io_analog[4]}
+C {devices/gnd.sym} 730 -150 0 0 {name=l2 lab=GND}
+C {devices/bus_connect.sym} 630 30 1 0 {name=l3 lab=io_clamp_high[2:1]}
+C {devices/bus_connect.sym} 630 90 1 0 {name=l8 lab=io_clamp_high[0]}
+C {devices/lab_pin.sym} 570 30 0 0 {name=l11 sig_type=std_logic lab=io_clamp_high[2:0]}
+C {devices/lab_pin.sym} 570 10 0 0 {name=l12 sig_type=std_logic lab=io_analog[10:0]}
+C {devices/lab_pin.sym} 480 50 0 0 {name=l9 sig_type=std_logic lab=io_clamp_low[2:0]}
+C {devices/lab_pin.sym} 450 -50 0 0 {name=l4 sig_type=std_logic lab=io_oeb[26:0]}
+C {devices/lab_pin.sym} 450 -70 0 0 {name=l5 sig_type=std_logic lab=io_out[26:0]}
+C {devices/bus_connect.sym} 510 -50 0 0 {name=l6 lab=io_oeb[16:15]}
+C {devices/bus_connect.sym} 600 -50 0 0 {name=l7 lab=io_oeb[12:11]}
+C {devices/code_shown.sym} 920 -130 0 0 {name=s1 only_toplevel=false value=".param mc_mm_switch=0
+.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
+.control
+tran 10u 20m
+plot V(io_out[11]) V(io_out[12]) V(io_out[15]) V(io_out[16])
++ V(gpio_analog[3]) V(gpio_analog[7])
+.endc"}
diff --git a/xschem/analog_wrapper_tb.spice b/xschem/analog_wrapper_tb.spice
new file mode 100644
index 0000000..e28a311
--- /dev/null
+++ b/xschem/analog_wrapper_tb.spice
@@ -0,0 +1,273 @@
+**.subckt analog_wrapper_tb
+x1 net1 net4 GND net5 net2 net6 net7 net8 net15 net16 net17 net18 net19 net20[3] net20[2] net20[1]
++ net20[0] net21[31] net21[30] net21[29] net21[28] net21[27] net21[26] net21[25] net21[24] net21[23] net21[22]
++ net21[21] net21[20] net21[19] net21[18] net21[17] net21[16] net21[15] net21[14] net21[13] net21[12] net21[11]
++ net21[10] net21[9] net21[8] net21[7] net21[6] net21[5] net21[4] net21[3] net21[2] net21[1] net21[0] net22[31]
++ net22[30] net22[29] net22[28] net22[27] net22[26] net22[25] net22[24] net22[23] net22[22] net22[21] net22[20]
++ net22[19] net22[18] net22[17] net22[16] net22[15] net22[14] net22[13] net22[12] net22[11] net22[10] net22[9]
++ net22[8] net22[7] net22[6] net22[5] net22[4] net22[3] net22[2] net22[1] net22[0] net9 net10[31] net10[30]
++ net10[29] net10[28] net10[27] net10[26] net10[25] net10[24] net10[23] net10[22] net10[21] net10[20] net10[19]
++ net10[18] net10[17] net10[16] net10[15] net10[14] net10[13] net10[12] net10[11] net10[10] net10[9] net10[8]
++ net10[7] net10[6] net10[5] net10[4] net10[3] net10[2] net10[1] net10[0] net23[127] net23[126] net23[125]
++ net23[124] net23[123] net23[122] net23[121] net23[120] net23[119] net23[118] net23[117] net23[116] net23[115]
++ net23[114] net23[113] net23[112] net23[111] net23[110] net23[109] net23[108] net23[107] net23[106] net23[105]
++ net23[104] net23[103] net23[102] net23[101] net23[100] net23[99] net23[98] net23[97] net23[96] net23[95]
++ net23[94] net23[93] net23[92] net23[91] net23[90] net23[89] net23[88] net23[87] net23[86] net23[85] net23[84]
++ net23[83] net23[82] net23[81] net23[80] net23[79] net23[78] net23[77] net23[76] net23[75] net23[74] net23[73]
++ net23[72] net23[71] net23[70] net23[69] net23[68] net23[67] net23[66] net23[65] net23[64] net23[63] net23[62]
++ net23[61] net23[60] net23[59] net23[58] net23[57] net23[56] net23[55] net23[54] net23[53] net23[52] net23[51]
++ net23[50] net23[49] net23[48] net23[47] net23[46] net23[45] net23[44] net23[43] net23[42] net23[41] net23[40]
++ net23[39] net23[38] net23[37] net23[36] net23[35] net23[34] net23[33] net23[32] net23[31] net23[30] net23[29]
++ net23[28] net23[27] net23[26] net23[25] net23[24] net23[23] net23[22] net23[21] net23[20] net23[19] net23[18]
++ net23[17] net23[16] net23[15] net23[14] net23[13] net23[12] net23[11] net23[10] net23[9] net23[8] net23[7]
++ net23[6] net23[5] net23[4] net23[3] net23[2] net23[1] net23[0] net11[127] net11[126] net11[125] net11[124]
++ net11[123] net11[122] net11[121] net11[120] net11[119] net11[118] net11[117] net11[116] net11[115] net11[114]
++ net11[113] net11[112] net11[111] net11[110] net11[109] net11[108] net11[107] net11[106] net11[105] net11[104]
++ net11[103] net11[102] net11[101] net11[100] net11[99] net11[98] net11[97] net11[96] net11[95] net11[94]
++ net11[93] net11[92] net11[91] net11[90] net11[89] net11[88] net11[87] net11[86] net11[85] net11[84] net11[83]
++ net11[82] net11[81] net11[80] net11[79] net11[78] net11[77] net11[76] net11[75] net11[74] net11[73] net11[72]
++ net11[71] net11[70] net11[69] net11[68] net11[67] net11[66] net11[65] net11[64] net11[63] net11[62] net11[61]
++ net11[60] net11[59] net11[58] net11[57] net11[56] net11[55] net11[54] net11[53] net11[52] net11[51] net11[50]
++ net11[49] net11[48] net11[47] net11[46] net11[45] net11[44] net11[43] net11[42] net11[41] net11[40] net11[39]
++ net11[38] net11[37] net11[36] net11[35] net11[34] net11[33] net11[32] net11[31] net11[30] net11[29] net11[28]
++ net11[27] net11[26] net11[25] net11[24] net11[23] net11[22] net11[21] net11[20] net11[19] net11[18] net11[17]
++ net11[16] net11[15] net11[14] net11[13] net11[12] net11[11] net11[10] net11[9] net11[8] net11[7] net11[6]
++ net11[5] net11[4] net11[3] net11[2] net11[1] net11[0] net24[127] net24[126] net24[125] net24[124] net24[123]
++ net24[122] net24[121] net24[120] net24[119] net24[118] net24[117] net24[116] net24[115] net24[114] net24[113]
++ net24[112] net24[111] net24[110] net24[109] net24[108] net24[107] net24[106] net24[105] net24[104] net24[103]
++ net24[102] net24[101] net24[100] net24[99] net24[98] net24[97] net24[96] net24[95] net24[94] net24[93]
++ net24[92] net24[91] net24[90] net24[89] net24[88] net24[87] net24[86] net24[85] net24[84] net24[83] net24[82]
++ net24[81] net24[80] net24[79] net24[78] net24[77] net24[76] net24[75] net24[74] net24[73] net24[72] net24[71]
++ net24[70] net24[69] net24[68] net24[67] net24[66] net24[65] net24[64] net24[63] net24[62] net24[61] net24[60]
++ net24[59] net24[58] net24[57] net24[56] net24[55] net24[54] net24[53] net24[52] net24[51] net24[50] net24[49]
++ net24[48] net24[47] net24[46] net24[45] net24[44] net24[43] net24[42] net24[41] net24[40] net24[39] net24[38]
++ net24[37] net24[36] net24[35] net24[34] net24[33] net24[32] net24[31] net24[30] net24[29] net24[28] net24[27]
++ net24[26] net24[25] net24[24] net24[23] net24[22] net24[21] net24[20] net24[19] net24[18] net24[17] net24[16]
++ net24[15] net24[14] net24[13] net24[12] net24[11] net24[10] net24[9] net24[8] net24[7] net24[6] net24[5]
++ net24[4] net24[3] net24[2] net24[1] net24[0] net25[26] net25[25] net25[24] net25[23] net25[22] net25[21]
++ net25[20] net25[19] net25[18] net25[17] net25[16] net25[15] net25[14] net25[13] net25[12] net25[11] net25[10]
++ net25[9] net25[8] net25[7] net25[6] net25[5] net25[4] net25[3] net25[2] net25[1] net25[0] net26[26]
++ net26[25] net26[24] net26[23] net26[22] net26[21] net26[20] net26[19] net26[18] net26[17] net26[16] net26[15]
++ net26[14] net26[13] net26[12] net26[11] net26[10] net26[9] net26[8] net26[7] net26[6] net26[5] net26[4]
++ net26[3] net26[2] net26[1] net26[0] io_out[26] io_out[25] io_out[24] io_out[23] io_out[22] io_out[21]
++ io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15] io_out[14] io_out[13] io_out[12] io_out[11]
++ io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5] io_out[4] io_out[3] io_out[2] io_out[1] io_out[0]
++ io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22] io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17]
++ io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12] io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7]
++ io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2] io_oeb[1] io_oeb[0] net12[17] net12[16] net12[15] net12[14]
++ net12[13] net12[12] net12[11] net12[10] net12[9] net12[8] net12[7] net12[6] net12[5] net12[4] net12[3]
++ net12[2] net12[1] net12[0] net13[17] net13[16] net13[15] net13[14] net13[13] net13[12] net13[11] net13[10]
++ net13[9] net13[8] net13[7] net13[6] net13[5] net13[4] net13[3] net13[2] net13[1] net13[0] net3[10] net3[9]
++ net3[8] net3[7] net3[6] net3[5] net3[4] net3[3] net3[2] net3[1] net3[0] io_clamp_high[2] io_clamp_high[1]
++ io_clamp_high[0] GND GND GND net27 net14[2] net14[1] net14[0] user_analog_project_wrapper
+V1 net1 GND PWL(0.0 0 400u 0 5.4m 3.3)
+V2 net2 GND PWL(0.0 0 300u 0 5.3 1.8)
+V3 io_analog[4] GND PWL(0.0 0 100u 0 5m 3.3)
+**** begin user architecture code
+
+.param mc_mm_switch=0
+.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
+.control
+tran 10u 20m
+plot V(io_out[11]) V(io_out[12]) V(io_out[15]) V(io_out[16]) V(gpio_analog[3]) V(gpio_analog[7])
+.endc
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: user_analog_project_wrapper.sym # of pins=32
+* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/user_analog_project_wrapper.sym
+* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/user_analog_project_wrapper.sch
+.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i
++ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3] wbs_sel_i[2] wbs_sel_i[1] wbs_sel_i[0] wbs_dat_i[31]
++ wbs_dat_i[30] wbs_dat_i[29] wbs_dat_i[28] wbs_dat_i[27] wbs_dat_i[26] wbs_dat_i[25] wbs_dat_i[24] wbs_dat_i[23]
++ wbs_dat_i[22] wbs_dat_i[21] wbs_dat_i[20] wbs_dat_i[19] wbs_dat_i[18] wbs_dat_i[17] wbs_dat_i[16] wbs_dat_i[15]
++ wbs_dat_i[14] wbs_dat_i[13] wbs_dat_i[12] wbs_dat_i[11] wbs_dat_i[10] wbs_dat_i[9] wbs_dat_i[8] wbs_dat_i[7]
++ wbs_dat_i[6] wbs_dat_i[5] wbs_dat_i[4] wbs_dat_i[3] wbs_dat_i[2] wbs_dat_i[1] wbs_dat_i[0] wbs_adr_i[31]
++ wbs_adr_i[30] wbs_adr_i[29] wbs_adr_i[28] wbs_adr_i[27] wbs_adr_i[26] wbs_adr_i[25] wbs_adr_i[24] wbs_adr_i[23]
++ wbs_adr_i[22] wbs_adr_i[21] wbs_adr_i[20] wbs_adr_i[19] wbs_adr_i[18] wbs_adr_i[17] wbs_adr_i[16] wbs_adr_i[15]
++ wbs_adr_i[14] wbs_adr_i[13] wbs_adr_i[12] wbs_adr_i[11] wbs_adr_i[10] wbs_adr_i[9] wbs_adr_i[8] wbs_adr_i[7]
++ wbs_adr_i[6] wbs_adr_i[5] wbs_adr_i[4] wbs_adr_i[3] wbs_adr_i[2] wbs_adr_i[1] wbs_adr_i[0] wbs_ack_o
++ wbs_dat_o[31] wbs_dat_o[30] wbs_dat_o[29] wbs_dat_o[28] wbs_dat_o[27] wbs_dat_o[26] wbs_dat_o[25] wbs_dat_o[24]
++ wbs_dat_o[23] wbs_dat_o[22] wbs_dat_o[21] wbs_dat_o[20] wbs_dat_o[19] wbs_dat_o[18] wbs_dat_o[17] wbs_dat_o[16]
++ wbs_dat_o[15] wbs_dat_o[14] wbs_dat_o[13] wbs_dat_o[12] wbs_dat_o[11] wbs_dat_o[10] wbs_dat_o[9] wbs_dat_o[8]
++ wbs_dat_o[7] wbs_dat_o[6] wbs_dat_o[5] wbs_dat_o[4] wbs_dat_o[3] wbs_dat_o[2] wbs_dat_o[1] wbs_dat_o[0]
++ la_data_in[127] la_data_in[126] la_data_in[125] la_data_in[124] la_data_in[123] la_data_in[122] la_data_in[121]
++ la_data_in[120] la_data_in[119] la_data_in[118] la_data_in[117] la_data_in[116] la_data_in[115] la_data_in[114]
++ la_data_in[113] la_data_in[112] la_data_in[111] la_data_in[110] la_data_in[109] la_data_in[108] la_data_in[107]
++ la_data_in[106] la_data_in[105] la_data_in[104] la_data_in[103] la_data_in[102] la_data_in[101] la_data_in[100]
++ la_data_in[99] la_data_in[98] la_data_in[97] la_data_in[96] la_data_in[95] la_data_in[94] la_data_in[93]
++ la_data_in[92] la_data_in[91] la_data_in[90] la_data_in[89] la_data_in[88] la_data_in[87] la_data_in[86]
++ la_data_in[85] la_data_in[84] la_data_in[83] la_data_in[82] la_data_in[81] la_data_in[80] la_data_in[79]
++ la_data_in[78] la_data_in[77] la_data_in[76] la_data_in[75] la_data_in[74] la_data_in[73] la_data_in[72]
++ la_data_in[71] la_data_in[70] la_data_in[69] la_data_in[68] la_data_in[67] la_data_in[66] la_data_in[65]
++ la_data_in[64] la_data_in[63] la_data_in[62] la_data_in[61] la_data_in[60] la_data_in[59] la_data_in[58]
++ la_data_in[57] la_data_in[56] la_data_in[55] la_data_in[54] la_data_in[53] la_data_in[52] la_data_in[51]
++ la_data_in[50] la_data_in[49] la_data_in[48] la_data_in[47] la_data_in[46] la_data_in[45] la_data_in[44]
++ la_data_in[43] la_data_in[42] la_data_in[41] la_data_in[40] la_data_in[39] la_data_in[38] la_data_in[37]
++ la_data_in[36] la_data_in[35] la_data_in[34] la_data_in[33] la_data_in[32] la_data_in[31] la_data_in[30]
++ la_data_in[29] la_data_in[28] la_data_in[27] la_data_in[26] la_data_in[25] la_data_in[24] la_data_in[23]
++ la_data_in[22] la_data_in[21] la_data_in[20] la_data_in[19] la_data_in[18] la_data_in[17] la_data_in[16]
++ la_data_in[15] la_data_in[14] la_data_in[13] la_data_in[12] la_data_in[11] la_data_in[10] la_data_in[9]
++ la_data_in[8] la_data_in[7] la_data_in[6] la_data_in[5] la_data_in[4] la_data_in[3] la_data_in[2] la_data_in[1]
++ la_data_in[0] la_data_out[127] la_data_out[126] la_data_out[125] la_data_out[124] la_data_out[123]
++ la_data_out[122] la_data_out[121] la_data_out[120] la_data_out[119] la_data_out[118] la_data_out[117]
++ la_data_out[116] la_data_out[115] la_data_out[114] la_data_out[113] la_data_out[112] la_data_out[111]
++ la_data_out[110] la_data_out[109] la_data_out[108] la_data_out[107] la_data_out[106] la_data_out[105]
++ la_data_out[104] la_data_out[103] la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98]
++ la_data_out[97] la_data_out[96] la_data_out[95] la_data_out[94] la_data_out[93] la_data_out[92] la_data_out[91]
++ la_data_out[90] la_data_out[89] la_data_out[88] la_data_out[87] la_data_out[86] la_data_out[85] la_data_out[84]
++ la_data_out[83] la_data_out[82] la_data_out[81] la_data_out[80] la_data_out[79] la_data_out[78] la_data_out[77]
++ la_data_out[76] la_data_out[75] la_data_out[74] la_data_out[73] la_data_out[72] la_data_out[71] la_data_out[70]
++ la_data_out[69] la_data_out[68] la_data_out[67] la_data_out[66] la_data_out[65] la_data_out[64] la_data_out[63]
++ la_data_out[62] la_data_out[61] la_data_out[60] la_data_out[59] la_data_out[58] la_data_out[57] la_data_out[56]
++ la_data_out[55] la_data_out[54] la_data_out[53] la_data_out[52] la_data_out[51] la_data_out[50] la_data_out[49]
++ la_data_out[48] la_data_out[47] la_data_out[46] la_data_out[45] la_data_out[44] la_data_out[43] la_data_out[42]
++ la_data_out[41] la_data_out[40] la_data_out[39] la_data_out[38] la_data_out[37] la_data_out[36] la_data_out[35]
++ la_data_out[34] la_data_out[33] la_data_out[32] la_data_out[31] la_data_out[30] la_data_out[29] la_data_out[28]
++ la_data_out[27] la_data_out[26] la_data_out[25] la_data_out[24] la_data_out[23] la_data_out[22] la_data_out[21]
++ la_data_out[20] la_data_out[19] la_data_out[18] la_data_out[17] la_data_out[16] la_data_out[15] la_data_out[14]
++ la_data_out[13] la_data_out[12] la_data_out[11] la_data_out[10] la_data_out[9] la_data_out[8] la_data_out[7]
++ la_data_out[6] la_data_out[5] la_data_out[4] la_data_out[3] la_data_out[2] la_data_out[1] la_data_out[0]
++ la_oenb[127] la_oenb[126] la_oenb[125] la_oenb[124] la_oenb[123] la_oenb[122] la_oenb[121] la_oenb[120]
++ la_oenb[119] la_oenb[118] la_oenb[117] la_oenb[116] la_oenb[115] la_oenb[114] la_oenb[113] la_oenb[112]
++ la_oenb[111] la_oenb[110] la_oenb[109] la_oenb[108] la_oenb[107] la_oenb[106] la_oenb[105] la_oenb[104]
++ la_oenb[103] la_oenb[102] la_oenb[101] la_oenb[100] la_oenb[99] la_oenb[98] la_oenb[97] la_oenb[96] la_oenb[95]
++ la_oenb[94] la_oenb[93] la_oenb[92] la_oenb[91] la_oenb[90] la_oenb[89] la_oenb[88] la_oenb[87] la_oenb[86]
++ la_oenb[85] la_oenb[84] la_oenb[83] la_oenb[82] la_oenb[81] la_oenb[80] la_oenb[79] la_oenb[78] la_oenb[77]
++ la_oenb[76] la_oenb[75] la_oenb[74] la_oenb[73] la_oenb[72] la_oenb[71] la_oenb[70] la_oenb[69] la_oenb[68]
++ la_oenb[67] la_oenb[66] la_oenb[65] la_oenb[64] la_oenb[63] la_oenb[62] la_oenb[61] la_oenb[60] la_oenb[59]
++ la_oenb[58] la_oenb[57] la_oenb[56] la_oenb[55] la_oenb[54] la_oenb[53] la_oenb[52] la_oenb[51] la_oenb[50]
++ la_oenb[49] la_oenb[48] la_oenb[47] la_oenb[46] la_oenb[45] la_oenb[44] la_oenb[43] la_oenb[42] la_oenb[41]
++ la_oenb[40] la_oenb[39] la_oenb[38] la_oenb[37] la_oenb[36] la_oenb[35] la_oenb[34] la_oenb[33] la_oenb[32]
++ la_oenb[31] la_oenb[30] la_oenb[29] la_oenb[28] la_oenb[27] la_oenb[26] la_oenb[25] la_oenb[24] la_oenb[23]
++ la_oenb[22] la_oenb[21] la_oenb[20] la_oenb[19] la_oenb[18] la_oenb[17] la_oenb[16] la_oenb[15] la_oenb[14]
++ la_oenb[13] la_oenb[12] la_oenb[11] la_oenb[10] la_oenb[9] la_oenb[8] la_oenb[7] la_oenb[6] la_oenb[5]
++ la_oenb[4] la_oenb[3] la_oenb[2] la_oenb[1] la_oenb[0] io_in[26] io_in[25] io_in[24] io_in[23] io_in[22]
++ io_in[21] io_in[20] io_in[19] io_in[18] io_in[17] io_in[16] io_in[15] io_in[14] io_in[13] io_in[12] io_in[11]
++ io_in[10] io_in[9] io_in[8] io_in[7] io_in[6] io_in[5] io_in[4] io_in[3] io_in[2] io_in[1] io_in[0]
++ io_in_3v3[26] io_in_3v3[25] io_in_3v3[24] io_in_3v3[23] io_in_3v3[22] io_in_3v3[21] io_in_3v3[20] io_in_3v3[19]
++ io_in_3v3[18] io_in_3v3[17] io_in_3v3[16] io_in_3v3[15] io_in_3v3[14] io_in_3v3[13] io_in_3v3[12] io_in_3v3[11]
++ io_in_3v3[10] io_in_3v3[9] io_in_3v3[8] io_in_3v3[7] io_in_3v3[6] io_in_3v3[5] io_in_3v3[4] io_in_3v3[3]
++ io_in_3v3[2] io_in_3v3[1] io_in_3v3[0] io_out[26] io_out[25] io_out[24] io_out[23] io_out[22] io_out[21]
++ io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15] io_out[14] io_out[13] io_out[12] io_out[11]
++ io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5] io_out[4] io_out[3] io_out[2] io_out[1] io_out[0]
++ io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22] io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17]
++ io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12] io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7]
++ io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2] io_oeb[1] io_oeb[0] gpio_analog[17] gpio_analog[16]
++ gpio_analog[15] gpio_analog[14] gpio_analog[13] gpio_analog[12] gpio_analog[11] gpio_analog[10] gpio_analog[9]
++ gpio_analog[8] gpio_analog[7] gpio_analog[6] gpio_analog[5] gpio_analog[4] gpio_analog[3] gpio_analog[2]
++ gpio_analog[1] gpio_analog[0] gpio_noesd[17] gpio_noesd[16] gpio_noesd[15] gpio_noesd[14] gpio_noesd[13]
++ gpio_noesd[12] gpio_noesd[11] gpio_noesd[10] gpio_noesd[9] gpio_noesd[8] gpio_noesd[7] gpio_noesd[6] gpio_noesd[5]
++ gpio_noesd[4] gpio_noesd[3] gpio_noesd[2] gpio_noesd[1] gpio_noesd[0] io_analog[10] io_analog[9] io_analog[8]
++ io_analog[7] io_analog[6] io_analog[5] io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0]
++ io_clamp_high[2] io_clamp_high[1] io_clamp_high[0] io_clamp_low[2] io_clamp_low[1] io_clamp_low[0] user_clock2
++ user_irq[2] user_irq[1] user_irq[0]
+*.iopin vdda1
+*.iopin vdda2
+*.iopin vssa1
+*.iopin vssa2
+*.iopin vccd1
+*.iopin vccd2
+*.iopin vssd1
+*.iopin vssd2
+*.ipin wb_clk_i
+*.ipin wb_rst_i
+*.ipin wbs_stb_i
+*.ipin wbs_cyc_i
+*.ipin wbs_we_i
+*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*.ipin
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*.ipin
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0]
+*.opin wbs_ack_o
+*.opin
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*.ipin
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*.opin
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*.ipin
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*.ipin
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0]
+*.ipin user_clock2
+*.opin
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*.opin
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*.iopin
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*.iopin
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*.iopin
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0]
+*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0]
+*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*.opin user_irq[2],user_irq[1],user_irq[0]
+*.ipin
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+x1 vdda1 vccd1 gpio_analog[3] io_out[11] io_out[12] vssa1 example_por
+x2 io_analog[4] vccd1 gpio_analog[7] io_out[15] io_out[16] vssa1 example_por
+.ends
+
+
+* expanding symbol: example_por.sym # of pins=6
+* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym
+* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch
+.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss
+*.iopin vdd3v3
+*.iopin vss
+*.opin porb_h
+*.opin porb_l
+*.opin por_l
+*.iopin vdd1v8
+XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
+XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
+XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=500 mult=1 m=1
+XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=150 mult=1 m=1
+XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=25 mult=2 m=2
+x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
+x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
+x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
+x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/current_test.spice b/xschem/current_test.spice
new file mode 100644
index 0000000..8e4162d
--- /dev/null
+++ b/xschem/current_test.spice
@@ -0,0 +1,86 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* Simple POR circuit for Caravel current mirror test
+*-------------------------------------------------------------------
+
+.param mc_mm_switch=0
+.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+* Note: 20 resistors of length 25um connected in series
+Xres1 vdda vin vss sky130_fd_pr__res_xhigh_po_0p69 l=500
+Xres2 vin vss vss sky130_fd_pr__res_xhigh_po_0p69 l=149
+
+* voltage sources at 0V for measuring current in each branch
+
+Vm1 vssm1 vss DC=0
+Vm2 vdda vddm2 DC=0
+Vm3 vdda vddm3 DC=0
+Vm4 vssm4 vss DC=0
+Vm5 vssm5 vss DC=0
+Vm6 vdda vddm6 DC=0
+Vm7 vdda vddm7 DC=0
+
+* D G S B
+Xm1 casc1 vin vssm1 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc1 mir1 casc1 casc1 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xm2 mir1 mir1 vddm2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=8
+Xm3 mir2 mir1 vddm3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc2 casc2 casc1 mir2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xm4 casc2 casc2 vssm4 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=7
+Xm5 casc3 casc2 vssm5 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc3 mir3 casc3 casc3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xm6 mir3 mir3 vddm6 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=7
+Xm7 mir4 mir3 vddm7 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc4 vcap casc3 mir4 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+
+* Check branch currents in each mirror branch.
+* 1st branch should be 240nA
+* 2nd branch should be 30nA
+* 3rd branch should be 4.3nA
+* 4th branch should be 612pA
+*
+* Result: vin sits at 0.7590 (close to 0.7575 target)
+* I(Vm1/2) = 202.80 nA
+* I(Vm3/4) = 26.10 nA (should be /8) actually /7.77
+* I(Vm5/6) = 4.58 nA (should be /7) actually /5.70
+* I(Vm7) = 0.67 nA (should be /7) actually /6.80
+
+*----------------------------
+* Testbench circuit
+*----------------------------
+Vpwr vdda vss DC=3.3
+Rgnd vss 0 0.01
+Rload vcap vss 1MEG
+*----------------------------
+
+*----------------------------
+* Testbench control
+*----------------------------
+.control
+op
+print V(vin)
+print I(Vm1)
+print I(Vm2)
+print I(Vm3)
+print I(Vm4)
+print I(Vm5)
+print I(Vm6)
+print I(Vm7)
+.endc
+
+.end
+
diff --git a/xschem/example_por.sch b/xschem/example_por.sch
new file mode 100644
index 0000000..cf6e0c3
--- /dev/null
+++ b/xschem/example_por.sch
@@ -0,0 +1,297 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+L 4 3370 -60 3390 -60 {}
+L 4 3390 -60 3390 80 {}
+L 4 3370 80 3390 80 {}
+T {Current step-down mirror} 2270 140 0 0 0.4 0.4 {}
+T {Charge accumulator} 2650 140 0 0 0.4 0.4 {}
+T {Voltage divider} 1860 140 0 0 0.4 0.4 {}
+T {Schmitt trigger} 2930 -200 0 0 0.4 0.4 {}
+T {150 / 650 * 3.3V = 0.76V} 1860 180 0 0 0.4 0.4 {}
+T {step down 8x} 2130 -430 0 0 0.4 0.4 {}
+T {step down 7x} 2330 80 0 0 0.4 0.4 {}
+T {step down 7x} 2520 -430 0 0 0.4 0.4 {}
+T {1.8V domain outputs} 3400 0 0 0 0.4 0.4 {}
+T {3.3V domain output} 3410 -140 0 0 0.4 0.4 {}
+T {392 : 1} 2270 180 0 0 0.4 0.4 {}
+T {Simple power-on-reset circuit
+calibrated to 500us nominal delay
+no temperature compensation} 1950 -570 0 0 0.6 0.6 {}
+N 2500 -310 2500 -270 { lab=#net1}
+N 2500 -210 2500 -100 { lab=#net2}
+N 2300 -40 2300 20 { lab=#net3}
+N 2300 80 2300 110 { lab=vss}
+N 2360 110 2500 110 { lab=vss}
+N 2500 80 2500 110 { lab=vss}
+N 2400 50 2460 50 { lab=#net3}
+N 2360 -400 2500 -400 { lab=vdd3v3}
+N 2500 -400 2500 -370 { lab=vdd3v3}
+N 2500 -400 2790 -400 { lab=vdd3v3}
+N 2300 -10 2370 -10 { lab=#net3}
+N 2370 -10 2370 50 { lab=#net3}
+N 2500 -290 2570 -290 { lab=#net1}
+N 2570 -340 2570 -290 { lab=#net1}
+N 2540 -340 2570 -340 { lab=#net1}
+N 2500 -190 2570 -190 { lab=#net2}
+N 2570 -240 2570 -190 { lab=#net2}
+N 2540 -240 2570 -240 { lab=#net2}
+N 2240 110 2360 110 { lab=vss}
+N 2500 110 2630 110 { lab=vss}
+N 2500 50 2630 50 { lab=vss}
+N 2110 110 2240 110 { lab=vss}
+N 1930 60 1930 110 { lab=vss}
+N 1930 -160 1930 0 { lab=#net4}
+N 1930 -400 1930 -220 { lab=vdd3v3}
+N 2110 -400 2360 -400 { lab=vdd3v3}
+N 1880 -190 1910 -190 { lab=vss}
+N 1880 -190 1880 110 { lab=vss}
+N 1880 110 1930 110 { lab=vss}
+N 1880 30 1910 30 { lab=vss}
+N 2300 -310 2300 -270 { lab=#net5}
+N 2300 -400 2300 -370 { lab=vdd3v3}
+N 2300 -140 2300 -100 { lab=#net3}
+N 2340 50 2400 50 { lab=#net3}
+N 2300 -210 2300 -140 { lab=#net3}
+N 2100 80 2100 110 { lab=vss}
+N 2100 110 2110 110 { lab=vss}
+N 2050 50 2060 50 { lab=#net4}
+N 2050 -70 2050 50 { lab=#net4}
+N 1930 -70 2050 -70 { lab=#net4}
+N 1930 -400 2110 -400 { lab=vdd3v3}
+N 2100 -400 2100 -370 { lab=vdd3v3}
+N 2100 -310 2100 -270 { lab=#net6}
+N 2100 -210 2100 20 { lab=#net7}
+N 2100 50 2300 50 { lab=vss}
+N 2200 50 2200 110 { lab=vss}
+N 2140 -240 2260 -240 { lab=#net7}
+N 2140 -340 2260 -340 { lab=#net6}
+N 2100 -290 2180 -290 { lab=#net6}
+N 2180 -340 2180 -290 { lab=#net6}
+N 2100 -180 2180 -180 { lab=#net7}
+N 2180 -240 2180 -180 { lab=#net7}
+N 1930 -240 2100 -240 { lab=vdd3v3}
+N 1930 -340 2100 -340 { lab=vdd3v3}
+N 1930 110 2100 110 { lab=vss}
+N 2300 -240 2500 -240 { lab=vdd3v3}
+N 2300 -340 2500 -340 { lab=vdd3v3}
+N 2400 -340 2400 -240 { lab=vdd3v3}
+N 2400 -400 2400 -340 { lab=vdd3v3}
+N 2570 -240 2650 -240 { lab=#net2}
+N 2570 -340 2650 -340 { lab=#net1}
+N 2690 -400 2690 -370 { lab=vdd3v3}
+N 2790 -400 2790 -340 { lab=vdd3v3}
+N 2690 -340 2790 -340 { lab=vdd3v3}
+N 2690 -240 2790 -240 { lab=vdd3v3}
+N 2790 -340 2790 -240 { lab=vdd3v3}
+N 2690 -310 2690 -270 { lab=#net8}
+N 2690 -210 2690 -150 { lab=#net9}
+N 1830 30 1880 30 { lab=vss}
+N 1810 60 1810 110 { lab=vss}
+N 1810 110 1880 110 { lab=vss}
+N 1810 -70 1810 0 { lab=vss}
+N 1810 -70 1880 -70 { lab=vss}
+N 2690 -150 2690 -70 { lab=#net9}
+N 2820 -130 2820 -70 { lab=#net9}
+N 2690 -130 2820 -130 { lab=#net9}
+N 2630 110 2820 110 { lab=vss}
+N 2820 -10 2820 110 { lab=vss}
+N 2690 -10 2690 110 { lab=vss}
+N 2820 -130 2980 -130 { lab=#net9}
+N 3060 -130 3130 -130 { lab=#net10}
+N 3090 -130 3090 60 { lab=#net10}
+N 3090 60 3130 60 { lab=#net10}
+N 3090 -40 3130 -40 { lab=#net10}
+N 3210 -130 3300 -130 { lab=porb_h}
+N 3210 -40 3300 -40 { lab=porb_l}
+N 3210 60 3300 60 { lab=por_l}
+N 2790 -400 2840 -400 { lab=vdd3v3}
+N 2820 110 2870 110 { lab=vss}
+N 2630 50 2690 50 { lab=vss}
+N 2300 -100 2300 -40 { lab=#net3}
+N 2500 -100 2500 -30 { lab=#net2}
+N 2500 -30 2500 20 { lab=#net2}
+C {sky130_fd_pr/cap_mim_m3_1.sym} 2690 -40 0 0 {name=C1 model=cap_mim_m3_1 W=30 L=30 MF=1 spiceprefix=X}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 2820 -40 2 1 {name=C2 model=cap_mim_m3_2 W=30 L=30 MF=1 spiceprefix=X}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2280 -240 0 0 {name=M1
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2480 50 0 0 {name=M2
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1930 -190 0 0 {name=R1
+L=500
+model=res_xhigh_po_0p69
+spiceprefix=X
+mult=1}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2280 -340 0 0 {name=M4
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2320 50 0 1 {name=M5
+L=0.8
+W=14
+nf=7
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1930 30 0 0 {name=R2
+L=150
+model=res_xhigh_po_0p69
+spiceprefix=X
+mult=1}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2520 -240 0 1 {name=M7
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2520 -340 0 1 {name=M8
+L=0.8
+W=14
+nf=7
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2080 50 0 0 {name=M10
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2120 -240 0 1 {name=M9
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2120 -340 0 1 {name=M11
+L=0.8
+W=16
+nf=8
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2670 -340 0 0 {name=M12
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2670 -240 0 0 {name=M13
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1810 30 0 1 {name=R3
+L=25
+model=res_xhigh_po_0p69
+spiceprefix=X
+mult=2}
+C {sky130_stdcells/buf_8.sym} 3170 -130 0 0 {name=x2 VGND=vss VNB=vss VPB=vdd3v3 VPWR=vdd3v3 prefix=sky130_fd_sc_hvl__ }
+C {sky130_stdcells/buf_8.sym} 3170 -40 0 0 {name=x3 VGND=vss VNB=vss VPB=vdd1v8 VPWR=vdd1v8 prefix=sky130_fd_sc_hvl__ }
+C {sky130_stdcells/inv_8.sym} 3170 60 0 0 {name=x4 VGND=vss VNB=vss VPB=vdd1v8 VPWR=vdd1v8 prefix=sky130_fd_sc_hvl__ }
+C {sky130_stdcells/buf_1.sym} 3020 -130 0 0 {name=x5 VGND=vss VNB=vss VPB=vdd3v3 VPWR=vdd3v3 prefix=sky130_fd_sc_hvl__schmitt }
+C {devices/iopin.sym} 2840 -400 0 0 {name=p1 lab=vdd3v3}
+C {devices/iopin.sym} 2870 110 0 0 {name=p2 lab=vss}
+C {devices/opin.sym} 3300 -130 0 0 {name=p3 lab=porb_h}
+C {devices/opin.sym} 3300 -40 0 0 {name=p4 lab=porb_l}
+C {devices/opin.sym} 3300 60 0 0 {name=p5 lab=por_l}
+C {devices/iopin.sym} 2840 -330 0 0 {name=p6 lab=vdd1v8}
diff --git a/xschem/example_por.sym b/xschem/example_por.sym
new file mode 100644
index 0000000..e3875f5
--- /dev/null
+++ b/xschem/example_por.sym
@@ -0,0 +1,33 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -60 130 -60 {}
+L 4 -130 60 130 60 {}
+L 4 -130 -60 -130 60 {}
+L 4 130 -60 130 60 {}
+L 4 130 -30 150 -30 {}
+L 4 130 0 150 0 {}
+L 4 130 30 150 30 {}
+L 7 -30 -80 -30 -60 {}
+L 7 30 -80 30 -60 {}
+L 7 0 60 0 80 {}
+B 5 -32.5 -82.5 -27.5 -77.5 {name=vdd3v3 dir=inout }
+B 5 27.5 -82.5 32.5 -77.5 {name=vdd1v8 dir=inout }
+B 5 147.5 -32.5 152.5 -27.5 {name=porb_h dir=out }
+B 5 147.5 -2.5 152.5 2.5 {name=porb_l dir=out }
+B 5 147.5 27.5 152.5 32.5 {name=por_l dir=out }
+B 5 -2.5 77.5 2.5 82.5 {name=vss dir=inout }
+T {@symname} -47.5 -6 0 0 0.3 0.3 {}
+T {@name} -25 18 0 0 0.2 0.2 {}
+T {vdd3v3} -15 -54 0 1 0.2 0.2 {}
+T {vdd1v8} 55 -54 0 1 0.2 0.2 {}
+T {porb_h} 125 -34 0 1 0.2 0.2 {}
+T {porb_l} 125 -4 0 1 0.2 0.2 {}
+T {por_l} 125 26 0 1 0.2 0.2 {}
+T {vss} 5 46 0 1 0.2 0.2 {}
diff --git a/xschem/example_por_tb.sch b/xschem/example_por_tb.sch
new file mode 100644
index 0000000..664018f
--- /dev/null
+++ b/xschem/example_por_tb.sch
@@ -0,0 +1,45 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+T {Testbench for simple POR} -350 -240 0 0 0.6 0.6 {}
+N -280 60 -10 60 { lab=GND}
+N -540 0 -540 60 { lab=#net1}
+N -330 0 -330 60 { lab=GND}
+N -330 -100 -330 -60 { lab=vdd3v3}
+N -330 -110 -330 -100 { lab=vdd3v3}
+N -210 -110 -40 -110 { lab=vdd3v3}
+N -40 -110 -40 -100 { lab=vdd3v3}
+N -540 -130 -540 -60 { lab=vdd1v8}
+N -280 -130 20 -130 { lab=#net2}
+N 20 -130 20 -100 { lab=#net2}
+N 140 -50 180 -50 { lab=porb_h}
+N 140 -20 180 -20 { lab=porb_l}
+N 140 10 180 10 { lab=por_l}
+N -340 -110 -330 -110 { lab=vdd3v3}
+N -500 -130 -490 -130 { lab=vdd1v8}
+N -540 -130 -500 -130 { lab=vdd1v8}
+N -560 -130 -540 -130 { lab=vdd1v8}
+N -540 60 -490 60 { lab=#net1}
+N -490 -130 -280 -130 {}
+N -490 60 -330 60 {}
+N -330 60 -280 60 {}
+N -330 -110 -210 -110 {}
+C {example_por.sym} -10 -20 0 0 {name=x1}
+C {devices/gnd.sym} -100 60 0 0 {name=l1 lab=GND}
+C {devices/vsource.sym} -330 -30 0 0 {name=V1 value="PWL(0.0 0 100u 0 5m 3.3)"}
+C {devices/vsource.sym} -540 -30 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3m 1.8)"}
+C {devices/opin.sym} -340 -110 0 1 {name=p1 lab=vdd3v3}
+C {devices/opin.sym} -560 -130 0 1 {name=p2 lab=vdd1v8}
+C {devices/opin.sym} 180 -50 0 0 {name=p3 lab=porb_h}
+C {devices/opin.sym} 180 -20 0 0 {name=p4 lab=porb_l}
+C {devices/opin.sym} 180 10 0 0 {name=p5 lab=por_l}
+C {devices/code_shown.sym} -470 140 0 0 {name=s1 only_toplevel=false value=".param mc_mm_switch=0
+.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"}
+C {devices/code_shown.sym} -470 250 0 0 {name=s2 only_toplevel=false value=".control
+tran 1u 20m
+plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l)
+.endc"}
diff --git a/xschem/example_por_tb.spice b/xschem/example_por_tb.spice
new file mode 100644
index 0000000..265e666
--- /dev/null
+++ b/xschem/example_por_tb.spice
@@ -0,0 +1,81 @@
+**.subckt example_por_tb vdd3v3 vdd1v8 porb_h porb_l por_l
+*.opin vdd3v3
+*.opin vdd1v8
+*.opin porb_h
+*.opin porb_l
+*.opin por_l
+x1 vdd3v3 vdd1v8 porb_h porb_l por_l GND example_por
+V1 vdd3v3 GND PWL(0.0 0 100u 0 5m 3.3)
+V2 vdd1v8 GND PWL(0.0 0 300u 0 5.3m 1.8)
+**** begin user architecture code
+
+.param mc_mm_switch=0
+.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
+
+
+.control
+tran 1u 20m
+plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l)
+.endc
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: example_por.sym # of pins=6
+* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym
+* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch
+.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss
+*.iopin vdd3v3
+*.iopin vss
+*.opin porb_h
+*.opin porb_l
+*.opin por_l
+*.iopin vdd1v8
+XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
+XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
+XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=500 mult=1 m=1
+XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=150 mult=1 m=1
+XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=25 mult=2 m=2
+x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
+x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
+x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
+x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/example_por_tb.spice.orig b/xschem/example_por_tb.spice.orig
new file mode 100644
index 0000000..069c74d
--- /dev/null
+++ b/xschem/example_por_tb.spice.orig
@@ -0,0 +1,88 @@
+**.subckt example_por_tb vdd3v3 vdd1v8 porb_h porb_l por_l
+.param mc_switch=0
+*.opin vdd3v3
+*.opin vdd1v8
+*.opin porb_h
+*.opin porb_l
+*.opin por_l
+x1 vdd3v3 vdd1v8 porb_h porb_l por_l GND example_por
+V1 vdd3v3 GND PWL(0.0 0 100u 0 5m 3.3)
+V2 vdd1v8 GND PWL(0.0 0 300u 0 5.3m 1.8)
+**** begin user architecture code
+
+.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+
+.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
+
+.control
+tran 1u 20m
+plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l)
+.endc
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: example_por.sym # of pins=6
+* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym
+* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch
+.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss
+*.iopin vdd3v3
+*.iopin vss
+*.opin porb_h
+*.opin porb_l
+*.opin por_l
+*.iopin vdd1v8
+XC1 net11 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
+XC2 net11 vss sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
+XM1 net5 net9 net7 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net1 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR1 net6 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=500 mult=1 m=1
+XM3 net3 net5 net1 vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net7 net8 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net4 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 net5 net5 net4 vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR2 vss net6 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=150 mult=1 m=1
+XM7 net3 net3 net2 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net2 net2 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net9 net6 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 net9 net9 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net8 net8 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net10 net2 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net11 net3 net10 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=25 mult=2 m=2
+x2 net12 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
+x3 net12 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
+x4 net12 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
+x5 net11 vss vss vdd3v3 vdd3v3 net12 sky130_fd_sc_hvl__schmittbuf_1
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/test.data b/xschem/test.data
new file mode 100644
index 0000000..c9cde37
--- /dev/null
+++ b/xschem/test.data
@@ -0,0 +1,101 @@
+ 7.00000000e-01 -8.93059159e-08 7.00000000e-01 7.00000000e-01
+ 7.01000000e-01 -9.08452852e-08 7.01000000e-01 7.01000000e-01
+ 7.02000000e-01 -9.24385447e-08 7.02000000e-01 7.02000000e-01
+ 7.03000000e-01 -9.40459956e-08 7.03000000e-01 7.03000000e-01
+ 7.04000000e-01 -9.56814959e-08 7.04000000e-01 7.04000000e-01
+ 7.05000000e-01 -9.73455368e-08 7.05000000e-01 7.05000000e-01
+ 7.06000000e-01 -9.90386085e-08 7.06000000e-01 7.06000000e-01
+ 7.07000000e-01 -1.00761227e-07 7.07000000e-01 7.07000000e-01
+ 7.08000000e-01 -1.02513882e-07 7.08000000e-01 7.08000000e-01
+ 7.09000000e-01 -1.04297110e-07 7.09000000e-01 7.09000000e-01
+ 7.10000000e-01 -1.06111443e-07 7.10000000e-01 7.10000000e-01
+ 7.11000000e-01 -1.07957415e-07 7.11000000e-01 7.11000000e-01
+ 7.12000000e-01 -1.09835552e-07 7.12000000e-01 7.12000000e-01
+ 7.13000000e-01 -1.11746436e-07 7.13000000e-01 7.13000000e-01
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+ 7.15000000e-01 -1.15668634e-07 7.15000000e-01 7.15000000e-01
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+ 7.38000000e-01 -1.71972266e-07 7.38000000e-01 7.38000000e-01
+ 7.39000000e-01 -1.74960357e-07 7.39000000e-01 7.39000000e-01
+ 7.40000000e-01 -1.77999888e-07 7.40000000e-01 7.40000000e-01
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+ 7.42000000e-01 -1.84236664e-07 7.42000000e-01 7.42000000e-01
+ 7.43000000e-01 -1.87435634e-07 7.43000000e-01 7.43000000e-01
+ 7.44000000e-01 -1.90689493e-07 7.44000000e-01 7.44000000e-01
+ 7.45000000e-01 -1.93999127e-07 7.45000000e-01 7.45000000e-01
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+ 7.49000000e-01 -2.07813739e-07 7.49000000e-01 7.49000000e-01
+ 7.50000000e-01 -2.11416073e-07 7.50000000e-01 7.50000000e-01
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+ 7.56000000e-01 -2.34353630e-07 7.56000000e-01 7.56000000e-01
+ 7.57000000e-01 -2.38406548e-07 7.57000000e-01 7.57000000e-01
+ 7.58000000e-01 -2.42527913e-07 7.58000000e-01 7.58000000e-01
+ 7.59000000e-01 -2.46718795e-07 7.59000000e-01 7.59000000e-01
+ 7.60000000e-01 -2.50980278e-07 7.60000000e-01 7.60000000e-01
+ 7.61000000e-01 -2.55313430e-07 7.61000000e-01 7.61000000e-01
+ 7.62000000e-01 -2.59719344e-07 7.62000000e-01 7.62000000e-01
+ 7.63000000e-01 -2.64199148e-07 7.63000000e-01 7.63000000e-01
+ 7.64000000e-01 -2.68753946e-07 7.64000000e-01 7.64000000e-01
+ 7.65000000e-01 -2.73384860e-07 7.65000000e-01 7.65000000e-01
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+ 7.69000000e-01 -2.92692776e-07 7.69000000e-01 7.69000000e-01
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+ 7.71000000e-01 -3.02833688e-07 7.71000000e-01 7.71000000e-01
+ 7.72000000e-01 -3.08030053e-07 7.72000000e-01 7.72000000e-01
+ 7.73000000e-01 -3.13311974e-07 7.73000000e-01 7.73000000e-01
+ 7.74000000e-01 -3.18680710e-07 7.74000000e-01 7.74000000e-01
+ 7.75000000e-01 -3.24137468e-07 7.75000000e-01 7.75000000e-01
+ 7.76000000e-01 -3.29683509e-07 7.76000000e-01 7.76000000e-01
+ 7.77000000e-01 -3.35320078e-07 7.77000000e-01 7.77000000e-01
+ 7.78000000e-01 -3.41048451e-07 7.78000000e-01 7.78000000e-01
+ 7.79000000e-01 -3.46869908e-07 7.79000000e-01 7.79000000e-01
+ 7.80000000e-01 -3.52785731e-07 7.80000000e-01 7.80000000e-01
+ 7.81000000e-01 -3.58797218e-07 7.81000000e-01 7.81000000e-01
+ 7.82000000e-01 -3.64905663e-07 7.82000000e-01 7.82000000e-01
+ 7.83000000e-01 -3.71112381e-07 7.83000000e-01 7.83000000e-01
+ 7.84000000e-01 -3.77418703e-07 7.84000000e-01 7.84000000e-01
+ 7.85000000e-01 -3.83825919e-07 7.85000000e-01 7.85000000e-01
+ 7.86000000e-01 -3.90335390e-07 7.86000000e-01 7.86000000e-01
+ 7.87000000e-01 -3.96948455e-07 7.87000000e-01 7.87000000e-01
+ 7.88000000e-01 -4.03666461e-07 7.88000000e-01 7.88000000e-01
+ 7.89000000e-01 -4.10490750e-07 7.89000000e-01 7.89000000e-01
+ 7.90000000e-01 -4.17422681e-07 7.90000000e-01 7.90000000e-01
+ 7.91000000e-01 -4.24463629e-07 7.91000000e-01 7.91000000e-01
+ 7.92000000e-01 -4.31614946e-07 7.92000000e-01 7.92000000e-01
+ 7.93000000e-01 -4.38878017e-07 7.93000000e-01 7.93000000e-01
+ 7.94000000e-01 -4.46254218e-07 7.94000000e-01 7.94000000e-01
+ 7.95000000e-01 -4.53744916e-07 7.95000000e-01 7.95000000e-01
+ 7.96000000e-01 -4.61351506e-07 7.96000000e-01 7.96000000e-01
+ 7.97000000e-01 -4.69075369e-07 7.97000000e-01 7.97000000e-01
+ 7.98000000e-01 -4.76917893e-07 7.98000000e-01 7.98000000e-01
+ 7.99000000e-01 -4.84880471e-07 7.99000000e-01 7.99000000e-01
+ 8.00000000e-01 -4.92964482e-07 8.00000000e-01 8.00000000e-01
diff --git a/xschem/threshold_test_tb.spice b/xschem/threshold_test_tb.spice
new file mode 100644
index 0000000..9543330
--- /dev/null
+++ b/xschem/threshold_test_tb.spice
@@ -0,0 +1,47 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* Threshold test for POR circuit
+* Determine gate voltage at which the HV NFET draws 240nA nominal
+*
+* Result: 0.7575V
+*-------------------------------------------------------------------
+
+.param mc_mm_switch=0
+.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+*----------------------------
+* Testbench circuit
+*----------------------------
+Rtest vdda mir1 1MEG
+Xm1 mir1 vin vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8
+
+Vgate vin vss DC=0
+Vpwr vdda vss DC=3.3
+Rgnd vss 0 0.1
+
+*----------------------------
+* Testbench control
+*----------------------------
+.control
+* DC sweep from 0.7 to 0.8V
+dc Vgate 0.7 0.8 0.001
+wrdata test.data Vpwr#branch vin
+
+.endc
+
+.end
+
diff --git a/xschem/user_analog_project_wrapper.sch b/xschem/user_analog_project_wrapper.sch
new file mode 100644
index 0000000..e0da610
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.sch
@@ -0,0 +1,70 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 3830 -460 3830 -390 { lab=vdda1}
+N 3730 -460 3830 -460 { lab=vdda1}
+N 3860 -230 3860 -180 { lab=vssa1}
+N 3770 -180 3860 -180 { lab=vssa1}
+N 3890 -460 3890 -390 { lab=vccd1}
+N 3890 -460 3960 -460 { lab=vccd1}
+N 3890 -130 3890 -60 { lab=vccd1}
+N 3890 -130 3950 -130 { lab=vccd1}
+N 3830 -130 3830 -60 { lab=io_analog[4]}
+N 3790 -130 3830 -130 { lab=io_analog[4]}
+N 3860 100 3860 150 { lab=vssa1}
+N 3800 150 3860 150 { lab=vssa1}
+N 4010 -10 4110 -10 { lab=gpio_analog[7]}
+N 4010 20 4110 20 { lab=io_out[15]}
+N 4010 50 4110 50 { lab=io_out[16]}
+N 4010 -340 4130 -340 { lab=gpio_analog[3]}
+N 4010 -310 4130 -310 { lab=io_out[11]}
+N 4010 -280 4130 -280 { lab=io_out[12]}
+C {example_por.sym} 3860 -310 0 0 {name=x1}
+C {example_por.sym} 3860 20 0 0 {name=x2}
+C {devices/iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
+C {devices/iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
+C {devices/iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
+C {devices/iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2}
+C {devices/iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1}
+C {devices/iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2}
+C {devices/iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1}
+C {devices/iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2}
+C {devices/ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i}
+C {devices/ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i}
+C {devices/ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i}
+C {devices/ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i}
+C {devices/ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i}
+C {devices/ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]}
+C {devices/ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]}
+C {devices/ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]}
+C {devices/opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o}
+C {devices/opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]}
+C {devices/ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]}
+C {devices/opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]}
+C {devices/ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]}
+C {devices/ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]}
+C {devices/ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2}
+C {devices/opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]}
+C {devices/opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]}
+C {devices/iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]}
+C {devices/iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]}
+C {devices/iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]}
+C {devices/iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]}
+C {devices/iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
+C {devices/opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
+C {devices/ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
+C {devices/lab_pin.sym} 3730 -460 0 0 {name=l1 sig_type=std_logic lab=vdda1}
+C {devices/lab_pin.sym} 3770 -180 0 0 {name=l2 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 3960 -460 0 1 {name=l3 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 3950 -130 0 1 {name=l4 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 3790 -130 0 0 {name=l5 sig_type=std_logic lab=io_analog[4]}
+C {devices/lab_pin.sym} 3800 150 0 0 {name=l6 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4130 -340 0 1 {name=l7 sig_type=std_logic lab=gpio_analog[3]}
+C {devices/lab_pin.sym} 4130 -310 0 1 {name=l8 sig_type=std_logic lab=io_out[11]}
+C {devices/lab_pin.sym} 4130 -280 0 1 {name=l9 sig_type=std_logic lab=io_out[12]}
+C {devices/lab_pin.sym} 4110 -10 0 1 {name=l10 sig_type=std_logic lab=gpio_analog[7]}
+C {devices/lab_pin.sym} 4110 20 0 1 {name=l11 sig_type=std_logic lab=io_out[15]}
+C {devices/lab_pin.sym} 4110 50 0 1 {name=l12 sig_type=std_logic lab=io_out[16]}
diff --git a/xschem/user_analog_project_wrapper.spice b/xschem/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..917d69e
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.spice
@@ -0,0 +1,121 @@
+**.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa1 vccd1 vccd2 vssd1 vssd2 wb_clk_i
+*+ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0] wbs_ack_o
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0] user_clock2
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0] io_clamp_high[2],io_clamp_high[1],io_clamp_high[0] io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*+ user_irq[2],user_irq[1],user_irq[0]
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+*.iopin vdda1
+*.iopin vdda2
+*.iopin vssa1
+*.iopin vssa1
+*.iopin vccd1
+*.iopin vccd2
+*.iopin vssd1
+*.iopin vssd2
+*.ipin wb_clk_i
+*.ipin wb_rst_i
+*.ipin wbs_stb_i
+*.ipin wbs_cyc_i
+*.ipin wbs_we_i
+*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*.ipin
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*.ipin
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0]
+*.opin wbs_ack_o
+*.opin
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*.ipin
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*.opin
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*.ipin
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*.ipin
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0]
+*.ipin user_clock2
+*.opin
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*.opin
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*.iopin
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*.iopin
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*.iopin
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0]
+*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0]
+*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*.opin user_irq[2],user_irq[1],user_irq[0]
+*.ipin
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+x1 vdda1 vccd1 gpio_analog[3] io_out[11] io_out[12] vssa1 example_por
+x2 io_analog[4] vccd1 gpio_analog[7] io_out[15] io_out[16] vssa1 example_por
+**.ends
+
+* expanding symbol: example_por.sym # of pins=6
+* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym
+* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch
+.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss
+*.iopin vdd3v3
+*.iopin vss
+*.opin porb_h
+*.opin porb_l
+*.opin por_l
+*.iopin vdd1v8
+XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
+XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
+XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=500 mult=1 m=1
+XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=150 mult=1 m=1
+XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=25 mult=2 m=2
+x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
+x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
+x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
+x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/user_analog_project_wrapper.sym b/xschem/user_analog_project_wrapper.sym
new file mode 100644
index 0000000..a561ba9
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.sym
@@ -0,0 +1,111 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -190 130 -190 {}
+L 4 -130 190 130 190 {}
+L 4 -130 -190 -130 190 {}
+L 4 130 -190 130 190 {}
+L 4 -150 -180 -130 -180 {}
+L 4 -150 -160 -130 -160 {}
+L 4 -150 -140 -130 -140 {}
+L 4 -150 -120 -130 -120 {}
+L 4 -150 -100 -130 -100 {}
+L 4 -150 -80 -130 -80 {}
+L 4 -150 -60 -130 -60 {}
+L 4 -150 -40 -130 -40 {}
+L 4 130 -20 150 -20 {}
+L 4 130 0 150 0 {}
+L 4 -150 -20 -130 -20 {}
+L 4 130 20 150 20 {}
+L 4 -150 0 -130 0 {}
+L 4 -150 20 -130 20 {}
+L 4 -150 40 -130 40 {}
+L 4 130 40 150 40 {}
+L 4 130 60 150 60 {}
+L 4 -150 60 -130 60 {}
+L 4 130 180 150 180 {}
+L 7 130 -180 150 -180 {}
+L 7 130 -160 150 -160 {}
+L 7 130 -140 150 -140 {}
+L 7 130 -120 150 -120 {}
+L 7 130 -100 150 -100 {}
+L 7 130 -80 150 -80 {}
+L 7 130 -60 150 -60 {}
+L 7 130 -40 150 -40 {}
+L 7 130 80 150 80 {}
+L 7 130 100 150 100 {}
+L 7 130 120 150 120 {}
+L 7 130 140 150 140 {}
+L 7 130 160 150 160 {}
+B 5 147.5 -182.5 152.5 -177.5 {name=vdda1 dir=inout }
+B 5 147.5 -162.5 152.5 -157.5 {name=vdda2 dir=inout }
+B 5 147.5 -142.5 152.5 -137.5 {name=vssa1 dir=inout }
+B 5 147.5 -122.5 152.5 -117.5 {name=vssa2 dir=inout }
+B 5 147.5 -102.5 152.5 -97.5 {name=vccd1 dir=inout }
+B 5 147.5 -82.5 152.5 -77.5 {name=vccd2 dir=inout }
+B 5 147.5 -62.5 152.5 -57.5 {name=vssd1 dir=inout }
+B 5 147.5 -42.5 152.5 -37.5 {name=vssd2 dir=inout }
+B 5 -152.5 -182.5 -147.5 -177.5 {name=wb_clk_i dir=in }
+B 5 -152.5 -162.5 -147.5 -157.5 {name=wb_rst_i dir=in }
+B 5 -152.5 -142.5 -147.5 -137.5 {name=wbs_stb_i dir=in }
+B 5 -152.5 -122.5 -147.5 -117.5 {name=wbs_cyc_i dir=in }
+B 5 -152.5 -102.5 -147.5 -97.5 {name=wbs_we_i dir=in }
+B 5 -152.5 -82.5 -147.5 -77.5 {name=wbs_sel_i[3:0] dir=in }
+B 5 -152.5 -62.5 -147.5 -57.5 {name=wbs_dat_i[31:0] dir=in }
+B 5 -152.5 -42.5 -147.5 -37.5 {name=wbs_adr_i[31:0] dir=in }
+B 5 147.5 -22.5 152.5 -17.5 {name=wbs_ack_o dir=out }
+B 5 147.5 -2.5 152.5 2.5 {name=wbs_dat_o[31:0] dir=out }
+B 5 -152.5 -22.5 -147.5 -17.5 {name=la_data_in[127:0] dir=in }
+B 5 147.5 17.5 152.5 22.5 {name=la_data_out[127:0] dir=out }
+B 5 -152.5 -2.5 -147.5 2.5 {name=la_oenb[127:0] dir=in }
+B 5 -152.5 17.5 -147.5 22.5 {name=io_in[26:0] dir=in }
+B 5 -152.5 37.5 -147.5 42.5 {name=io_in_3v3[26:0] dir=in }
+B 5 147.5 37.5 152.5 42.5 {name=io_out[26:0] dir=out }
+B 5 147.5 57.5 152.5 62.5 {name=io_oeb[26:0] dir=out }
+B 5 147.5 77.5 152.5 82.5 {name=gpio_analog[17:0] dir=inout }
+B 5 147.5 97.5 152.5 102.5 {name=gpio_noesd[17:0] dir=inout }
+B 5 147.5 117.5 152.5 122.5 {name=io_analog[10:0] dir=inout }
+B 5 147.5 137.5 152.5 142.5 {name=io_clamp_high[2:0] dir=inout }
+B 5 147.5 157.5 152.5 162.5 {name=io_clamp_low[2:0] dir=inout }
+B 5 -152.5 57.5 -147.5 62.5 {name=user_clock2 dir=in }
+B 5 147.5 177.5 152.5 182.5 {name=user_irq[2:0] dir=out }
+T {@symname} -119.5 114 0 0 0.3 0.3 {}
+T {@name} 135 -202 0 0 0.2 0.2 {}
+T {vdda1} 125 -184 0 1 0.2 0.2 {}
+T {vdda2} 125 -164 0 1 0.2 0.2 {}
+T {vssa1} 125 -144 0 1 0.2 0.2 {}
+T {vssa2} 125 -124 0 1 0.2 0.2 {}
+T {vccd1} 125 -104 0 1 0.2 0.2 {}
+T {vccd2} 125 -84 0 1 0.2 0.2 {}
+T {vssd1} 125 -64 0 1 0.2 0.2 {}
+T {vssd2} 125 -44 0 1 0.2 0.2 {}
+T {wb_clk_i} -125 -184 0 0 0.2 0.2 {}
+T {wb_rst_i} -125 -164 0 0 0.2 0.2 {}
+T {wbs_stb_i} -125 -144 0 0 0.2 0.2 {}
+T {wbs_cyc_i} -125 -124 0 0 0.2 0.2 {}
+T {wbs_we_i} -125 -104 0 0 0.2 0.2 {}
+T {wbs_sel_i[3:0]} -125 -84 0 0 0.2 0.2 {}
+T {wbs_dat_i[31:0]} -125 -64 0 0 0.2 0.2 {}
+T {wbs_adr_i[31:0]} -125 -44 0 0 0.2 0.2 {}
+T {wbs_ack_o} 125 -24 0 1 0.2 0.2 {}
+T {wbs_dat_o[31:0]} 125 -4 0 1 0.2 0.2 {}
+T {la_data_in[127:0]} -125 -24 0 0 0.2 0.2 {}
+T {la_data_out[127:0]} 125 16 0 1 0.2 0.2 {}
+T {la_oenb[127:0]} -125 -4 0 0 0.2 0.2 {}
+T {io_in[26:0]} -125 16 0 0 0.2 0.2 {}
+T {io_in_3v3[26:0]} -125 36 0 0 0.2 0.2 {}
+T {io_out[26:0]} 125 36 0 1 0.2 0.2 {}
+T {io_oeb[26:0]} 125 56 0 1 0.2 0.2 {}
+T {gpio_analog[17:0]} 125 76 0 1 0.2 0.2 {}
+T {gpio_noesd[17:0]} 125 96 0 1 0.2 0.2 {}
+T {io_analog[10:0]} 125 116 0 1 0.2 0.2 {}
+T {io_clamp_high[2:0]} 125 136 0 1 0.2 0.2 {}
+T {io_clamp_low[2:0]} 125 156 0 1 0.2 0.2 {}
+T {user_clock2} -125 56 0 0 0.2 0.2 {}
+T {user_irq[2:0]} 125 176 0 1 0.2 0.2 {}
diff --git a/xschem/xschemrc b/xschem/xschemrc
new file mode 100644
index 0000000..98fead5
--- /dev/null
+++ b/xschem/xschemrc
@@ -0,0 +1,273 @@
+#### xschemrc system configuration file
+
+#### values may be overridden by user's ~/.xschem/xschemrc configuration file
+#### or by project-local ./xschemrc
+
+###########################################################################
+#### XSCHEM INSTALLATION DIRECTORY: XSCHEM_SHAREDIR
+###########################################################################
+#### Normally there is no reason to set this variable if using standard
+#### installation. Location of files is set at compile time but may be overridden
+#### with following line:
+# set XSCHEM_SHAREDIR $env(HOME)/share/xschem
+
+###########################################################################
+#### XSCHEM SYSTEM-WIDE DESIGN LIBRARY PATHS: XSCHEM_LIBRARY_PATH
+###########################################################################
+#### If unset xschem starts with XSCHEM_LIBRARY_PATH set to the default, typically:
+# /home/schippes/.xschem/xschem_library
+# /home/schippes/share/xschem/xschem_library/devices
+# /home/schippes/share/doc/xschem/examples
+# /home/schippes/share/doc/xschem/ngspice
+# /home/schippes/share/doc/xschem/logic
+# /home/schippes/share/doc/xschem/xschem_simulator
+# /home/schippes/share/doc/xschem/binto7seg
+# /home/schippes/share/doc/xschem/pcb
+# /home/schippes/share/doc/xschem/rom8k
+
+#### Flush any previous definition
+set XSCHEM_LIBRARY_PATH {}
+#### include devices/*.sym
+append XSCHEM_LIBRARY_PATH ${XSCHEM_SHAREDIR}/xschem_library
+#### include skywater libraries. Here i use [pwd]. This works if i start xschem from here.
+append XSCHEM_LIBRARY_PATH :$env(PWD)
+append XSCHEM_LIBRARY_PATH :/usr/share/pdk/sky130A/libs.tech/xschem
+#### add ~/.xschem/xschem_library (USER_CONF_DIR is normally ~/.xschem)
+append XSCHEM_LIBRARY_PATH :$USER_CONF_DIR/xschem_library
+
+###########################################################################
+#### SET CUSTOM COLORS FOR XSCHEM LIBRARIES MATCHING CERTAIN PATTERNS
+###########################################################################
+#### each line contains a dircolor(pattern) followed by a color
+#### color can be an ordinary name (grey, brown, blue) or a hex code {#77aaff}
+#### hex code must be enclosed in braces
+array unset dircolor
+set dircolor(sky130_fd_pr$) blue
+set dircolor(sky130_tests$) blue
+set dircolor(xschem_sky130$) blue
+set dircolor(xschem_library$) red
+set dircolor(devices$) red
+
+###########################################################################
+#### WINDOW TO OPEN ON STARTUP: XSCHEM_START_WINDOW
+###########################################################################
+#### Start without a design if no filename given on command line:
+#### To avoid absolute paths, use a path that is relative to one of the
+#### XSCHEM_LIBRARY_PATH directories. Default: empty
+set XSCHEM_START_WINDOW {sky130_tests/top.sch}
+
+###########################################################################
+#### DIRECTORY WHERE SIMULATIONS, NETLIST AND SIMULATOR OUTPUTS ARE PLACED
+###########################################################################
+#### If unset $USER_CONF_DIR/simulations is assumed (normally ~/.xschem/simulations)
+# set netlist_dir $env(HOME)/.xschem/simulations
+set netlist_dir .
+
+###########################################################################
+#### CHANGE DEFAULT [] WITH SOME OTHER CHARACTERS FOR BUSSED SIGNALS
+#### IN SPICE NETLISTS (EXAMPLE: DATA[7] --> DATA<7>)
+###########################################################################
+#### default: empty (use xschem default, [ ])
+# set bus_replacement_char {<>}
+#### for XSPICE: replace square brackets as the are used for XSPICE vector nodes.
+# set bus_replacement_char {__}
+
+###########################################################################
+#### SOME DEFAULT BEHAVIOR
+###########################################################################
+#### Allowed values: spice, verilog, vhdl, tedax, default: spice
+# set netlist_type spice
+
+#### Some netlisting options (these are the defaults)
+# set hspice_netlist 1
+# set verilog_2001 1
+
+#### to use a fixed line with set change_lw to 0 and set some value to line_width
+#### these are the defaults
+# set line_width 0
+# set change_lw 1
+
+#### allow color postscript and svg exports. Default: 1, enable color
+# set color_ps 1
+
+#### initial size of xschem window you can specify also position with (wxh+x+y)
+#### this is the default:
+# set initial_geometry {900x600}
+
+#### if set to 0, when zooming out allow the viewport do drift toward the mouse position,
+#### allowing to move away by zooming / unzooming with mouse wheel
+#### default setting: 0
+# set unzoom_nodrift 0
+
+#### if set to 1 allow to place multiple components with same name.
+#### Warning: this is normally not allowed in any simulation netlist.
+#### default: 0, do not allow place multiple elements with same name (refdes)
+# set disable_unique_names 0
+
+#### if set to 1 continue drawing lines / wires after click
+#### default: 0
+# set persistent_command 1
+
+#### if set to 1 automatically join/trim wires while editing
+#### this may slow down on rally big designs. Can be disabled via menu
+#### default: 0
+# set autotrim_wires 0
+
+#### set widget scaling (mainly for font display), this is useful on 4K displays
+#### default: unset (tk uses its default) > 1.0 ==> bigger
+# set tk_scaling 1.7
+
+#### disable some symbol layers. Default: none, all layers are visible.
+# set enable_layer(5) 0 ;# example to disable pin red boxes
+
+#### enable to scale grid point size as done with lines at close zoom, default: 0
+# set big_grid_points 0
+
+###########################################################################
+#### EXPORT FORMAT TRANSLATORS, PNG AND PDF
+###########################################################################
+#### command to translate xpm to png; (assumes command takes source
+#### and dest file as arguments, example: gm convert plot.xpm plot.png)
+#### default: {gm convert}
+# set to_png {gm convert}
+
+#### command to translate ps to pdf; (assumes command takes source
+#### and dest file as arguments, example: ps2pdf plot.ps plot.pdf)
+#### default: ps2pdf
+# set to_pdf ps2pdf
+
+###########################################################################
+#### CUSTOM GRID / SNAP VALUE SETTINGS
+###########################################################################
+#### Warning: changing these values will likely break compatibility
+#### with existing symbol libraries. Defaults: grid 20, snap 10.
+# set grid 20
+# set snap 10
+
+###########################################################################
+#### CUSTOM COLORS MAY BE DEFINED HERE
+###########################################################################
+# set cadlayers 22
+# set light_colors {
+# "#ffffff" "#0044ee" "#aaaaaa" "#222222" "#229900"
+# "#bb2200" "#00ccee" "#ff0000" "#888800" "#00aaaa"
+# "#880088" "#00ff00" "#0000cc" "#666600" "#557755"
+# "#aa2222" "#7ccc40" "#00ffcc" "#ce0097" "#d2d46b"
+# "#ef6158" "#fdb200" }
+
+# set dark_colors {
+# "#000000" "#00ccee" "#3f3f3f" "#cccccc" "#88dd00"
+# "#bb2200" "#00ccee" "#ff0000" "#ffff00" "#ffffff"
+# "#ff00ff" "#00ff00" "#0000cc" "#aaaa00" "#aaccaa"
+# "#ff7777" "#bfff81" "#00ffcc" "#ce0097" "#d2d46b"
+# "#ef6158" "#fdb200" }
+
+###########################################################################
+#### CAIRO STUFF
+###########################################################################
+#### Scale all fonts by this number
+# set cairo_font_scale 1.0
+
+#### default for following two is 0.85 (xscale) and 0.88 (yscale) to
+#### match cairo font spacing
+# set nocairo_font_xscale 1.0
+#### set nocairo_font_yscale 1.0
+
+#### Scale line spacing by this number
+# set cairo_font_line_spacing 1.0
+
+#### Specify a font
+# set cairo_font_name {Sans-Serif}
+# set svg_font_name {Sans-Serif}
+
+#### Lift up text by some zoom-corrected pixels for
+#### better compatibility wrt no cairo version.
+#### Useful values in the range [-1, 3]
+# set cairo_vert_correct 0
+# set nocairo_vert_correct 0
+
+###########################################################################
+#### KEYBINDINGS
+###########################################################################
+#### General format for specifying a replacement for a keybind
+#### Replace Ctrl-d with Escape (so you wont kill the program)
+# set replace_key(Control-d) Escape
+
+#### swap w and W keybinds; Always specify Shift for capital letters
+# set replace_key(Shift-W) w
+# set replace_key(w) Shift-W
+
+###########################################################################
+#### TERMINAL
+###########################################################################
+#### default for linux: xterm
+# set terminal {xterm -geometry 100x35 -fn 9x15 -bg black -fg white -cr white -ms white }
+#### lxterminal is not OK since it will not inherit env vars:
+#### In order to reduce memory usage and increase the performance, all instances
+#### of the lxterminal are sharing a single process. LXTerminal is part of LXDE
+
+###########################################################################
+#### EDITOR
+###########################################################################
+#### editor must not detach from launching shell (-f mandatory for gvim)
+#### default for linux: gvim -f
+# set editor {gvim -f -geometry 90x28}
+# set editor { xterm -geometry 100x40 -e nano }
+# set editor { xterm -geometry 100x40 -e pico }
+
+#### For Windows
+# set editor {notepad.exe}
+
+###########################################################################
+#### SHOW ERC INFO WINDOW (erc errors, warnings etc)
+###########################################################################
+#### default: 0 (can be enabled by menu)
+# set show_infowindow 0
+
+###########################################################################
+#### CONFIGURE COMPUTER FARM JOB REDIRECTORS FOR SIMULATIONS
+###########################################################################
+#### RTDA NC
+# set computerfarm {nc run -Il}
+#### LSF BSUB
+# set computerfarm {bsub -Is}
+
+###########################################################################
+#### TCP CONNECTION WITH GAW
+###########################################################################
+#### set gaw address for socket connection: {host port}
+#### default: set to localhost, port 2020
+# set gaw_tcp_address {localhost 2020}
+
+###########################################################################
+#### XSCHEM LISTEN TO TCP PORT
+###########################################################################
+#### set xschem listening port; default: not enabled
+# set xschem_listen_port 2021
+
+###########################################################################
+#### UTILE SPICE STIMULI DESCRIPTION LANGUAGE AND TRANSLATOR
+###########################################################################
+#### default paths are set as shown here:
+# set utile_gui_path ${XSCHEM_SHAREDIR}/utile/utile3
+# set utile_cmd_path ${XSCHEM_SHAREDIR}/utile/utile
+
+###########################################################################
+#### TCL FILES TO LOAD AT STARTUP
+###########################################################################
+#### list of tcl files to preload.
+# lappend tcl_files ${XSCHEM_SHAREDIR}/change_index.tcl
+lappend tcl_files ${XSCHEM_SHAREDIR}/ngspice_backannotate.tcl
+lappend tcl_files /usr/share/pdk/sky130A/libs.tech/xschem/scripts/sky130_models.tcl
+###########################################################################
+#### XSCHEM TOOLBAR
+###########################################################################
+#### default: not enabled.
+# set toolbar_visible 1
+# set toolbar_horiz 1
+
+###########################################################################
+#### SKYWATER PDK SPECIFIC VARIABLES
+###########################################################################
+set SKYWATER_MODELS ~/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest
+set SKYWATER_STDCELLS ~/skywater-pdk/libraries/sky130_fd_sc_hd/latest
