commit: 1eb2fdbbfef6887f8c262aa2daf0c1c6e230e4fc
[log] [tgz]
author: zaellis <ellis128@purdue.edu>
Sun Jun 13 04:12:57 2021 -0400
committer: zaellis <ellis128@purdue.edu>
Sun Jun 13 04:12:57 2021 -0400
tree: 9be1e2e48de7f5d9bca10db528a38342bf3f1186
parent: d3e050539b229d532a45c37a645482e081e344cc [diff]

cannot get through entire flow. added project files

def/user_proj_example.def[diff]
gds/user_proj_example.gds[Added - diff]
lef/user_proj_example.lef[diff]
mag/user_proj_example.mag[diff]
maglef/user_proj_example.mag[diff]
openlane/user_proj_example/config.tcl[diff]
signoff/user_proj_example/OPENLANE_VERSION[diff]
signoff/user_proj_example/PDK_SOURCES[diff]
signoff/user_proj_example/final_summary_report.csv[diff]
spi/lvs/user_proj_example.spice[diff]
verilog/gl/user_proj_example.v[diff]
verilog/rtl/CAN_receiver.sv[Added - diff]
verilog/rtl/CRCcheck.sv[Added - diff]
verilog/rtl/ECU.sv[Added - diff]
verilog/rtl/RCU.sv[Added - diff]
verilog/rtl/TCU.sv[Added - diff]
verilog/rtl/edgedetect.sv[Added - diff]
verilog/rtl/fifo.sv[Added - diff]
verilog/rtl/fifo.v[Added - diff]
verilog/rtl/flex_counter.sv[Added - diff]
verilog/rtl/flex_pts_sr.sv[Added - diff]
verilog/rtl/flex_stp_sr.sv[Added - diff]
verilog/rtl/tb_CAN_receiver.sv[Added - diff]
verilog/rtl/tb_fifo.sv[Added - diff]
verilog/rtl/tb_wb_CAN.sv[Added - diff]
verilog/rtl/tb_wb_slave.sv[Added - diff]
verilog/rtl/timer.sv[Added - diff]
verilog/rtl/tx_timer.sv[Added - diff]
verilog/rtl/user_proj_example.v[diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl/wb_CAN.sv[Added - diff]
verilog/rtl/wb_slave.sv[Added - diff]
verilog/rtl/wb_slave.v[Added - diff]

33 files changed

tree: 9be1e2e48de7f5d9bca10db528a38342bf3f1186

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.