Updated custom memory
- dv simulations pass
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index d817340..7233b8a 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -11,6 +11,10 @@
// don't change the following without double checking addr widths
`define MEM_WORDS 256
+// Number of columns in the custom memory; takes one of three values:
+// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB
+`define COLS 1
+
// not really parameterized but just to easily keep track of the number
// of ram_block across different modules
`define RAM_BLOCKS 2
\ No newline at end of file
