commit: 6db38729a1312066919ca18df6f40b0a159ec0d9
[log]
author: Ganesh Gore <goreganesh007@gmail.com>
Wed Dec 16 18:11:11 2020 -0700
committer: Ganesh Gore <goreganesh007@gmail.com>
Wed Dec 16 18:11:11 2020 -0700
tree: b887cf711b842f694f8f324ad34ee940991ccc04
parent: a83c6a944a4c797d2e169fdcb25c4c21cd4a2d3c [diff]

[Cleanup] Removed travis build files

.travis.yml[Deleted - diff]
.travisCI/runPrecheck.sh[Deleted - diff]
.travisCI/travisBuild.sh[Deleted - diff]

3 files changed

tree: b887cf711b842f694f8f324ad34ee940991ccc04

README.md

Caravel-QLSOFA-HD

Highlights

Opensource 12x12 FPGA designed using OpenFPGA prototyping tool
Designed with Skywater130nm PDK with HD standard cell library + and Custom Transmission Gate Cells
Base K4 architecture from VPR with 60 vertical and horizontal channels
Soft adder implementation
Designed using commercial PnR tool

Contribution

NOTE

This repository is created for The eFabless Open MPW shuttle program submission
The repository is auto-updated. For any commits issues and feature requests, please check Skywater-OpenFPGA

Caravel design and CIIC Harness

For caravel related updated refer efabless/caravel