| commit | 589a528c7eec14294621d99747bb0850dcfae114 | [log] [tgz] |
|---|---|---|
| author | manarabdelaty <manarabdelatty@aucegypt.edu> | Sat Dec 05 01:06:48 2020 +0200 |
| committer | manarabdelaty <manarabdelatty@aucegypt.edu> | Sat Dec 05 01:06:48 2020 +0200 |
| tree | 64a4cc6b3d0f53e1ccfdff6560449668d7b995fc | |
| parent | ea96b3a6c6fa5e4c7236be9292cda5f9774c128f [diff] [blame] |
RTL updates to fix gl sim
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v index a72f0c8..b9df2bd 100644 --- a/verilog/rtl/defines.v +++ b/verilog/rtl/defines.v
@@ -21,4 +21,8 @@ `define RAM_BLOCKS 2 // Clock divisor default value -`define CLK_DIV 3'b010 \ No newline at end of file +`define CLK_DIV 3'b010 + +// GPIO conrol default mode and enable +`define DM_INIT 3'b110 +`define OENB_INIT 1'b1 \ No newline at end of file