Corrected the mess caused by introducing default_nettype none into the design
verification netlists. Also cleaned up the broken power-on-reset signaling,
and added connections from the user space to the I/O pad direct-to-pad analog
signal pins.
diff --git a/verilog/rtl/storage.v b/verilog/rtl/storage.v
index fe0eae7..a290525 100644
--- a/verilog/rtl/storage.v
+++ b/verilog/rtl/storage.v
@@ -42,4 +42,5 @@
.dout0(mgmt_rdata[63:32])
);
-endmodule
\ No newline at end of file
+endmodule
+`default_nettype wire
