"Emulate" the substrate in mgmt_protect_hv
- which is shorting grounds together
diff --git a/verilog/rtl/mgmt_protect_hv.v b/verilog/rtl/mgmt_protect_hv.v
index c1ecd0b..23d9cf6 100644
--- a/verilog/rtl/mgmt_protect_hv.v
+++ b/verilog/rtl/mgmt_protect_hv.v
@@ -42,6 +42,13 @@
wire mprj_vdd_logic1_h;
wire mprj2_vdd_logic1_h;
+`ifdef USE_POWER_PINS
+ // This is to emulate the substrate shorting grounds together for LVS
+ // purposes
+ assign vssa2 = vssa1;
+ assign vssa1 = vssd;
+`endif
+
// Logic high in the VDDA (3.3V) domains
sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl (
@@ -91,6 +98,6 @@
.X(mprj2_vdd_logic1),
.A(mprj2_vdd_logic1_h)
);
-
endmodule
+
`default_nettype wire
