Add a global defines.v and rely less on parameters
- This is mainly to avoid "accidents" with default parameter values
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
new file mode 100644
index 0000000..5cc6d03
--- /dev/null
+++ b/verilog/rtl/defines.v
@@ -0,0 +1,11 @@
+// Global parameters
+
+`define MPRJ_IO_PADS 38
+`define MPRJ_PWR_PADS 4 /* vdda1, vccd1, vdda2, vccd2 */
+
+// Size of soc_mem_synth
+`define MEM_SYNTH_WORDS 1024
+
+// Type and size of soc_mem
+`define USE_OPENRAM
+`define MEM_WORDS 256
