| commit | 1d1679d3dd324d416d116eccefe3a24ab6c8dfa0 | [log] [tgz] |
|---|---|---|
| author | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Mon Nov 30 17:44:45 2020 +0200 |
| committer | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Mon Nov 30 19:08:20 2020 +0200 |
| tree | 541a58f0d37d9dc83965916e07fc105975ab79e0 | |
| parent | 64d5115eb49f42cebb03341a6535bdaa4f1ad4e5 [diff] [blame] |
Wrap lsbufhv2lv to eliminate li1 pins at the top
diff --git a/verilog/rtl/mgmt_protect_hv.v b/verilog/rtl/mgmt_protect_hv.v index 9c8cabe..dbd04bb 100644 --- a/verilog/rtl/mgmt_protect_hv.v +++ b/verilog/rtl/mgmt_protect_hv.v
@@ -10,12 +10,14 @@ /*----------------------------------------------------------------------*/ module mgmt_protect_hv ( +`ifdef USE_POWER_PINS inout vccd, inout vssd, inout vdda1, inout vssa1, inout vdda2, inout vssa2, +`endif output mprj_vdd_logic1, output mprj2_vdd_logic1