Corrected some things from the initial pass of removing unused GPIO
signals and analog signals, and converting from EFS8A to sky130A.
Close to being able to simulate, with some hand-editing of the
standard cell library files.
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index df0ca62..f3bba5e 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -165,7 +165,7 @@
// GPIO pads
`INOUT_PAD_V(
- gpio, gpio_in_core, gpio_out_core, 16,
+ gpio, gpio_in_core, gpio_out_core, 2,
gpio_inenb_core, gpio_outenb_core, dm_all);
// Flash pads
