Vast and substantial changes: Removed the old GPIO control with the new one
that implements a shift register around the perimeter of the chip, to control
most aspects of each GPIO pad locally to avoid excessive wiring. Added modules
for the metal-programmed user ID, two counter-timers, and a general-purpose SPI
master. The SPI master can be internally directly connected to the SPI slave,
so the processor can access the housekeeping SPI in the same way as an external
host. Most signals other than 1 GPIO pin and the SPI flash controller pins were
remapped to pads in the user area, where they are active on startup and until
they are programmed for user use from the management processor. There are
several known syntax issues that need to be fixed; this is a work in progress.
diff --git a/verilog/rtl/wb_intercon.v b/verilog/rtl/wb_intercon.v
index 3a2c58f..1397cd4 100644
--- a/verilog/rtl/wb_intercon.v
+++ b/verilog/rtl/wb_intercon.v
@@ -24,12 +24,12 @@
{8'hFF, {24{1'b0}} }
};
parameter [NS*AW-1:0] SLAVE_ADR = {
- {8'h28, {24{1'b0}} }, // Flash Configuration Register
- {8'h23, {24{1'b0}} }, // System Control
- {8'h21, {24{1'b0}} }, // GPIOs
- {8'h20, {24{1'b0}} }, // UART
- {8'h10, {24{1'b0}} }, // Flash
- {8'h00, {24{1'b0}} } // RAM
+ { 32'h2800_0000 }, // Flash Configuration Register
+ { 32'h2200_0000 }, // System Control
+ { 32'h2100_0000 }, // GPIOs
+ { 32'h2000_0000 }, // UART
+ { 32'h1000_0000 }, // Flash
+ { 32'h0000_0000 } // RAM
};
wire [NS-1: 0] slave_sel;
@@ -54,4 +54,4 @@
wbm_dat_o[i%DW] = wbm_dat_o[i%DW] | (slave_sel[i/DW] & wbs_dat_i[i]);
end
-endmodule
\ No newline at end of file
+endmodule
