| # Analog & RF IPs |
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| ## LVDS Receiver |
| Design of an LVDS receiver in Skywater 130nm. The receiver architecture consists of a biasing stage followed by two amplification stages—the simulated maximum frequency of 1.5Gs at 1.8V, TT corner & 25C. |
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| Submodules: |
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| Biasing Stage – AC coupled with common-mode biasing of 1.2V |
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| CML Stage – Amplification stage with a gain of 5 |
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| Differential Stage – Gain of ~8 |
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| ## Ring Oscillator |
| 7 stage RO with enable |
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| Designed with Skywater standard cells library. AND gate followed by 7 smallest inverters |
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| ## Differential VCO |
| 5 stages of differential delay cells. Delay cell consists of symmetric loads |
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| Submodule: |
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| Self bias generator with startup circuit |
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| ## Power Amplifier |
| Linear Class AB power amplifier. On-chip inductor is designed as a test structure by using top metal layer. Actual inductance & Q factor is unknown |
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| ## Folded Cascode |
| Differential input single ended Folded Cascode Opamp; 1Mhz unity gain frequency, 60 degree phase margin & a gain of 79dB |
