| commit | b44c4ba1b2d9de93e837e880d0a8d56a4e11928e | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Fri Feb 19 02:12:02 2021 -0800 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Fri Feb 19 02:12:02 2021 -0800 |
| tree | 4f8d27e83af0b61b675b6d56a23a31fb115a80f8 | |
| parent | b39807411a7410e8568a8f3a085c9d0e0a42671f [diff] |
final gds & drc results
Design of an LVDS receiver in Skywater 130nm. The receiver architecture consists of a biasing stage followed by two amplification stages—the simulated maximum frequency of 1.5Gs at 1.8V, TT corner & 25C.
Submodules:
Biasing Stage – AC coupled with common-mode biasing of 1.2V
CML Stage – Amplification stage with a gain of 5
Differential Stage – Gain of ~8
7 stage RO with enable
Designed with Skywater standard cells library. AND gate followed by 7 smallest inverters
5 stages of differential delay cells. Delay cell consists of symmetric loads
Submodule:
Self bias generator with startup circuit
Linear Class AB power amplifier. On-chip inductor is designed as a test structure by using top metal layer. Actual inductance & Q factor is unknown
Differential input single ended Folded Cascode Opamp; 1Mhz unity gain frequency, 60 degree phase margin & a gain of 79dB
