| commit | f8b8aa889065375d770877812bca1fcdc9b54daa | [log] [tgz] |
|---|---|---|
| author | affanabbasi <69873021+affanabbasi@users.noreply.github.com> | Fri Dec 18 18:52:14 2020 -0600 |
| committer | GitHub <noreply@github.com> | Fri Dec 18 18:52:14 2020 -0600 |
| tree | 30c939e10f38e9214fd6320e5bde0922d153b057 | |
| parent | dfd24858977c2333bae8659553b01f7fc9b39044 [diff] |
Update README.md
Design of an LVDS receiver in Skywater 130nm. The receiver architecture consists of a biasing stage followed by two amplification stages—the simulated maximum frequency of 1.5Gs at 1.8V, TT corner & 25C.
Submodules:
Biasing Stage – AC coupled with common-mode biasing of 1.2V
CML Stage – Amplification stage with a gain of 5
Differential Stage – Gain of ~8
7 stage RO with enable
Designed with Skywater standard cells library. AND gate followed by 7 smallest inverters
5 stages of differential delay cells. Delay cell consists of symmetric loads
Submodule:
Self bias generator with startup circuit
Linear Class AB power amplifier. On-chip inductor is designed as a test structure by using top metal layer. Actual inductance & Q factor is unknown
Differential input single ended Folded Cascode Opamp; 1Mhz unity gain frequency, 60 degree phase margin & a gain of 79dB