| commit | e52cc5b93a85cec8ed71fa95f69a6eacd732891b | [log] [tgz] |
|---|---|---|
| author | affanabbasi <69873021+affanabbasi@users.noreply.github.com> | Fri Feb 05 22:06:24 2021 +0100 |
| committer | GitHub <noreply@github.com> | Fri Feb 05 22:06:24 2021 +0100 |
| tree | 608dc1f32e44adea89515ef032869decab4ce157 | |
| parent | 3d446ca1833382dfd6c23fa82ee44dfb18fe7098 [diff] |
Delete user_project_wrapper.mag
Design of an LVDS receiver in Skywater 130nm. The receiver architecture consists of a biasing stage followed by two amplification stages—the simulated maximum frequency of 1.5Gs at 1.8V, TT corner & 25C.
Submodules:
Biasing Stage – AC coupled with common-mode biasing of 1.2V
CML Stage – Amplification stage with a gain of 5
Differential Stage – Gain of ~8
7 stage RO with enable
Designed with Skywater standard cells library. AND gate followed by 7 smallest inverters
5 stages of differential delay cells. Delay cell consists of symmetric loads
Submodule:
Self bias generator with startup circuit
Linear Class AB power amplifier. On-chip inductor is designed as a test structure by using top metal layer. Actual inductance & Q factor is unknown
Differential input single ended Folded Cascode Opamp; 1Mhz unity gain frequency, 60 degree phase margin & a gain of 79dB