| commit | 546ae24be3f1fbae3784284944b03c61abb5d243 | [log] [tgz] |
|---|---|---|
| author | affanabbasi <69873021+affanabbasi@users.noreply.github.com> | Mon Feb 01 03:48:33 2021 +0100 |
| committer | GitHub <noreply@github.com> | Mon Feb 01 03:48:33 2021 +0100 |
| tree | 79fd9aa58d16ca5cde5cfa9c50b383cfb51b7046 | |
| parent | 2cba0da4a6eca249b2b9f6f44e7429d0e06403e8 [diff] |
DRC cleaned mag file This file is DRC cleaned, however the gds version is still showing 50 violations.
Design of an LVDS receiver in Skywater 130nm. The receiver architecture consists of a biasing stage followed by two amplification stages—the simulated maximum frequency of 1.5Gs at 1.8V, TT corner & 25C.
Submodules:
Biasing Stage – AC coupled with common-mode biasing of 1.2V
CML Stage – Amplification stage with a gain of 5
Differential Stage – Gain of ~8
7 stage RO with enable
Designed with Skywater standard cells library. AND gate followed by 7 smallest inverters
5 stages of differential delay cells. Delay cell consists of symmetric loads
Submodule:
Self bias generator with startup circuit
Linear Class AB power amplifier. On-chip inductor is designed as a test structure by using top metal layer. Actual inductance & Q factor is unknown
Differential input single ended Folded Cascode Opamp; 1Mhz unity gain frequency, 60 degree phase margin & a gain of 79dB