| commit | 3c4bb11fb9e273ba0c2e06813a12c5125d65bd38 | [log] [tgz] |
|---|---|---|
| author | affanabbasi <69873021+affanabbasi@users.noreply.github.com> | Fri Dec 18 18:53:43 2020 -0600 |
| committer | GitHub <noreply@github.com> | Fri Dec 18 18:53:43 2020 -0600 |
| tree | 940b956b5ed12f0a7eba9d55d3d50ac3f3a43328 | |
| parent | f8b8aa889065375d770877812bca1fcdc9b54daa [diff] |
Update info.yaml
Design of an LVDS receiver in Skywater 130nm. The receiver architecture consists of a biasing stage followed by two amplification stages—the simulated maximum frequency of 1.5Gs at 1.8V, TT corner & 25C.
Submodules:
Biasing Stage – AC coupled with common-mode biasing of 1.2V
CML Stage – Amplification stage with a gain of 5
Differential Stage – Gain of ~8
7 stage RO with enable
Designed with Skywater standard cells library. AND gate followed by 7 smallest inverters
5 stages of differential delay cells. Delay cell consists of symmetric loads
Submodule:
Self bias generator with startup circuit
Linear Class AB power amplifier. On-chip inductor is designed as a test structure by using top metal layer. Actual inductance & Q factor is unknown
Differential input single ended Folded Cascode Opamp; 1Mhz unity gain frequency, 60 degree phase margin & a gain of 79dB