commit | 23a74993e834ce5f76abeba0239a3b356acfdfd4 | [log] [tgz] |
---|---|---|
author | affanabbasi <69873021+affanabbasi@users.noreply.github.com> | Wed Feb 03 12:49:41 2021 -0600 |
committer | GitHub <noreply@github.com> | Wed Feb 03 12:49:41 2021 -0600 |
tree | 79fd9aa58d16ca5cde5cfa9c50b383cfb51b7046 | |
parent | 546ae24be3f1fbae3784284944b03c61abb5d243 [diff] |
DRC Cleaned Corrected more DRCs on the request from Jeff
Design of an LVDS receiver in Skywater 130nm. The receiver architecture consists of a biasing stage followed by two amplification stages—the simulated maximum frequency of 1.5Gs at 1.8V, TT corner & 25C.
Submodules:
Biasing Stage – AC coupled with common-mode biasing of 1.2V
CML Stage – Amplification stage with a gain of 5
Differential Stage – Gain of ~8
7 stage RO with enable
Designed with Skywater standard cells library. AND gate followed by 7 smallest inverters
5 stages of differential delay cells. Delay cell consists of symmetric loads
Submodule:
Self bias generator with startup circuit
Linear Class AB power amplifier. On-chip inductor is designed as a test structure by using top metal layer. Actual inductance & Q factor is unknown
Differential input single ended Folded Cascode Opamp; 1Mhz unity gain frequency, 60 degree phase margin & a gain of 79dB