commit: bc4e20635bda9d944ea7b4c15116f8d735a45cf3
[log] [tgz]
author: Ganesh Gore <goreganesh007@gmail.com>
Wed Feb 10 22:59:44 2021 -0700
committer: Ganesh Gore <goreganesh007@gmail.com>
Wed Feb 10 22:59:44 2021 -0700
tree: 2e029f73ec68b87babfcd993f70d75bad57bc862
parent: cb8b44e66ca15eb5d1908c1e7542cfe934545714 [diff]

[DRCFix] Swpapped filer cells with decap cells

gds/caravel.gds.gz[diff]
gds/fpga_top_icv_in_design.gds.gz.sha1[Deleted - diff]
gds/user_project_wrapper.gds.gz[diff]

3 files changed

tree: 2e029f73ec68b87babfcd993f70d75bad57bc862

README.md

Caravel-QLSOFA-HD

Highlights

Opensource 12x12 FPGA designed using OpenFPGA prototyping tool
Designed with Skywater130nm PDK with HD standard cell library
Base K4 architecture from VPR with 60 vertical and horizontal channels
Soft adder implementation
Designed using commercial PnR tool

Contribution

NOTE

This repository is created for The eFabless Open MPW shuttle program submission
The repository is auto-updated. For any commits issues and feature requests, please check Skywater-OpenFPGA

Caravel design and CIIC Harness

For caravel related updated refer efabless/caravel