commit: a10a63878c52dac98e5bec4f87d5c554aa5aed77
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author: Ganesh Gore <goreganesh007@gmail.com>
Mon Dec 14 14:35:07 2020 -0700
committer: Ganesh Gore <goreganesh007@gmail.com>
Mon Dec 14 14:35:07 2020 -0700
tree: 5c6fe514d8aa1c2b5c79d5843b519430ea76d550
parent: b3b1167d5793de0ecff4158e2825da4ab9b3bc0b [diff]

[Cleanup] Removed travis build

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tree: 5c6fe514d8aa1c2b5c79d5843b519430ea76d550

README.md

Caravel-QLSOFA-HD

Highlights

Opensource 12x12 FPGA designed using OpenFPGA prototyping tool
Designed with Skywater130nm PDK with HD standard cell library
Base K4 architecture from VPR with 60 vertical and horizontal channels
Soft adder implementation
Designed using commercial PnR tool

Contribution

NOTE

This repository is created for The eFabless Open MPW shuttle program submission
The repository is auto-updated. For any commits issues and feature requests, please check Skywater-OpenFPGA

Caravel design and CIIC Harness

For caravel related updated refer efabless/caravel