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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-036 / 09c175054c021f65862d70d6be688b0ada491047
commit09c175054c021f65862d70d6be688b0ada491047[log] [tgz]
authorGanesh Gore <goreganesh007@gmail.com>Sun Dec 20 23:02:58 2020 -0700
committerGanesh Gore <goreganesh007@gmail.com>Sun Dec 20 23:02:58 2020 -0700
tree5634ca2e6fec02e21604c31a3e251606e19f0b05
parent10c1ee322396292192ea3237d8dc312c5694294d [diff]
[Localrun03] Added chip art + drc clean
13 files changed
tree: 5634ca2e6fec02e21604c31a3e251606e19f0b05
  1. checks/
  2. def/
  3. doc/
  4. gds/
  5. lef/
  6. macros/
  7. mag/
  8. maglef/
  9. ngspice/
  10. OpenFPGA_task/
  11. openlane/
  12. qflow/
  13. scripts/
  14. spi/
  15. utils/
  16. verilog/
  17. info.yaml
  18. LICENSE
  19. Makefile
  20. mpw-one-b.md
  21. README.md
  22. source_commit_hash.txt
README.md

Caravel-QLSOFA-HD

Highlights

  • Opensource 12x12 FPGA designed using OpenFPGA prototyping tool
  • Designed with Skywater130nm PDK with HD standard cell library
  • Base K4 architecture from VPR with 60 vertical and horizontal channels
  • Soft adder implementation
  • Designed using commercial PnR tool

Contribution

NOTE

  • This repository is created for The eFabless Open MPW shuttle program submission
  • The repository is auto-updated. For any commits issues and feature requests, please check Skywater-OpenFPGA

Caravel design and CIIC Harness

For caravel related updated refer efabless/caravel