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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-035 / refs/heads/main / . / verilog / rtl
tree: aa151b65c75b148c9bf342061fad9fe201b7ca16 [path history] [tgz]
  1. accelerator ⇨ ../../crypto-accelerator-chip/verilog/rtl/accelerator
  2. user_project_wrapper.v ⇨ ../../crypto-accelerator-chip/verilog/rtl/user_project_wrapper.v
  3. caravel.v
  4. caravel_clocking.v
  5. caravel_netlists.v
  6. chip_io.v
  7. clock_div.v
  8. convert_gpio_sigs.v
  9. counter_timer_high.v
  10. counter_timer_low.v
  11. defines.v
  12. DFFRAM.v
  13. DFFRAMBB.v
  14. digital_pll.v
  15. digital_pll_controller.v
  16. gpio_control_block.v
  17. gpio_wb.v
  18. housekeeping_spi.v
  19. la_wb.v
  20. mem_wb.v
  21. mgmt_core.v
  22. mgmt_protect.v
  23. mgmt_protect_hv.v
  24. mgmt_soc.v
  25. mprj2_logic_high.v
  26. mprj_ctrl.v
  27. mprj_io.v
  28. mprj_logic_high.v
  29. pads.v
  30. picorv32.v
  31. README
  32. ring_osc2x13.v
  33. simple_por.v
  34. simple_spi_master.v
  35. simpleuart.v
  36. sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
  37. spimemio.v
  38. sram_1rw1r_32_256_8_sky130.v
  39. storage.v
  40. storage_bridge_wb.v
  41. sysctrl.v
  42. user_id_programming.v
  43. wb_intercon.v
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