Updates to build and testbenches
diff --git a/crypto-accelerator-chip b/crypto-accelerator-chip
index 92abfa8..ee1de94 160000
--- a/crypto-accelerator-chip
+++ b/crypto-accelerator-chip
@@ -1 +1 @@
-Subproject commit 92abfa8e6441ccae7283f213a5d5c94fb086674b
+Subproject commit ee1de946217a4aefec6b2e984eae455a6fafc00a
diff --git a/openlane/setup.sh b/openlane/setup.sh
index b5440ba..c3b768b 100644
--- a/openlane/setup.sh
+++ b/openlane/setup.sh
@@ -1,2 +1,16 @@
+#SPDX-FileCopyrightText: 2020 Anish Singhani
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
#!/bin/sh
cp ../crypto-accelerator-chip/openlane/user_project_wrapper/macro_placement.cfg user_project_wrapper/macro_placement.cfg
diff --git a/verilog/dv/caravel/accelerator/sha256/Makefile b/verilog/dv/caravel/accelerator/sha256/Makefile
new file mode 120000
index 0000000..32961ae
--- /dev/null
+++ b/verilog/dv/caravel/accelerator/sha256/Makefile
@@ -0,0 +1 @@
+../../../../../crypto-accelerator-chip/verilog/dv/caravel/accelerator/sha256/Makefile
\ No newline at end of file
diff --git a/verilog/dv/caravel/accelerator/sha256/printio.h b/verilog/dv/caravel/accelerator/sha256/printio.h
new file mode 120000
index 0000000..b7c61e9
--- /dev/null
+++ b/verilog/dv/caravel/accelerator/sha256/printio.h
@@ -0,0 +1 @@
+../../../../../crypto-accelerator-chip/verilog/dv/caravel/accelerator/sha256/printio.h
\ No newline at end of file
diff --git a/verilog/dv/caravel/accelerator/sha256/sha256.c b/verilog/dv/caravel/accelerator/sha256/sha256.c
new file mode 120000
index 0000000..442c848
--- /dev/null
+++ b/verilog/dv/caravel/accelerator/sha256/sha256.c
@@ -0,0 +1 @@
+../../../../../crypto-accelerator-chip/verilog/dv/caravel/accelerator/sha256/sha256.c
\ No newline at end of file
diff --git a/verilog/dv/caravel/accelerator/sha256/sha256_tb.v b/verilog/dv/caravel/accelerator/sha256/sha256_tb.v
new file mode 120000
index 0000000..fddc05e
--- /dev/null
+++ b/verilog/dv/caravel/accelerator/sha256/sha256_tb.v
@@ -0,0 +1 @@
+../../../../../crypto-accelerator-chip/verilog/dv/caravel/accelerator/sha256/sha256_tb.v
\ No newline at end of file
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/frame-gl.png b/verilog/dv/caravel/mgmt_soc/gpio/frame-gl.png
new file mode 100644
index 0000000..015003f
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/gpio/frame-gl.png
Binary files differ
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio.c b/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
index ae6e621..22e3e85 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
@@ -3,8 +3,38 @@
#include "printio.h"
void main() {
- unsigned int s = 0;
- for(int i = 0; i < 10000; i++) s += i;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_28 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;
+
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ //unsigned int x = 0;
+ //for(int i = 0; i < 10000; i++) x += i;
+ //printhex(x, true);
+
printstr("test\n");
printstr((char*)0x30000050);
printstr("\n");
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index f46fee9..ee5fbc6 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -36,12 +36,17 @@
clock <= 0;
end
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire gpio;
+ reg RSTB;
+
+ wire [40:0] dump = {clock, RSTB, gpio, mprj_io};
initial begin
$dumpfile("gpio.vcd");
- $dumpvars(0, gpio_tb);
+ $dumpvars(0, dump);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (25) begin
+ repeat (40) begin
repeat (1000) @(posedge clock);
$display("+1000 cycles");
end
@@ -55,7 +60,6 @@
$finish;
end
- wire [37:0] mprj_io; // Most of these are no-connects
wire [15:0] checkbits;
reg [7:0] checkbits_lo;
wire [7:0] checkbits_hi;
@@ -69,9 +73,6 @@
wire flash_clk;
wire flash_io0;
wire flash_io1;
- wire gpio;
-
- reg RSTB;
// Transactor
initial begin
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/printio.h b/verilog/dv/caravel/mgmt_soc/gpio/printio.h
index 94da39d..6568366 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/printio.h
+++ b/verilog/dv/caravel/mgmt_soc/gpio/printio.h
@@ -9,55 +9,55 @@
}
void setup_out() {
- reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
}
void write_char(char c) {
- uint32_t tmp7 = reg_mprj_io_7;
- uint32_t tmp6 = reg_mprj_io_6;
- uint32_t tmp5 = reg_mprj_io_5;
- uint32_t tmp4 = reg_mprj_io_4;
- uint32_t tmp3 = reg_mprj_io_3;
- uint32_t tmp2 = reg_mprj_io_2;
- uint32_t tmp1 = reg_mprj_io_1;
- uint32_t tmp0 = reg_mprj_io_0;
+ uint32_t tmp7 = reg_mprj_io_17;
+ uint32_t tmp6 = reg_mprj_io_16;
+ uint32_t tmp5 = reg_mprj_io_15;
+ uint32_t tmp4 = reg_mprj_io_14;
+ uint32_t tmp3 = reg_mprj_io_13;
+ uint32_t tmp2 = reg_mprj_io_12;
+ uint32_t tmp1 = reg_mprj_io_11;
+ uint32_t tmp0 = reg_mprj_io_10;
setup_out();
shift_char(c);
- reg_mprj_io_7 = tmp7;
- reg_mprj_io_6 = tmp6;
- reg_mprj_io_5 = tmp5;
- reg_mprj_io_4 = tmp4;
- reg_mprj_io_3 = tmp3;
- reg_mprj_io_2 = tmp2;
- reg_mprj_io_1 = tmp1;
- reg_mprj_io_0 = tmp0;
+ reg_mprj_io_17 = tmp7;
+ reg_mprj_io_16 = tmp6;
+ reg_mprj_io_15 = tmp5;
+ reg_mprj_io_14 = tmp4;
+ reg_mprj_io_13 = tmp3;
+ reg_mprj_io_12 = tmp2;
+ reg_mprj_io_11 = tmp1;
+ reg_mprj_io_10 = tmp0;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
}
void printhex(uint32_t x, bool newline) {
- uint32_t tmp7 = reg_mprj_io_7;
- uint32_t tmp6 = reg_mprj_io_6;
- uint32_t tmp5 = reg_mprj_io_5;
- uint32_t tmp4 = reg_mprj_io_4;
- uint32_t tmp3 = reg_mprj_io_3;
- uint32_t tmp2 = reg_mprj_io_2;
- uint32_t tmp1 = reg_mprj_io_1;
- uint32_t tmp0 = reg_mprj_io_0;
+ uint32_t tmp7 = reg_mprj_io_17;
+ uint32_t tmp6 = reg_mprj_io_16;
+ uint32_t tmp5 = reg_mprj_io_15;
+ uint32_t tmp4 = reg_mprj_io_14;
+ uint32_t tmp3 = reg_mprj_io_13;
+ uint32_t tmp2 = reg_mprj_io_12;
+ uint32_t tmp1 = reg_mprj_io_11;
+ uint32_t tmp0 = reg_mprj_io_10;
setup_out();
@@ -69,42 +69,42 @@
}
if(newline) shift_char('\n');
- reg_mprj_io_7 = tmp7;
- reg_mprj_io_6 = tmp6;
- reg_mprj_io_5 = tmp5;
- reg_mprj_io_4 = tmp4;
- reg_mprj_io_3 = tmp3;
- reg_mprj_io_2 = tmp2;
- reg_mprj_io_1 = tmp1;
- reg_mprj_io_0 = tmp0;
+ reg_mprj_io_17 = tmp7;
+ reg_mprj_io_16 = tmp6;
+ reg_mprj_io_15 = tmp5;
+ reg_mprj_io_14 = tmp4;
+ reg_mprj_io_13 = tmp3;
+ reg_mprj_io_12 = tmp2;
+ reg_mprj_io_11 = tmp1;
+ reg_mprj_io_10 = tmp0;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
}
void printstr(char *str) {
- uint32_t tmp7 = reg_mprj_io_7;
- uint32_t tmp6 = reg_mprj_io_6;
- uint32_t tmp5 = reg_mprj_io_5;
- uint32_t tmp4 = reg_mprj_io_4;
- uint32_t tmp3 = reg_mprj_io_3;
- uint32_t tmp2 = reg_mprj_io_2;
- uint32_t tmp1 = reg_mprj_io_1;
- uint32_t tmp0 = reg_mprj_io_0;
+ uint32_t tmp7 = reg_mprj_io_17;
+ uint32_t tmp6 = reg_mprj_io_16;
+ uint32_t tmp5 = reg_mprj_io_15;
+ uint32_t tmp4 = reg_mprj_io_14;
+ uint32_t tmp3 = reg_mprj_io_13;
+ uint32_t tmp2 = reg_mprj_io_12;
+ uint32_t tmp1 = reg_mprj_io_11;
+ uint32_t tmp0 = reg_mprj_io_10;
setup_out();
char c;
while (*str) shift_char(*str++);
- reg_mprj_io_7 = tmp7;
- reg_mprj_io_6 = tmp6;
- reg_mprj_io_5 = tmp5;
- reg_mprj_io_4 = tmp4;
- reg_mprj_io_3 = tmp3;
- reg_mprj_io_2 = tmp2;
- reg_mprj_io_1 = tmp1;
- reg_mprj_io_0 = tmp0;
+ reg_mprj_io_17 = tmp7;
+ reg_mprj_io_16 = tmp6;
+ reg_mprj_io_15 = tmp5;
+ reg_mprj_io_14 = tmp4;
+ reg_mprj_io_13 = tmp3;
+ reg_mprj_io_12 = tmp2;
+ reg_mprj_io_11 = tmp1;
+ reg_mprj_io_10 = tmp0;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 9966cfd..a944d9c 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -1,6 +1,6 @@
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
-module user_project_wrapper(user_clock2, wb_clk_i, wb_rst_i, wbs_ack_o, wbs_cyc_i, wbs_stb_i, wbs_we_i, vccd1, vssd1, vccd2, vssd2, vdda1, vssa1, vdda2, vssa2, analog_io, io_in, io_oeb, io_out, la_data_in, la_data_out, la_oen, wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i);
+module user_project_wrapper(wb_clk_i, wb_rst_i, wbs_stb_i, wbs_cyc_i, wbs_we_i, wbs_sel_i, wbs_dat_i, wbs_adr_i, wbs_ack_o, wbs_dat_o, la_data_in, la_data_out, la_oen, io_in, io_out, io_oeb, analog_io, user_clock2);
inout [30:0] analog_io;
input [37:0] io_in;
output [37:0] io_oeb;
@@ -9,14 +9,6 @@
output [127:0] la_data_out;
input [127:0] la_oen;
input user_clock2;
- input vccd1;
- input vccd2;
- input vdda1;
- input vdda2;
- input vssa1;
- input vssa2;
- input vssd1;
- input vssd2;
input wb_clk_i;
input wb_rst_i;
output wbs_ack_o;
@@ -34,14 +26,6 @@
.la_data_in(la_data_in),
.la_data_out(la_data_out),
.la_oen(la_oen),
- .vccd1(vccd1),
- .vccd2(vccd2),
- .vdda1(vdda1),
- .vdda2(vdda2),
- .vssa1(vssa1),
- .vssa2(vssa2),
- .vssd1(vssd1),
- .vssd2(vssd2),
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wbs_ack_o(wbs_ack_o),
diff --git a/verilog/rtl/manifest b/verilog/rtl/manifest
index a79b82a..7d42170 100644
--- a/verilog/rtl/manifest
+++ b/verilog/rtl/manifest
@@ -1,10 +1,11 @@
b2feeb2a098894d5d731a5b011858a471e855d73 caravel_clocking.v
-c39b4f6a67a044aec105ca83ef1eb6d3f2b06028 caravel.v
+fd381372c7120ced342867572a327fc4e38fc566 caravel.v
38d2c674ea1f696bf2c9deaeee5f9b044f2445fb chip_io.v
d772308bd2a72121d7ed9dcdd40c8e6cbbe4b43c clock_div.v
f937b52e53d45bdbe41bcbd07c65b41104c21756 convert_gpio_sigs.v
a16f89c8efa638eab43641ab7047bb8eeedd6fa6 counter_timer_high.v
d8eab2f4cef158e3c7800778ffc2367ab4abe130 counter_timer_low.v
+d8e0e88c860f1285e6ac6f4726f0726fc75e4858 defines.v
dab57f3c5464ce3354219840dae589a3fcd27135 DFFRAMBB.v
d328f88dd48e015bbaa95e0d7c88954343cc5632 DFFRAM.v
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 digital_pll_controller.v
@@ -29,9 +30,11 @@
917aa6e1bb869f973c79fb2c7894eab882ead74c simple_spi_master.v
7a949db8a5665540e0125bfb7544852167e821b0 simpleuart.v
ec5fa62d935e1139de104b9201740020fdea4a17 sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
-b77b7eb6ae4b253abf157a01f6f349719a81628c spimemio.v
+75dd8e88e3c550d396f6900cd5f335ec30e07fb1 spimemio.v
3b4c3de623f8af0f0780f1e5b0f2217ef6406a2f sram_1rw1r_32_256_8_sky130.v
7e8d789570ed224df49cf61f69593cc738790a5d storage_bridge_wb.v
8dea2030f1f59fc58ce50d943c395b8041ff1fb3 storage.v
5e314e94a13d7291117123395ae088e1d17cf487 sysctrl.v
+ba45c454d03c4798e0cff4ee00fe8ebd1c23d054 user_id_programming.v
+e77f840421d118db4cc3674e453e71ec49754907 user_project_wrapper.v
e6246df6bbf0860a331b3547d64f7d235b0eca9a wb_intercon.v
diff --git a/verilog/rtl/spimemio.v b/verilog/rtl/spimemio.v
index dc37126..7a21cb0 100644
--- a/verilog/rtl/spimemio.v
+++ b/verilog/rtl/spimemio.v
@@ -73,6 +73,69 @@
input flash_io3_di
);
+
+`ifdef SPOOF_FAST_FLASH
+ assign wb_cfg_ack_o = 0;
+ assign wb_cfg_dat_o = 0;
+
+ assign pass_thru_sdo = 0;
+ assign flash_csb = 0;
+ assign flash_clk = 0;
+ assign flash_csb_oeb = 0;
+ assign flash_clk_oeb = 0;
+ assign flash_io0_oeb = 0;
+ assign flash_io1_oeb = 0;
+ assign flash_io2_oeb = 0;
+ assign flash_io3_oeb = 0;
+ assign flash_csb_ieb = 0;
+ assign flash_clk_ieb = 0;
+ assign flash_io0_ieb = 0;
+ assign flash_io1_ieb = 0;
+ assign flash_io2_ieb = 0;
+ assign flash_io3_ieb = 0;
+ assign flash_io0_do = 0;
+ assign flash_io1_do = 0;
+ assign flash_io2_do = 0;
+ assign flash_io3_do = 0;
+
+ // 16 MB (128Mb) Flash
+ reg [7:0] memory [0:16*1024*1024-1];
+
+ reg ack_reg;
+ reg [31:0] dat_reg;
+
+ assign wb_flash_ack_o = ack_reg;
+ assign wb_flash_dat_o = dat_reg;
+
+ wire [31:0] adr = {7'b0, wb_adr_i[23:0]};
+
+ initial begin
+ $display("============================================================");
+ $display("Spoofing flash from file %s", `SPOOF_FAST_FLASH);
+ $display("Warning: this is experimental and \ndoes not match exact hardware behavior");
+ $display("(assumes that flash base is a multiple of 0x1000000)");
+ $display("============================================================");
+ $readmemh(`SPOOF_FAST_FLASH, memory);
+ end
+
+ always @(posedge wb_clk_i) begin
+ if (wb_cyc_i & wb_cfg_stb_i) $error("wb_cfg_stb_i unsupported in SPOOF_FAST_FLASH mode. Please use normal flash emulation.");
+ if (pass_thru) $error("pass_thru unsupported in SPOOF_FAST_FLASH mode. Please use normal flash emulation.");
+
+ ack_reg <= 0;
+
+ if (wb_cyc_i & wb_flash_stb_i & ~wb_flash_ack_o) begin
+ ack_reg <= 1;
+ dat_reg <= {memory[adr+3], memory[adr+2], memory[adr+1], memory[adr+0]};
+
+ if (wb_we_i & wb_sel_i[0]) memory[adr+0] <= wb_dat_i[7:0];
+ if (wb_we_i & wb_sel_i[1]) memory[adr+1] <= wb_dat_i[15:8];
+ if (wb_we_i & wb_sel_i[2]) memory[adr+2] <= wb_dat_i[23:16];
+ if (wb_we_i & wb_sel_i[3]) memory[adr+3] <= wb_dat_i[31:24];
+ end
+ end
+
+`else
wire spimem_ready;
wire [23:0] mem_addr;
wire [31:0] spimem_rdata;
@@ -141,6 +204,7 @@
.pass_thru_sdi(pass_thru_sdi),
.pass_thru_sdo(pass_thru_sdo)
);
+`endif
endmodule
