- 4306d9a final gds & drc results by Jeff DiCorpo · 4 years, 2 months ago
- 545efbf forgot to enable output in user_project by nqdtan · 4 years, 3 months ago
- 2985649 [warning] some minor source RTL changes for vcs compatibility by nqdtan · 4 years, 3 months ago
- d9b784d pass power pins when simulation; use VCS for now :/ by nqdtan · 4 years, 3 months ago
- a45bf65 [rtl] added wishbone src by Tan Nguyen · 4 years, 3 months ago
- e4bec99 add rtl sources, dv by Arya Reais-Parsi · 4 years, 3 months ago
- 4d78284 "Emulate" the substrate in mgmt_protect_hv by Ahmed Ghazy · 4 years, 3 months ago
- 9279a70 [DATA] update manifest by agorararmard · 4 years, 3 months ago
- d0dcdcf Add a conb cell in gpio_control_block by Ahmed Ghazy · 4 years, 3 months ago
- deaedcc [DATA] manifest update by agorararmard · 4 years, 3 months ago
- 33f5f6f Revised the GPIO control block to remove the zeroing of outputs from by Tim Edwards · 4 years, 3 months ago
- 35c88bb [DATA] Update caravel and chip_io by Ahmed Ghazy · 4 years, 3 months ago
- 442825e Refactor mgmt_protect.v into separate islands by Ahmed Ghazy · 4 years, 3 months ago
- 94dabb8 Fix the driver of the user2_vcc_powergood signal by Ahmed Ghazy · 4 years, 3 months ago
- 0bf9cd6 Update manifest files by Ahmed Ghazy · 4 years, 4 months ago
- 312a1cd [LICENSE] Add hidden SPDX headers to markdown files by agorararmard · 4 years, 4 months ago
- 6c766a8 [LICENSE] Copyright -> SPDX-FileCopyrightText: by agorararmard · 4 years, 4 months ago
- 3f2b471 [Manifest] update rtl manifest by agorararmard · 4 years, 4 months ago
- afa96ea [LICENSE] Add SPDX Identifier by agorararmard · 4 years, 4 months ago
- e5780bf [LICENSE] used addlicense to add licenses to all source files by agorararmard · 4 years, 4 months ago
- 9e76a15 [Makefile] don't include manifest when creating manifest by agorararmard · 4 years, 4 months ago
- 7eebfe4 [Makefile] Added a basic manifest target to hash rtl/.v files by agorararmard · 4 years, 4 months ago
- c752431 Added more macros under GL by manarabdelaty · 4 years, 4 months ago
- 589a528 RTL updates to fix gl sim by manarabdelaty · 4 years, 4 months ago
- 08dd483 Added global default value for the clock divisor by manarabdelaty · 4 years, 4 months ago
- 31c3465 First pruned version of the repo (~470MB w/o .git) by Ahmed Ghazy · 4 years, 4 months ago
- 9e230f8 Updated power net name in mgmt_core to match the one in the GL by manarabdelaty · 4 years, 4 months ago
- 8839d6a Correct instance names that iverilog doesn't like by Ahmed Ghazy · 4 years, 4 months ago
- 65065c6 Correct path of sky130_ef_io__gpiov2_pad_wrapped.v by Ahmed Ghazy · 4 years, 4 months ago
- a115bdd Added GL simulations by manarabdelaty · 4 years, 4 months ago
- 1d1679d Wrap lsbufhv2lv to eliminate li1 pins at the top by Ahmed Ghazy · 4 years, 4 months ago
- 14645b9 Merge branch 'develop' into new_wrapper by ax3ghazy · 4 years, 4 months ago
- 886f48b Merge pull request #9 from ax3ghazy/develop-fork by ax3ghazy · 4 years, 4 months ago
- fe9c3bb Add two more missing USE_POWER_PINS guards by Ahmed Ghazy · 4 years, 4 months ago
- 27200e9 Add more missing USE_POWER_PINS by Ahmed Ghazy · 4 years, 4 months ago
- df4dd88 Minor RTL fixes, switching to wrapped GPIOV2 by Ahmed Ghazy · 4 years, 4 months ago
- bc03551 Split the high voltage part of the mgmt_protect.v module into its own by Tim Edwards · 4 years, 4 months ago
- 1070832 Added ngspice netlist and testbenches for the power-on-reset circuit. by Tim Edwards · 4 years, 4 months ago
- 4518c62 Corrected the logic in mgmt_protect; also corrected a problem in the la_test2 by Tim Edwards · 4 years, 4 months ago
- 43e5c60 Corrections to the management protection buffer block, and a couple of corrections by Tim Edwards · 4 years, 4 months ago
- 581068f Corrected the mess caused by introducing default_nettype none into the design by Tim Edwards · 4 years, 4 months ago
- 64c17e8 Add missing USE_POWER_PINS in other modules by Ahmed Ghazy · 4 years, 4 months ago
- 69663c7 Eliminate the two inverters at the top level by Ahmed Ghazy · 4 years, 4 months ago
- 336e082 add missing signals by Matt Venn · 4 years, 4 months ago
- 08cd6eb add default nettype none by Matt Venn · 4 years, 4 months ago
- 8f13179 Updated custom memory by Manar · 4 years, 4 months ago
- 61dce92 Renamed lvs guard to use_power_pins by Manar · 4 years, 5 months ago
- ffe6cad Updated storage area by Manar · 4 years, 5 months ago
- e5ac00f Merge pull request #33 from Manarabdelaty/custom_mem by R. Timothy Edwards · 4 years, 5 months ago
- 50b0ea0 Merge pull request #32 from dan-rodrigues/user_proj_wb_ack by R. Timothy Edwards · 4 years, 5 months ago
- 68e0363 Added power pins to the custom memory cells by Manar · 4 years, 5 months ago
- 2517fa8 Add USE_CUSTOM_DFFRAM guard by Ahmed Ghazy · 4 years, 5 months ago
- b9a8c91 user_proj_example: fix wbs_ack_o wiring by Dan Rodrigues · 4 years, 5 months ago
- 5586f1b Add the custom DFF RAM by Ahmed Ghazy · 4 years, 5 months ago
- cd4cff7 Connected WB MI A port outputs to the wb bus by Manar · 4 years, 5 months ago
- 6bedda9 Added localparam for calculating mem address bits by Manar · 4 years, 5 months ago
- db08adb Updated default number of sram blocks for the user area by Manar · 4 years, 5 months ago
- cd41a1d Merge pull request #27 from ax3ghazy/conflict_warnings_fix by R. Timothy Edwards · 4 years, 5 months ago
- 706c312 Reset iomem_ready to 0 only in one block by Ahmed Ghazy · 4 years, 5 months ago
- f46273f Fix for the synthesis warnings about iomem_rdata by Ahmed Ghazy · 4 years, 5 months ago
- 55ec369 Connected storage area to mgmt_core by Manar · 4 years, 5 months ago
- 0cefb93 Seperated mgmt and user storage blocks base addresses by Manar · 4 years, 5 months ago
- 14f7ca0 Added storage area standalone rtl by Manar · 4 years, 5 months ago
- ec9b536 Removed storage area from mgmt_core by Manar · 4 years, 5 months ago
- d01c637 Modified the mprj_ctrl.v verilog to be completely clear about how by Tim Edwards · 4 years, 5 months ago
- 22d29d6 Add a global defines.v and rely less on parameters by Ahmed Ghazy · 4 years, 5 months ago
- 0445c08 Revised the mprj_ctrl module verilog so that it does not generate by Tim Edwards · 4 years, 5 months ago
- ba32890 Revised the mprj_ctrl to treat the power control as a single bit by Tim Edwards · 4 years, 5 months ago
- e6eda80 Fix a typo in a previous fix... by Ahmed Ghazy · 4 years, 5 months ago
- 0b6219d Fix to an issue with index arithmetic by Ahmed Ghazy · 4 years, 5 months ago
- 496a08a Corrected an issue with the JTAG and SDO pins that prevented them from by Tim Edwards · 4 years, 5 months ago
- 7be29a2 Made a number of modifications to the counter-timer to correctly pipeline by Tim Edwards · 4 years, 5 months ago
- 14d35ac Added synthesized memory (4kb) by Manar · 4 years, 5 months ago
- 05ad4fc Added two additional signals for monitoring the user areas 1 and 2 by Tim Edwards · 4 years, 5 months ago
- 2a62066 Merge pull request #19 from Manarabdelaty/rm_xbar by R. Timothy Edwards · 4 years, 5 months ago
- 32d0542 Added two additional features: (1) Timer chaining, which allows one by Tim Edwards · 4 years, 5 months ago
- 98a7adc Removed cross bar switch port from mgmt core by Manar · 4 years, 5 months ago
- b6dd152 Updated testbenches to declare 38 bits for the user project GPIO pins. by Tim Edwards · 4 years, 5 months ago
- 268a90b Merge pull request #18 from ax3ghazy/params by R. Timothy Edwards · 4 years, 5 months ago
- f757546 Merge pull request #15 from ax3ghazy/release by R. Timothy Edwards · 4 years, 5 months ago
- 2adba10 Fix typos in parameter names by Ahmed Ghazy · 4 years, 5 months ago
- 6d9739d Removed references to "Mega-Project" and replaced them with "User Project". by Tim Edwards · 4 years, 5 months ago
- 81d5a89 Move wire declarations before they're first used by Ahmed Ghazy · 4 years, 5 months ago
- b86fc84 (1) Added a wrapper interface between the top level verilog and the user project by Tim Edwards · 4 years, 5 months ago
- 21a9aac Testbench simulations are now all working correctly with the pre-release by Tim Edwards · 4 years, 5 months ago
- e2ef673 Additional corrections to the pads and connections for sky130_fd_io. by Tim Edwards · 4 years, 5 months ago
- 4c73335 Modified I/O references to match the sky130_fd_io release. Mostly by Tim Edwards · 4 years, 5 months ago
- 7a8cbb1 Added a secondary clock output, going to the user area, that is derived by Tim Edwards · 4 years, 5 months ago
- 53d9218 Added additional protection for all the signals output to the user by Tim Edwards · 4 years, 6 months ago
- ef2b68d Made a few testbench corrections and added the missing OEB lines from the by Tim Edwards · 4 years, 6 months ago
- 4286ae1 Made a change to all of the testbench Makefiles to define PDK_PATH as the by Tim Edwards · 4 years, 6 months ago
- f645a84 Finalized the voltage clamp arrangement and the total number of pads. by Tim Edwards · 4 years, 6 months ago
- 3245e2f Revised the clocking scheme in several ways: (1) Removed the output by Tim Edwards · 4 years, 6 months ago
- bb3cd69 Added a behavioral model for the ring oscillator, and a testbench by Tim Edwards · 4 years, 6 months ago
- 8115320 Modified code to let SPI master control the housekeeping SPI through by Tim Edwards · 4 years, 6 months ago
- 856b092 Corrected the counter/timer and made an enhancement to respond to a by Tim Edwards · 4 years, 6 months ago
- b78e1c1 Added management flash SPI pass-through mode testbench and debugged it. by Tim Edwards · 4 years, 6 months ago
- b3cef09 Removed temporary file. by Tim Edwards · 4 years, 6 months ago
- 5ae07d9 Corrected the error causing the failure of the GPIO testbench. by Tim Edwards · 4 years, 6 months ago
- 9eda80d Split the main power supply into managment and two user areas. Mostly by Tim Edwards · 4 years, 6 months ago
