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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-034 / 7ed2ba3c5302a953eb04f43468f81c0c95088403 / verilog / dv / caravel
  1. 4306d9a final gds & drc results by Jeff DiCorpo · 4 years, 2 months ago
  2. a746c10 updated readme for testing by nqdtan · 4 years, 3 months ago
  3. cb7132a added integration test with caravel soc by nqdtan · 4 years, 3 months ago
  4. 0795a1e added makefile for vcs simulation in standalone test (no caravel) by nqdtan · 4 years, 3 months ago
  5. d9b784d pass power pins when simulation; use VCS for now :/ by nqdtan · 4 years, 3 months ago
  6. d13e475 primitive_config -> standalone_test by Tan Nguyen · 4 years, 3 months ago
  7. e4bec99 add rtl sources, dv by Arya Reais-Parsi · 4 years, 3 months ago
  8. 09344bb Corrected the user project example Makefiles. by Tim Edwards · 4 years, 4 months ago
  9. 312a1cd [LICENSE] Add hidden SPDX headers to markdown files by agorararmard · 4 years, 4 months ago
  10. 3f79735 [LICENSE] Add SPDX headers to Makefiles by agorararmard · 4 years, 4 months ago
  11. 6c766a8 [LICENSE] Copyright -> SPDX-FileCopyrightText: by agorararmard · 4 years, 4 months ago
  12. afa96ea [LICENSE] Add SPDX Identifier by agorararmard · 4 years, 4 months ago
  13. e5780bf [LICENSE] used addlicense to add licenses to all source files by agorararmard · 4 years, 4 months ago
  14. c4b44ec Updated timer testbench checks to account for csb io by manarabdelaty · 4 years, 4 months ago
  15. ea96b3a Update mem.c by manarabdelaty · 4 years, 4 months ago
  16. fc7ff68 Testbench updates to force csb to 1 by manarabdelaty · 4 years, 4 months ago
  17. 5c6afe7 Corrected the GPIO testbench to force CSB high during startup, to by Tim Edwards · 4 years, 4 months ago
  18. 57c50fa Added DSIM to the simulation makefiles by manarabdelaty · 4 years, 4 months ago
  19. acdf29d Removed duplicate GL testbenches by manarabdelaty · 4 years, 4 months ago
  20. 8e065f2 Update README.md by Mohamed Kassem · 4 years, 4 months ago
  21. a115bdd Added GL simulations by manarabdelaty · 4 years, 4 months ago
  22. c2f0867 Revert platform specific changes by Dan Rodrigues · 4 years, 4 months ago
  23. 4ce2d70 Testbench and Makefile fixes to get sims running by Dan Rodrigues · 4 years, 4 months ago
  24. 4518c62 Corrected the logic in mgmt_protect; also corrected a problem in the la_test2 by Tim Edwards · 4 years, 4 months ago
  25. 43e5c60 Corrections to the management protection buffer block, and a couple of corrections by Tim Edwards · 4 years, 4 months ago
  26. 24c2085 Updates to the Makefiles for easier passing of user-specific variables, by Tim Edwards · 4 years, 4 months ago
  27. 581068f Corrected the mess caused by introducing default_nettype none into the design by Tim Edwards · 4 years, 4 months ago
  28. 08cd6eb add default nettype none by Matt Venn · 4 years, 4 months ago
  29. 61dce92 Renamed lvs guard to use_power_pins by Manar · 4 years, 5 months ago
  30. ffe6cad Updated storage area by Manar · 4 years, 5 months ago
  31. c3b9da4 Updated Makefiles to have lvs defined to use the power pins by Manar · 4 years, 5 months ago
  32. 55ec369 Connected storage area to mgmt_core by Manar · 4 years, 5 months ago
  33. ec9b536 Removed storage area from mgmt_core by Manar · 4 years, 5 months ago
  34. d01c637 Modified the mprj_ctrl.v verilog to be completely clear about how by Tim Edwards · 4 years, 5 months ago
  35. 3a1e353 Fix another 36->37 typo in mem_tb.v by Ahmed Ghazy · 4 years, 5 months ago
  36. cfe7653 Corrected the timer testbenches for minor count differences due to by Tim Edwards · 4 years, 5 months ago
  37. 0445c08 Revised the mprj_ctrl module verilog so that it does not generate by Tim Edwards · 4 years, 5 months ago
  38. ba32890 Revised the mprj_ctrl to treat the power control as a single bit by Tim Edwards · 4 years, 5 months ago
  39. 496a08a Corrected an issue with the JTAG and SDO pins that prevented them from by Tim Edwards · 4 years, 5 months ago
  40. 7be29a2 Made a number of modifications to the counter-timer to correctly pipeline by Tim Edwards · 4 years, 5 months ago
  41. 14d35ac Added synthesized memory (4kb) by Manar · 4 years, 5 months ago
  42. 32d0542 Added two additional features: (1) Timer chaining, which allows one by Tim Edwards · 4 years, 5 months ago
  43. b6dd152 Updated testbenches to declare 38 bits for the user project GPIO pins. by Tim Edwards · 4 years, 5 months ago
  44. ba04b40 Allow PDK_PATH to be user-specified by Ahmed Ghazy · 4 years, 5 months ago
  45. 63c933f Removed VCD and hex files, which should not be in the repository. by Tim Edwards · 4 years, 6 months ago
  46. b86fc84 (1) Added a wrapper interface between the top level verilog and the user project by Tim Edwards · 4 years, 6 months ago
  47. 21a9aac Testbench simulations are now all working correctly with the pre-release by Tim Edwards · 4 years, 6 months ago
  48. ef2b68d Made a few testbench corrections and added the missing OEB lines from the by Tim Edwards · 4 years, 6 months ago
  49. 4286ae1 Made a change to all of the testbench Makefiles to define PDK_PATH as the by Tim Edwards · 4 years, 6 months ago
  50. 3245e2f Revised the clocking scheme in several ways: (1) Removed the output by Tim Edwards · 4 years, 6 months ago
  51. 406d37f Solved the trap issue by not driving the PLL clock so fast (not sure why by Tim Edwards · 4 years, 6 months ago
  52. 9073946 Removed a small error in the PLL testbench C code. However, the by Tim Edwards · 4 years, 6 months ago
  53. bb3cd69 Added a behavioral model for the ring oscillator, and a testbench by Tim Edwards · 4 years, 6 months ago
  54. 8115320 Modified code to let SPI master control the housekeeping SPI through by Tim Edwards · 4 years, 6 months ago
  55. 856b092 Corrected the counter/timer and made an enhancement to respond to a by Tim Edwards · 4 years, 6 months ago
  56. b78e1c1 Added management flash SPI pass-through mode testbench and debugged it. by Tim Edwards · 4 years, 6 months ago
  57. 0c03240 Updated all the testbenches to use the new split power supplies and 37-bit by Tim Edwards · 4 years, 6 months ago
  58. 9eda80d Split the main power supply into managment and two user areas. Mostly by Tim Edwards · 4 years, 6 months ago
  59. 0553751 Most testbenches are working again now. Renamed "mprj_counter" to "user_proj_example" by Tim Edwards · 4 years, 6 months ago
  60. ca2f318 Various corrections to simplify the user project I/O wiring by Tim Edwards · 4 years, 6 months ago
  61. f51dd08 Added a simple power-on-reset circuit with schmitt trigger output, and by Tim Edwards · 4 years, 6 months ago
  62. 251e0df Serial chain loading of the I/O configurations is now working. by Tim Edwards · 4 years, 6 months ago
  63. 44bab47 In spite of many errors that still need fixing, this is a major advance by Tim Edwards · 4 years, 6 months ago
  64. 61bfc1f Corrected the primary issue with simulation, which was the failure by Tim Edwards · 4 years, 6 months ago
  65. c18c474 Fixed the syntactical loose ends from yesterday. There are by Tim Edwards · 4 years, 6 months ago
  66. 04ba17f Vast and substantial changes: Removed the old GPIO control with the new one by Tim Edwards · 4 years, 6 months ago
  67. 49e2c18 Some minor updates to the testbench Makefiles and verilog. by Tim Edwards · 4 years, 6 months ago
  68. c5265b8 Corrected some things from the initial pass of removing unused GPIO by Tim Edwards · 4 years, 6 months ago
  69. ef8312e Caravel 2nd phase (branch phase2): First pass at removing the analog by Tim Edwards · 4 years, 6 months ago