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foss-eda-tools/third_party/shuttle/sky130/mpw-001/slot-034/f744e2e9183a49c672605f2b9f3ed680184ecac4^!/./openlane
commit
f744e2e9183a49c672605f2b9f3ed680184ecac4
[log]
author
Ahmed Ghazy <ax3ghazy@aucegypt.edu>
Fri Nov 06 11:32:09 2020 +0200
committer
Ahmed Ghazy <ax3ghazy@aucegypt.edu>
Fri Nov 06 11:32:09 2020 +0200
tree
682edcfe734830e0685ed0c9df7cfe0bc330f444
parent
2170449c546f85de1775a21a16b1d045835fef03 [diff]
Update openlane configs and Makefile

- can run the Makefile outside the container now

diff --git a/openlane/Makefile b/openlane/Makefile
index 23fdf62..1b7f4ec 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile

@@ -1,7 +1,11 @@
-BLOCKS = chip_io user_project_wrapper digital_pll mgmt_core
+BLOCKS = $(shell find * -maxdepth 0 -type d)
 CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
 CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
 
+OPENLANE_IMAGE_NAME ?= openlane:rc4
+OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
+OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl"
+
 all: $(BLOCKS)
 
 $(CONFIG) :
@@ -13,14 +17,30 @@
 	@echo "Please export OPENLANE_ROOT"
 	@exit 1
 endif
+ifeq ($(PDK_ROOT),)
+	@echo "Please export PDK_ROOT"
+	@exit 1
+endif
 	@echo "###############################################"
 	@sleep 1
-	if [[ -f ./$*/interactive.tcl ]]; then\
-		${OPENLANE_ROOT}/flow.tcl -it -file ./$*/interactive.tcl;\
+
+	@if [[ -f ./$*/interactive.tcl ]]; then\
+		docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(PWD)/..:/project \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
 	else\
-		${OPENLANE_ROOT}/flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite;\
+		docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(PWD)/..:/project \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
 	fi
 
+
 FORCE:
 
 clean: 

diff --git a/openlane/chip_io/config.tcl b/openlane/chip_io/config.tcl
index 7490488..6396c77 100644
--- a/openlane/chip_io/config.tcl
+++ b/openlane/chip_io/config.tcl

@@ -3,6 +3,7 @@
 set ::env(DESIGN_NAME) chip_io
 
 set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/defines.v\
 	$script_dir/../../verilog/rtl/pads.v\
 	$script_dir/../../verilog/rtl/mprj_io.v\
 	$script_dir/../../verilog/rtl/chip_io.v"
@@ -16,3 +17,5 @@
 
 set ::env(FP_SIZING) absolute
 set ::env(DIE_AREA) "0 0 3200 5300"
+
+set ::env(MAGIC_WRITE_FULL_LEF) 1

diff --git a/openlane/chip_io/padframe.cfg b/openlane/chip_io/padframe.cfg
index f37aec8..d73bd0b 100644
--- a/openlane/chip_io/padframe.cfg
+++ b/openlane/chip_io/padframe.cfg

@@ -5,38 +5,38 @@
 CORNER user1_corner NE sky130_ef_io__corner_pad ;
 CORNER user2_corner SE sky130_ef_io__corner_pad ;
 
-PAD mprj_pads/area2_io_pad\[5\] N sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[4\] N sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[3\] N sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[2\] N sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[1\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[5\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[4\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[3\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[2\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[1\] N sky130_ef_io__gpiov2_pad ;
 PAD mgmt_vssio_hvclamp_pad\[0\] N sky130_ef_io__vssio_hvc_pad ;
-PAD mprj_pads/area2_io_pad\[0\] N sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area1_io_pad\[17\] N sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area1_io_pad\[16\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[0\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[17\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[16\] N sky130_ef_io__gpiov2_pad ;
 PAD user1_vssa_hvclamp_pad\[0\] N sky130_ef_io__vssa_hvc_pad ;
-PAD mprj_pads/area1_io_pad\[15\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[15\] N sky130_ef_io__gpiov2_pad ;
 
-PAD mprj_pads/area1_io_pad\[0\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area1_io_pad\[1\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area1_io_pad\[2\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area1_io_pad\[3\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area1_io_pad\[4\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area1_io_pad\[5\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area1_io_pad\[6\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[0\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[1\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[2\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[3\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[4\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[5\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[6\] E sky130_ef_io__gpiov2_pad ;
 PAD user1_vssa_hvclamp_pad\[1\] E sky130_ef_io__vssa_hvc_pad ;
 PAD user1_vssd_lvclmap_pad E sky130_ef_io__vssd_lvc_pad ;
 PAD user1_vdda_hvclamp_pad\[1\] E sky130_ef_io__vdda_hvc_pad ;
-PAD mprj_pads/area1_io_pad\[7\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area1_io_pad\[8\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area1_io_pad\[9\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area1_io_pad\[10\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area1_io_pad\[11\] E sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area1_io_pad\[12\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[7\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[8\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[9\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[10\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[11\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[12\] E sky130_ef_io__gpiov2_pad ;
 PAD user1_vdda_hvclamp_pad\[0\] E sky130_ef_io__vdda_hvc_pad ;
-PAD mprj_pads/area1_io_pad\[13\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[13\] E sky130_ef_io__gpiov2_pad ;
 PAD user1_vccd_lvclamp_pad E sky130_ef_io__vccd_lvc_pad ;
-PAD mprj_pads/area1_io_pad\[14\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area1_io_pad\[14\] E sky130_ef_io__gpiov2_pad ;
 
 PAD mgmt_vssa_hvclamp_pad S sky130_ef_io__vssa_hvc_pad ;
 PAD resetb_pad S sky130_fd_io__top_xres4v2 ;
@@ -52,22 +52,22 @@
 
 PAD mgmt_vccd_lvclamp_pad W sky130_ef_io__vccd_lvc_pad ;
 PAD mgmt_vddio_hvclamp_pad\[0\] W sky130_ef_io__vddio_hvc_pad ;
-PAD mprj_pads/area2_io_pad\[19\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[18\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[17\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[16\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[15\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[14\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[19\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[18\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[17\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[16\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[15\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[14\] W sky130_ef_io__gpiov2_pad ;
 PAD user2_vssd_lvclmap_pad W sky130_ef_io__vssd_lvc_pad ;
 PAD user2_vdda_hvclamp_pad W sky130_ef_io__vdda_hvc_pad ;
-PAD mprj_pads/area2_io_pad\[13\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[12\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[11\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[10\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[9\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[8\] W sky130_ef_io__gpiov2_pad ;
-PAD mprj_pads/area2_io_pad\[7\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[13\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[12\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[11\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[10\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[9\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[8\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[7\] W sky130_ef_io__gpiov2_pad ;
 PAD user2_vssa_hvclamp_pad W sky130_ef_io__vssa_hvc_pad ;
 PAD mgmt_vddio_hvclamp_pad\[1\] W sky130_ef_io__vddio_hvc_pad ;
 PAD user2_vccd_lvclamp_pad W sky130_ef_io__vccd_lvc_pad ;
-PAD mprj_pads/area2_io_pad\[6\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads.area2_io_pad\[6\] W sky130_ef_io__gpiov2_pad ;

diff --git a/openlane/gpio_control_block/config.tcl b/openlane/gpio_control_block/config.tcl
new file mode 100644
index 0000000..bb4477c
--- /dev/null
+++ b/openlane/gpio_control_block/config.tcl

@@ -0,0 +1,15 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) gpio_control_block
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/defines.v\
+	$script_dir/../../verilog/rtl/gpio_control_block.v"
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+set ::env(CLOCK_PORT) "serial_clock"
+set ::env(CLOCK_PERIOD) "10"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 50 125"

diff --git a/openlane/gpio_control_block/pin_order.cfg b/openlane/gpio_control_block/pin_order.cfg
new file mode 100644
index 0000000..bb1d52c
--- /dev/null
+++ b/openlane/gpio_control_block/pin_order.cfg

@@ -0,0 +1,10 @@
+#E
+resetn
+serial_clock
+serial_data_in
+mgmt_.*
+user_.*
+
+#W
+pad_.*
+serial_data_out

diff --git a/openlane/storage/config.tcl b/openlane/storage/config.tcl
new file mode 100644
index 0000000..689258e
--- /dev/null
+++ b/openlane/storage/config.tcl

@@ -0,0 +1,42 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) storage
+
+set ::env(CLOCK_PORT) "mgmt_clk"
+set ::env(CLOCK_PERIOD) "50"
+set ::env(SYNTH_STRATEGY) 2
+
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+#set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+# set ::env(FP_CORE_UTIL) 40
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 950 1900"
+
+set ::env(FP_HORIZONTAL_HALO) 5
+set ::env(FP_VERTICAL_HALO) 10
+set ::env(FP_PDN_VPITCH) 50
+set ::env(FP_PDN_HPITCH) 50
+
+
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
+set ::env(PL_TARGET_DENSITY) 0.45
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
+
+set ::env(GLB_RT_ADJUSTMENT) 0
+set ::env(GLB_RT_TILES) 14
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/defines.v\
+	$script_dir/../../verilog/rtl/storage.v"
+
+set ::env(VERILOG_FILES_BLACKBOX) "\
+	$script_dir/../../verilog/rtl/sram_1rw1r_32_256_8_sky130.v"
+
+set ::env(EXTRA_LEFS) "\
+	$script_dir/../../lef/sram_1rw1r_32_256_8_sky130_lp1.lef"
+
+set ::env(EXTRA_GDS_FILES) "\
+	$script_dir/../../gds/sram_1rw1r_32_256_8_sky130_lp1.gds"

diff --git a/openlane/storage/macro_placement.cfg b/openlane/storage/macro_placement.cfg
new file mode 100644
index 0000000..a5bd41d
--- /dev/null
+++ b/openlane/storage/macro_placement.cfg

@@ -0,0 +1,8 @@
+SRAM_0\[1\] 41.430 21.000 N
+SRAM_1\[0\] 41.430 491.235 N
+SRAM_1\[3\] 41.430 959.845 N
+SRAM_1\[5\] 41.430 1429.360 N
+SRAM_1\[1\] 523.985 28.885 N
+SRAM_0\[0\] 523.985 496.830 N
+SRAM_1\[2\] 523.985 969.000 N
+SRAM_1\[4\] 523.985 1429.360 N

diff --git a/openlane/storage/pdn.tcl b/openlane/storage/pdn.tcl
new file mode 100644
index 0000000..4e918b8
--- /dev/null
+++ b/openlane/storage/pdn.tcl

@@ -0,0 +1,34 @@
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    power_pins "VPWR VDD"
+    ground_pins "VGND VSS"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo $::env(FP_HORIZONTAL_HALO)
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 91dca3c..7f63031 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl

@@ -3,7 +3,10 @@
 set ::env(DESIGN_NAME) user_project_wrapper
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 
-set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/user_project_wrapper.v $script_dir/../../verilog/rtl/user_proj_example.v"
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/defines.v \
+	$script_dir/../../verilog/rtl/user_project_wrapper.v \
+	$script_dir/../../verilog/rtl/user_proj_example.v"
 
 set ::env(CLOCK_PORT) "user_clock2"
 set ::env(CLOCK_NET) "mprj.clk"