Minor RTL fixes, switching to wrapped GPIOV2
- use USER2_ABUTMENT_PINS for the second of the vssio and vddio pads
- do core-facing power-to-signal connections using the auto-router
- fix corner pad power connections and keep them for LVS purposes
- add a bunch of missing USE_POWER_PINS guards
diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v
index d8cb449..ad59c18 100644
--- a/verilog/rtl/mprj_io.v
+++ b/verilog/rtl/mprj_io.v
@@ -44,7 +44,7 @@
wire [`MPRJ_IO_PADS-1:0] loop1_io;
wire [6:0] no_connect;
- sky130_ef_io__gpiov2_pad area1_io_pad [AREA1PADS - 1:0] (
+ sky130_ef_io__gpiov2_pad_wrapped area1_io_pad [AREA1PADS - 1:0] (
`USER1_ABUTMENT_PINS
`ifndef TOP_ROUTING
.PAD(io[AREA1PADS - 1:0]),
@@ -75,7 +75,7 @@
.TIE_LO_ESD(loop1_io[AREA1PADS - 1:0])
);
- sky130_ef_io__gpiov2_pad area2_io_pad [`MPRJ_IO_PADS - AREA1PADS - 1:0] (
+ sky130_ef_io__gpiov2_pad_wrapped area2_io_pad [`MPRJ_IO_PADS - AREA1PADS - 1:0] (
`USER2_ABUTMENT_PINS
`ifndef TOP_ROUTING
.PAD(io[`MPRJ_IO_PADS - 1:AREA1PADS]),
