primitive_config -> standalone_test
diff --git a/verilog/dv/caravel/fpga_250/primitive_config/fpga250_tb.v b/verilog/dv/caravel/fpga_250/primitive_config/fpga250_tb.v
deleted file mode 100644
index 3279887..0000000
--- a/verilog/dv/caravel/fpga_250/primitive_config/fpga250_tb.v
+++ /dev/null
@@ -1,304 +0,0 @@
-// This is an adaptation of [fabric_team]/testbench/fpga_test_harness.v for
-// the user_project_wrapper in Caravel.
-
-`timescale 1ns/1ns
-
-//`include "consts.vh"
-//`define DEBUG_CONFIG
-
-module fpga250_tb();
-
- reg clk, rst;
-
- localparam FABRIC_CLOCK_PERIOD = 10; // 100 MHz
-
- initial clk = 0;
- always #(FABRIC_CLOCK_PERIOD/2) clk = ~clk;
-
- wire
-
- user_project_wrapper #(
- .BITS(32)
- ) dut (
- .wb_clk_i(clk),
- .wb_rst_i(rst),
-
- // Wishbone signals
- .wbs_stb_i(wbs_stb_i), // input
- .wbs_cyc_i(wbs_cyc_i), // input
- .wbs_we_i(wbs_we_i), // input
- // Write mask
- .wbs_sel_i(wbs_sel_i), // input
- .wbs_dat_i(wbs_data_i), // input
- .wbs_adr_i(wbs_addr_i), // input
- .wbs_ack_o(wbs_ack_o), // output
- .wbs_data_o(wbs_data_o) // output
-
- .io_in,
- .io_out(),
- .io_oeb(),
- .la_data_in(),
- .la_data_out(),
- .la_oen(),
- .analog_io(),
- .user_clock2()
- );
-
- reg [31:0] address = 32'h3000_0000;
- reg [31:0] write_data = 0;
- reg transact = 0;
- reg we = 0;
- // FIXME: assume the fabric has 4 columns for now
- reg [3:0] select = 4'b1111;
-
- wire ack;
- wire [31:0] read_data;
-
- assign wbs_stb_i = transact;
- assign wbs_cyc_i = transact;
- assign wbs_we_i = we;
- assign wbs_sel_i = select;
- assign wbs_data_i = write_data;
- assign wbs_addr_i = address;
- assign ack = wbs_ack_o;
- assign read_data = wbs_data_o;
-
- reg fabric_reset;
- assign gpio_north[9] = fabric_reset;
-
- // MSB<[bitstream(0,0), bitstream(1,0), ..., bitstream(N-1,0)],
- // [bitstream(0,1), bitstream(1,1), ..., bitstream(N-1,1)],
- // ...
- // [bitstream(0,N-1), bitstream(1,N-1), ..., bitstream(N-1,N-1)]>LSB
-
- localparam COL_BITS = `CLB_TILE_BITSTREAM_SIZE * MY;
- localparam FPGA_BITS = COL_BITS * MX;
- reg [FPGA_BITS-1:0] bitstream[1];
- reg [8*MX*MY-1:0] gold_sync_output[1];
- reg [8*MX*MY-1:0] gold_comb_output[1];
-
- reg [1023:0] load_config = 0;
- reg [1023:0] load_sync_output = 0;
- reg [1023:0] load_comb_output = 0;
-
- initial begin
- $value$plusargs("load_config=%s", load_config);
- $value$plusargs("load_sync_output=%s", load_sync_output);
- $value$plusargs("load_comb_output=%s", load_comb_output);
-
- #1 $readmemb(load_config, bitstream);
- #1 $readmemb(load_sync_output, gold_sync_output);
- #1 $readmemb(load_comb_output, gold_comb_output);
- end
-
- wire [COL_BITS-1:0] col_bitstream [MX-1:0];
-
- genvar k, x, y;
- generate
- for (k = 0; k < MX; k = k + 1) begin
- assign col_bitstream[MX-1-k] = bitstream[0][COL_BITS * (k + 1) - 1: COL_BITS * k];
- end
- endgenerate
-
- wire [8*MX*MY-1:0] fabric_sync_output;
- wire [8*MX*MY-1:0] fabric_comb_output;
-
- // Extract the current registers' states from the Fabric
- // They will be compared against the golden registers' states given by a test
- generate
- for (x = 0; x < MX; x = x + 1) begin
- for (y = 0; y < MY; y = y + 1) begin
- assign fabric_sync_output[x * MY * 8 + y * 8 +: 8] = dut.fpga.X[MX-1-x].Y[MY-1-y].clb.slice.sync_output;
- assign fabric_comb_output[x * MY * 8 + y * 8 +: 8] = dut.fpga.X[MX-1-x].Y[MY-1-y].clb.slice.comb_output;
- end
- end
- endgenerate
-
- reg debug_config = 0;
- reg failed_tests = 0;
-
- localparam NUM_BYTES = COL_BITS / 8;
- localparam REM_BITS = COL_BITS - NUM_BYTES * 8;
- integer i, j;
- initial begin
- $dumpfile("fpga_test_harness.vcd");
- $dumpvars;
-
- rst = 1'b1;
- fabric_reset= 1'b1;
- repeat (10) @(posedge clk);
-
- @(negedge clk);
- rst = 1'b0;
- fabric_reset = 1'b0;
-
- address <= 32'h3000_0001;
- write_data <= {8'hFF, 8'hFF, 8'hFF, 8'hFF};
- we <= 1;
- transact <= 1;
-
- @(posedge ack);
- transact <= 0;
- we <= 0;
- @(negedge ack);
-
- repeat(5) @(posedge clk);
-
- for (i = 0; i < NUM_BYTES; i = i + 1) begin
- // sending the bits
- address <= 32'h3000_0002;
- for (j = 0; j < MX; j = j + 1) begin
- write_data[j * 8 +: 8] <= col_bitstream[j][i * 8 +: 8];
- end
- we <= 1;
- transact <= 1;
-
- @(posedge ack);
- transact <= 0;
- we <= 0;
- @(negedge ack);
- repeat(5) @(posedge clk);
-
- end
-
- // Send the remaining bits
- address <= 32'h3000_0001;
- write_data <= {8'hFF, 8'hFF, 8'hFF, 8'hFF};
- for (i = 0; i < MX; i = i + 1) begin
- write_data[i * 8 +: 8] <= REM_BITS;
- end
-
- we <= 1;
- transact <= 1;
-
- @(posedge ack);
- transact <= 0;
- we <= 0;
- @(negedge ack);
-
- repeat(5) @(posedge clk);
-
- // sending the bits
- address <= 32'h3000_0002;
- for (i = 0; i < MX; i = i + 1) begin
- write_data[i * 8 +: 8] <= col_bitstream[i][COL_BITS - 1 : NUM_BYTES * 8];
- end
- we <= 1;
- transact <= 1;
-
- @(posedge ack);
- transact <= 0;
- we <= 0;
- @(negedge ack);
-
- repeat(5) @(posedge clk);
-
- $display("Configuration done!");
-
- repeat (100) @(posedge clk);
-
- $display("Number of bits per column: %d\n", COL_BITS);
- $display("Bitstream size: %d\n", FPGA_BITS);
-
-`ifdef DEBUG_CONFIG
- @(negedge clk);
- debug_config = 1'b1;
- @(negedge clk);
- debug_config = 1'b0;
-`endif
-
- $display("GPIO_NORTH=%b", gpio_north);
- $display("GPIO_SOUTH=%b", gpio_south);
- $display("GPIO_EAST=%b", gpio_east);
- $display("GPIO_WEST=%b", gpio_west);
-
- $display("fabric_sync_output = %b", fabric_sync_output);
- $display("gold_sync_output = %b", gold_sync_output[0]);
-
- $display("fabric_comb_output = %b", fabric_comb_output);
- $display("gold_comb_output = %b", gold_comb_output[0]);
-
- if (fabric_sync_output === gold_sync_output[0])
- $display("[sync test] PASSED!");
- else begin
- $display("[sync test] FAILED: sync_output mismatch!");
- failed_tests = failed_tests + 1;
- end
-
- if (fabric_comb_output === gold_comb_output[0])
- $display("[comb test] PASSED!");
- else begin
- $display("[comb test] FAILED: comb_output mismatch!");
- failed_tests = failed_tests + 1;
- end
-
- #100;
- $display("Fabric test done! Num tests failed: %d", failed_tests);
- $finish;
- end
-
-`ifdef DEBUG_CONFIG
- // Print the config states of all the tiles for debuggging
- generate
- for (x = 0; x < 2; x = x + 1) begin
- for (y = 0; y < 1; y = y + 1) begin
- always @(posedge clk) begin
- if (debug_config === 1'b1) begin
-
- $display("X[%d]Y[%d] S44_0 config: split=%b, LUT_1=%h, LUT_0=%h",
- x, y,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.genblk1[0].lut.split,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.genblk1[0].lut.second_lut.latches0.mem,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.genblk1[0].lut.first_lut.latches0.mem,
- );
-
- $display("X[%d]Y[%d] S44_1 config: split=%b, LUT_1=%h, LUT_0=%h",
- x, y,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.genblk1[1].lut.split,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.genblk1[1].lut.second_lut.latches0.mem,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.genblk1[1].lut.first_lut.latches0.mem,
- );
-
- $display("X[%d]Y[%d] S44_2 config: split=%b, LUT_1=%h, LUT_0=%h",
- x, y,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.genblk1[2].lut.split,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.genblk1[2].lut.second_lut.latches0.mem,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.genblk1[2].lut.first_lut.latches0.mem,
- );
-
- $display("X[%d]Y[%d] S44_3 config: split=%b, LUT_1=%h, LUT_0=%h",
- x, y,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.genblk1[3].lut.split,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.genblk1[3].lut.second_lut.latches0.mem,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.genblk1[3].lut.first_lut.latches0.mem,
- );
-
- $display("X[%d]Y[%d] clb_inter_lut_mux_config = %b",
- x, y,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.muxes.config_state);
- $display("X[%d]Y[%d] clb_config_use_cc = %b",
- x, y,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.use_cc);
- $display("X[%d]Y[%d] clb_regs_config_in = %b",
- x, y,
- dut.fpga.X[x].Y[y].clb.slice.sliceluroni.sync_out);
-
- $display("X[%d]Y[%d] cb_east_config_bits = %b",
- x, y,
- dut.fpga.X[x].Y[y].clb.cb_east.inst.connectaroni.c);
-
- $display("X[%d]Y[%d] cb_north_config_bits = %b",
- x, y,
- dut.fpga.X[x].Y[y].clb.cb_north.inst.connectaroni.c);
-
- $display("X[%d]Y[%d] sb_config_bits = %b",
- x, y,
- dut.fpga.X[x].Y[y].clb.sb.switcharoni.c);
- end
- end
- end
- end
- endgenerate
-`endif
-
-endmodule
diff --git a/verilog/dv/caravel/fpga_250/standalone_test/bitstream.txt b/verilog/dv/caravel/fpga_250/standalone_test/bitstream.txt
new file mode 100644
index 0000000..7a5f7dd
--- /dev/null
+++ b/verilog/dv/caravel/fpga_250/standalone_test/bitstream.txt
@@ -0,0 +1 @@
+0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000100000000000000001000000000000000010000000000000000100000000000000001000000000000000010000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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\ No newline at end of file
diff --git a/verilog/dv/caravel/fpga_250/standalone_test/comb_output.txt b/verilog/dv/caravel/fpga_250/standalone_test/comb_output.txt
new file mode 100644
index 0000000..c17f38b
--- /dev/null
+++ b/verilog/dv/caravel/fpga_250/standalone_test/comb_output.txt
@@ -0,0 +1 @@
+xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
\ No newline at end of file
diff --git a/verilog/dv/caravel/fpga_250/standalone_test/fpga_consts.vh b/verilog/dv/caravel/fpga_250/standalone_test/fpga_consts.vh
new file mode 100644
index 0000000..4523ef2
--- /dev/null
+++ b/verilog/dv/caravel/fpga_250/standalone_test/fpga_consts.vh
@@ -0,0 +1,187 @@
+
+// CLB Tile: {CLB, CB, CB, SB, CFG}
+//
+// Example: 2x2 array of CLB Tiles
+// ______________ ______________
+// | CB1 -- SW | | CB1 -- SW |
+// | CLB -- CB0 | | CLB -- CB0 |
+// | CFG | | CFG |
+// |____________| |____________|
+// ______________ ______________
+// | CB1 -- SW | | CB1 -- SW |
+// | CLB -- CB0 | | CLB -- CB0 |
+// | CFG | | CFG |
+// |____________| |____________|
+//
+
+// Array dimension
+`define NUM_ROWS 8
+`define NUM_COLS 7
+
+// LUT parameters
+`define S_XX_BASE 4
+`define NUM_LUTS 4
+
+// Interconnect parameters
+`define WS 4
+`define WD 8
+`define WG 0
+`define CLBOS 4
+`define CLBOD 4
+`define CLBX 1
+
+
+`define NUM_CLB_TILES (`NUM_ROWS * `NUM_COLS)
+`define LUT_CFG_SIZE (2 * (2 ** `S_XX_BASE) + 1)
+`define MUX_LVLS $clog2(`NUM_LUTS)
+
+// 1x S44 LUT inputs, Inter-LUT MUX inputs, reg_ce
+`define NUM_CLB_INS 10 // (2 * `S_XX_BASE + `MUX_LVLS + 1)
+
+// 2x Comb. outputs, Sync. outputs
+`define NUM_CLB_OUTS 5 // (2 * 2)
+
+`define SWITCH_PER_IN (`WS + `WD + `WG + `CLBX * `NUM_CLB_OUTS)
+`define SWITCH_PER_OUT (`CLBOS + `CLBOD)
+
+`define CLB_COMB_CFG_SIZE (`LUT_CFG_SIZE * `NUM_LUTS + `MUX_LVLS + 1)
+`define CLB_MEM_CFG_SIZE (2 * `NUM_LUTS)
+`define CB_CFG_SIZE (2 * (`NUM_CLB_INS * `SWITCH_PER_IN + `NUM_CLB_OUTS * `SWITCH_PER_OUT))
+
+`define SB_CFG_SIZE (`WS + `WD / 2) * 6
+`define CLB_TILE_COMB_CFG_SIZE (`CLB_COMB_CFG_SIZE + `SB_CFG_SIZE + `CB_CFG_SIZE * 2)
+`define CLB_TILE_MEM_CFG_SIZE (`CLB_MEM_CFG_SIZE)
+
+`define CLB_TILE_BITSTREAM_SIZE (`CLB_TILE_COMB_CFG_SIZE + `CLB_TILE_MEM_CFG_SIZE + 2 + 2 + 2 + 2)
+
+// Define the sequence of configuration bits for a tile
+`define CFG_MEM_START_BIT 0
+`define CFG_MEM_END_BIT `CFG_MEM_START_BIT + `CLB_MEM_CFG_SIZE - 1
+`define CFG_USE_CC_START_BIT 0
+`define CFG_USE_CC_END_BIT `CFG_USE_CC_START_BIT + 1 - 1
+`define CFG_IXLUTMUX_START_BIT `CFG_USE_CC_END_BIT + 1
+`define CFG_IXLUTMUX_END_BIT `CFG_IXLUTMUX_START_BIT + `MUX_LVLS - 1
+`define CFG_LUTS_START_BIT `CFG_IXLUTMUX_END_BIT + 1
+`define CFG_LUTS_END_BIT `CFG_LUTS_START_BIT + `LUT_CFG_SIZE * `NUM_LUTS - 1
+`define CFG_CB0_START_BIT `CFG_LUTS_END_BIT + 1
+`define CFG_CB0_END_BIT `CFG_CB0_START_BIT + `CB_CFG_SIZE - 1
+`define CFG_CB1_START_BIT `CFG_CB0_END_BIT + 1
+`define CFG_CB1_END_BIT `CFG_CB1_START_BIT + `CB_CFG_SIZE - 1
+`define CFG_SB_START_BIT `CFG_CB1_END_BIT + 1
+`define CFG_SB_END_BIT `CFG_SB_START_BIT + `SB_CFG_SIZE - 1
+
+`define CB_OFFSET0 (`NUM_CLB_INS * `SWITCH_PER_IN)
+`define CB_OFFSET1 (`CB_OFFSET0 + `NUM_CLB_OUTS * `SWITCH_PER_OUT)
+`define CB_OFFSET2 (`CB_OFFSET1 + `NUM_CLB_INS * `SWITCH_PER_IN)
+`define SB_OFFSET0 (12 * (`WS / 2))
+
+// Helper functions for switching connectivity
+
+// SINGLE WIRES
+// Connect wire single0[m] of Connection Block to CLB input n (from the same tile)
+`define CB_SINGLE0_TO_CLB0_IN(m, n) (`SWITCH_PER_IN * n + m)
+// Connect CLB output m to wire single0[n] of Connection Block (from the same tile)
+`define CLB0_OUT_TO_CB_SINGLE0(m, n) (`CB_OFFSET0 + `SWITCH_PER_OUT * m + n)
+// Connect wire single0[m] of Connection Block to CLB input m (from an adjacent tile)
+`define CB_SINGLE0_TO_CLB1_IN(m, n) (`CB_OFFSET1 + `SWITCH_PER_IN * n + m)
+// Connect CLB output m to wire single0[n] of Connection Block (from an adjacent tile)
+`define CLB1_OUT_TO_CB_SINGLE0(m, n) (`CB_OFFSET2 + `SWITCH_PER_OUT * m + n)
+
+// DOUBLE WIRES
+// Note that with CLBOD = 4, only double[3], double[2], double[1], double[0] wires
+// can be connect to CLB output pins
+// Reference: ix_yukio/src/connection_block.v
+// Connect wire single0[m] of Connection Block to CLB input n (from the same tile)
+`define CB_DOUBLE0_TO_CLB0_IN(m, n) (`SWITCH_PER_IN * n + `WS + m)
+// Connect CLB output m to wire single0[n] of Connection Block (from the same tile)
+`define CLB0_OUT_TO_CB_DOUBLE0(m, n) (`CB_OFFSET0 + `SWITCH_PER_OUT * m + `CLBOS + n)
+// Connect wire single0[m] of Connection Block to CLB input m (from an adjacent tile)
+`define CB_DOUBLE0_TO_CLB1_IN(m, n) (`CB_OFFSET1 + `SWITCH_PER_IN * n + `WS + m)
+// Connect CLB output m to wire single0[n] of Connection Block (from an adjacent tile)
+`define CLB1_OUT_TO_CB_DOUBLE0(m, n) (`CB_OFFSET2 + `SWITCH_PER_OUT * m + `CLBOS + n)
+
+// Connect CLB output m (from an adjacent tile) to CLB input n
+`define CLB1_OUT_TO_CLB0_IN(m, n) (`SWITCH_PER_IN * m + `WS + `WD + n)
+// Connect CLB output m to CLB input (from an adjacent tile)
+`define CLB0_OUT_TO_CLB1_IN(m, n) (`CB_OFFSET1 + `SWITCH_PER_IN * m + `WS + `WD + n)
+
+// Indices of Config bits for Switchbox PIPs
+// Reference: ix_yukio/src/switch_box_element_two.v
+//
+// Convention: {Dir1}{Wire1}{Dir2}{Wire2}: enabling the connectivity of
+// wire `Wire1` coming from `Dir1` and wire `Wire2` coming from `Dir2`
+//
+// Wire1 = {0, 1}, Wire2 = {0, 1}, Dir1 = {N, S, E, W}, Dir2 = {N, S, E, W}
+//
+// Note that {Dir1}{Wire1}{Dir2}{Wire2} and {Dir2}{Wire2}{Dir1}{Wire1} are
+// the same (bi-directional)
+//
+// Each wire connects to three different directions => 8 * 3 / 2 = 12 PIPs inside
+// switch_box_element_two (SBE2)
+
+`define NUM_SBE2_PIPS 12
+
+`define SINGLE_N0E0(x) (`NUM_SBE2_PIPS * x + 0)
+`define SINGLE_N0S0(x) (`NUM_SBE2_PIPS * x + 4)
+`define SINGLE_N0W1(x) (`NUM_SBE2_PIPS * x + 11)
+
+`define SINGLE_N1E1(x) (`NUM_SBE2_PIPS * x + 8)
+`define SINGLE_N1S1(x) (`NUM_SBE2_PIPS * x + 6)
+`define SINGLE_N1W0(x) (`NUM_SBE2_PIPS * x + 3)
+
+`define SINGLE_E0W0(x) (`NUM_SBE2_PIPS * x + 7)
+`define SINGLE_E0N0(x) (`NUM_SBE2_PIPS * x + 0)
+`define SINGLE_E0S1(x) (`NUM_SBE2_PIPS * x + 9)
+
+`define SINGLE_E1W1(x) (`NUM_SBE2_PIPS * x + 5)
+`define SINGLE_E1N1(x) (`NUM_SBE2_PIPS * x + 8)
+`define SINGLE_E1S0(x) (`NUM_SBE2_PIPS * x + 1)
+
+`define SINGLE_S0W0(x) (`NUM_SBE2_PIPS * x + 10)
+`define SINGLE_S0N0(x) (`NUM_SBE2_PIPS * x + 4)
+`define SINGLE_S0E1(x) (`NUM_SBE2_PIPS * x + 1)
+
+`define SINGLE_S1W1(x) (`NUM_SBE2_PIPS * x + 2)
+`define SINGLE_S1N1(x) (`NUM_SBE2_PIPS * x + 6)
+`define SINGLE_S1E0(x) (`NUM_SBE2_PIPS * x + 9)
+
+`define SINGLE_W0E0(x) (`NUM_SBE2_PIPS * x + 7)
+`define SINGLE_W0S0(x) (`NUM_SBE2_PIPS * x + 10)
+`define SINGLE_W0N1(x) (`NUM_SBE2_PIPS * x + 3)
+
+`define SINGLE_W1E1(x) (`NUM_SBE2_PIPS * x + 5)
+`define SINGLE_W1S1(x) (`NUM_SBE2_PIPS * x + 2)
+`define SINGLE_W1N0(x) (`NUM_SBE2_PIPS * x + 11)
+
+`define DOUBLE_N0E0(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 0)
+`define DOUBLE_N0S0(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 4)
+`define DOUBLE_N0W1(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 11)
+
+`define DOUBLE_N1E1(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 8)
+`define DOUBLE_N1S1(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 6)
+`define DOUBLE_N1W0(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 3)
+
+`define DOUBLE_E0W0(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 7)
+`define DOUBLE_E0N0(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 0)
+`define DOUBLE_E0S1(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 9)
+
+`define DOUBLE_E1W1(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 5)
+`define DOUBLE_E1N1(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 8)
+`define DOUBLE_E1S0(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 1)
+
+`define DOUBLE_S0W0(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 10)
+`define DOUBLE_S0N0(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 4)
+`define DOUBLE_S0E1(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 1)
+
+`define DOUBLE_S1W1(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 2)
+`define DOUBLE_S1N1(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 6)
+`define DOUBLE_S1E0(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 9)
+
+`define DOUBLE_W0E0(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 7)
+`define DOUBLE_W0S0(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 10)
+`define DOUBLE_W0N1(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 3)
+
+`define DOUBLE_W1E1(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 5)
+`define DOUBLE_W1S1(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 2)
+`define DOUBLE_W1N0(x) ((`WS / 2) * `NUM_SBE2_PIPS + `NUM_SBE2_PIPS * x + 11)
+
diff --git a/verilog/dv/caravel/fpga_250/standalone_test/gpio_output.txt b/verilog/dv/caravel/fpga_250/standalone_test/gpio_output.txt
new file mode 100644
index 0000000..33c5a38
--- /dev/null
+++ b/verilog/dv/caravel/fpga_250/standalone_test/gpio_output.txt
@@ -0,0 +1 @@
+0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
\ No newline at end of file
diff --git a/verilog/dv/caravel/fpga_250/standalone_test/sync_output.txt b/verilog/dv/caravel/fpga_250/standalone_test/sync_output.txt
new file mode 100644
index 0000000..960b8a7
--- /dev/null
+++ b/verilog/dv/caravel/fpga_250/standalone_test/sync_output.txt
@@ -0,0 +1 @@
+0000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
\ No newline at end of file
diff --git a/verilog/dv/caravel/fpga_250/standalone_test/user_project_wrapper_tb.v b/verilog/dv/caravel/fpga_250/standalone_test/user_project_wrapper_tb.v
new file mode 100644
index 0000000..cf32091
--- /dev/null
+++ b/verilog/dv/caravel/fpga_250/standalone_test/user_project_wrapper_tb.v
@@ -0,0 +1,343 @@
+// This is an adaptation of [fabric_team]/testbench/fpga_test_harness.v for
+// the user_project_wrapper in Caravel.
+
+`timescale 1ns/1ns
+
+`include "defines.v"
+
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+
+`include "fpga_consts.vh"
+`include "user_project_wrapper.v"
+
+module user_project_wrapper_tb();
+
+ reg clk, rst;
+
+ localparam CLOCK_PERIOD = 12.5;
+
+ initial clk = 0;
+ always #(CLOCK_PERIOD/2) clk = ~clk;
+
+ // Array is 8 rows x 7 columns of CLB tiles
+ localparam MX = 7;
+ localparam MY = 8;
+
+ // We use two Wishbone modules to load the bitstream
+ localparam NUM_CONFIG_REGIONS = 2;
+
+ // Wishbone signals
+ wire wbs_stb_i;
+ wire wbs_cyc_i;
+ wire wbs_we_i;
+
+ // Write mask
+ wire [3:0] wbs_sel_i;
+ wire [31:0] wbs_data_i;
+ wire [31:0] wbs_addr_i;
+ wire wbs_ack_o;
+ wire [31:0] wbs_data_o;
+
+ // mprj_io ~ io_in ~ io_out (bidir)
+ wire [`MPRJ_IO_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-1:0] io_out;
+
+ user_project_wrapper dut (
+ .wb_clk_i(clk),
+ .wb_rst_i(rst),
+
+ // Wishbone signals
+ .wbs_stb_i(wbs_stb_i), // input
+ .wbs_cyc_i(wbs_cyc_i), // input
+ .wbs_we_i(wbs_we_i), // input
+ // Write mask
+ .wbs_sel_i(wbs_sel_i), // input
+ .wbs_dat_i(wbs_data_i), // input
+ .wbs_adr_i(wbs_addr_i), // input
+ .wbs_ack_o(wbs_ack_o), // output
+ .wbs_dat_o(wbs_data_o), // output
+
+ // IOs
+ .io_in(io_in),
+ .io_out(io_out),
+ .io_oeb(),
+
+ // Logic Analyzer Signals
+ .la_data_in(),
+ .la_data_out(),
+ .la_oen(),
+
+ .analog_io(),
+ .user_clock2()
+ );
+
+ reg [31:0] address = 32'h3000_0000;
+ reg [31:0] write_data = 0;
+ reg transact = 0;
+ reg we = 0;
+ reg [3:0] select = 4'b1111;
+
+ wire [1:0] ack;
+ wire [31:0] read_data;
+
+ assign wbs_stb_i = transact;
+ assign wbs_cyc_i = transact;
+ assign wbs_we_i = we;
+ assign wbs_sel_i = select;
+ assign wbs_data_i = write_data;
+ assign wbs_addr_i = address;
+ assign ack = wbs_ack_o;
+ assign read_data = wbs_data_o;
+
+ reg fabric_reset;
+ assign io_in[10] = fabric_reset;
+
+ // MSB<[bitstream(0,0), bitstream(1,0), ..., bitstream(N-1,0)],
+ // [bitstream(0,1), bitstream(1,1), ..., bitstream(N-1,1)],
+ // ...
+ // [bitstream(0,N-1), bitstream(1,N-1), ..., bitstream(N-1,N-1)]>LSB
+
+ localparam COL_BITS = `CLB_TILE_BITSTREAM_SIZE * MY;
+ localparam FPGA_BITS = COL_BITS * MX;
+ reg [FPGA_BITS-1:0] bitstream[1];
+ reg [8*MX*MY-1:0] gold_sync_output[1];
+ reg [8*MX*MY-1:0] gold_comb_output[1];
+ reg [`MPRJ_IO_PADS-1:0] gold_gpio_output[1];
+
+ reg [1023:0] load_config = 0;
+ reg [1023:0] load_sync_output = 0;
+ reg [1023:0] load_comb_output = 0;
+ reg [1023:0] load_gpio_output = 0;
+ reg status = 0;
+ initial begin
+ #0.1 status = $value$plusargs("load_config=%s", load_config);
+ #0.1 status = $value$plusargs("load_sync_output=%s", load_sync_output);
+ #0.1 status = $value$plusargs("load_comb_output=%s", load_comb_output);
+ #0.1 status = $value$plusargs("load_gpio_output=%s", load_gpio_output);
+
+ #1;
+ $readmemb(load_config, bitstream);
+ $readmemb(load_sync_output, gold_sync_output);
+ $readmemb(load_comb_output, gold_comb_output);
+ $readmemb(load_gpio_output, gold_gpio_output);
+ end
+
+ wire [COL_BITS-1:0] col_bitstream [MX-1:0];
+
+ genvar k, x, y;
+ generate
+ for (k = 0; k < MX; k = k + 1) begin
+ assign col_bitstream[MX-1-k] = bitstream[0][COL_BITS * (k + 1) - 1: COL_BITS * k];
+ end
+ endgenerate
+
+ wire [8*MX*MY-1:0] fabric_sync_output;
+ wire [8*MX*MY-1:0] fabric_comb_output;
+
+ // Extract the current registers' states from the Fabric
+ // They will be compared against the golden registers' states given by a test
+ generate
+ for (x = 0; x < MX; x = x + 1) begin
+ for (y = 0; y < MY; y = y + 1) begin
+`ifndef GATE_LV
+ assign fabric_sync_output[x * MY * 8 + y * 8 +: 8] = dut.fpga250.X[MX-1-x].Y[MY-1-y].clb.slice.sync_output;
+ assign fabric_comb_output[x * MY * 8 + y * 8 +: 8] = dut.fpga250.X[MX-1-x].Y[MY-1-y].clb.slice.comb_output;
+`endif
+ end
+ end
+ endgenerate
+
+// always @(posedge clk) begin
+// $display("[At %t] TEST shift00=%b cen00=%b set_out00=%b, shift10=%b, cen10=%b, set_out10=%b", $time,
+// dut.fpga250.wishbonatron_00.shift_out,
+// dut.fpga250.wishbonatron_00.cen,
+// dut.fpga250.wishbonatron_00.set_out,
+//
+// dut.fpga250.wishbonatron_10.shift_out,
+// dut.fpga250.wishbonatron_10.cen,
+// dut.fpga250.wishbonatron_10.set_out);
+// end
+
+ reg failed_tests = 0;
+
+ localparam NUM_BYTES = COL_BITS / 8;
+ localparam REM_BITS = COL_BITS - NUM_BYTES * 8;
+ integer i, j, z, wb;
+ initial begin
+ //$dumpfile("fpga_test_harness.vcd");
+ //$dumpvars;
+
+ rst = 1'b1;
+ fabric_reset= 1'b1;
+ repeat (10) @(posedge clk);
+
+ @(negedge clk);
+ rst = 1'b0;
+ fabric_reset = 1'b0;
+
+ for (wb = 0; wb < NUM_CONFIG_REGIONS; wb = wb + 1) begin
+ // Wishbone wb
+ address <= 32'h3000_0004 + (wb << 4);
+ write_data <= {8'hFF, 8'hFF, 8'hFF, 8'hFF};
+ we <= 1;
+ transact <= 1;
+
+ @(posedge ack);
+ transact <= 0;
+ we <= 0;
+
+ @(negedge ack);
+ end
+
+ for (wb = 0; wb < NUM_CONFIG_REGIONS; wb = wb + 1) begin
+ for (i = 0; i < NUM_BYTES; i = i + 1) begin
+ // sending the bits
+ address <= 32'h3000_0008 + (wb << 4);
+ for (j = wb * 4; j < wb * 4 + 4; j = j + 1) begin
+ if (j < MX)
+ write_data[(j % 4) * 8 +: 8] <= col_bitstream[j][i * 8 +: 8];
+ end
+ we <= 1;
+ transact <= 1;
+
+ @(posedge ack);
+ transact <= 0;
+ we <= 0;
+ @(negedge ack);
+
+ repeat(5) @(posedge clk);
+ end
+ end
+
+ if (REM_BITS > 0) begin
+ // Send the remaining bits
+ for (wb = 0; wb < NUM_CONFIG_REGIONS; wb = wb + 1) begin
+ address <= 32'h3000_0004 + (wb << 4);
+ for (i = wb * 4; i < wb * 4 + 4; i = i + 1) begin
+ if (i < MX)
+ write_data[(i % 4) * 8 +: 8] <= REM_BITS;
+ end
+
+ we <= 1;
+ transact <= 1;
+
+ @(posedge ack);
+ transact <= 0;
+ we <= 0;
+ @(negedge ack);
+
+ repeat(5) @(posedge clk);
+ end
+
+ for (wb = 0; wb < NUM_CONFIG_REGIONS; wb = wb + 1) begin
+ // sending the bits
+ address <= 32'h3000_0008 + (wb << 4);
+ for (i = wb * 4; i < wb * 4 + 4; i = i + 1) begin
+ if (i < MX)
+ for (z = 0; z < REM_BITS; z = z + 1)
+ write_data[(i % 4) * 8 + z] <= col_bitstream[i][NUM_BYTES * 8 + z];
+ end
+ we <= 1;
+ transact <= 1;
+
+ @(posedge ack);
+ transact <= 0;
+ we <= 0;
+ @(negedge ack);
+
+ repeat(5) @(posedge clk);
+ end
+ end
+ else begin
+ // Set the counters to 0 to fire cen
+ for (wb = 0; wb < NUM_CONFIG_REGIONS; wb = wb + 1) begin
+ address <= 32'h3000_0004 + (wb << 4);
+ write_data = {8'h00, 8'h00, 8'h00, 8'h00};
+
+ we <= 1;
+ transact <= 1;
+
+ @(posedge ack);
+ transact <= 0;
+ we <= 0;
+ @(negedge ack);
+
+ repeat(5) @(posedge clk);
+ end
+
+ for (wb = 0; wb < NUM_CONFIG_REGIONS; wb = wb + 1) begin
+ // We don't actually send anything here
+ address <= 32'h3000_0008 + (wb << 4);
+ we <= 1;
+ transact <= 1;
+
+ @(posedge ack);
+ transact <= 0;
+ we <= 1;
+ @(negedge ack);
+
+ repeat(5) @(posedge clk);
+ end
+ end
+
+ repeat(5) @(posedge clk);
+
+ $display("Configuration done!");
+
+ repeat (100) @(posedge clk);
+
+ $display("Number of bits per column: %d\n", COL_BITS);
+ $display("Bitstream size: %d\n", FPGA_BITS);
+
+ $display("GPIO_NORTH=%b", dut.fpga250.gpio_north);
+ $display("GPIO_SOUTH=%b", dut.fpga250.gpio_south);
+ $display("GPIO_EAST=%b", dut.fpga250.gpio_east);
+ $display("GPIO_WEST=%b", dut.fpga250.gpio_west);
+
+ $display("fabric_gpio_output = %b",
+ {dut.fpga250.gpio_north,
+ dut.fpga250.gpio_south,
+ dut.fpga250.gpio_east,
+ dut.fpga250.gpio_west});
+ $display("gold_gpio_output = %b", gold_gpio_output[0]);
+
+ if ({dut.fpga250.gpio_north,
+ dut.fpga250.gpio_south,
+ dut.fpga250.gpio_east,
+ dut.fpga250.gpio_west} === gold_gpio_output[0])
+ $display("[gpio test] PASSED!");
+ else begin
+ $display("[gpio test] FAILED: gpio_output mismatch!");
+ failed_tests = failed_tests + 1;
+ end
+
+`ifndef GATE_LV
+
+ $display("fabric_sync_output = %b", fabric_sync_output);
+ $display("gold_sync_output = %b", gold_sync_output[0]);
+
+ $display("fabric_comb_output = %b", fabric_comb_output);
+ $display("gold_comb_output = %b", gold_comb_output[0]);
+
+ if (fabric_sync_output === gold_sync_output[0])
+ $display("[sync test] PASSED!");
+ else begin
+ $display("[sync test] FAILED: sync_output mismatch!");
+ failed_tests = failed_tests + 1;
+ end
+
+ if (fabric_comb_output === gold_comb_output[0])
+ $display("[comb test] PASSED!");
+ else begin
+ $display("[comb test] FAILED: comb_output mismatch!");
+ failed_tests = failed_tests + 1;
+ end
+`endif
+
+ #100;
+ $display("Fabric test done! Num tests failed: %d", failed_tests);
+ $finish;
+ end
+
+endmodule
