commit c752431b89db399edff09e826d67ddca73c0db5f
author manarabdelaty <manarabdelatty@aucegypt.edu> Mon Dec 07 18:13:54 2020 +0200
committer manarabdelaty <manarabdelatty@aucegypt.edu> Mon Dec 07 18:13:54 2020 +0200
tree def6fffecc7bda7f9538f1430f44b64eb6e70c3c
parent c4b44ece687c33b21597ff003ea38ab2f14da328

Added more macros under GL

- updated chip_io.v GL
- renamed user_id_programming power ports to match the GL

verilog/rtl/user_id_programming.v

diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
index 934f9d7..ce1f42b 100644
--- a/verilog/rtl/user_id_programming.v
+++ b/verilog/rtl/user_id_programming.v
@@ -8,8 +8,8 @@
     parameter [ 0:0] USER_PROJECT_ID = 32'h0
 ) (
 `ifdef USE_POWER_PINS
-    inout vdd1v8,
-    inout vss,
+    inout VPWR,
+    inout VGND,
 `endif
     output [31:0] mask_rev
 );
@@ -21,10 +21,10 @@
 
     sky130_fd_sc_hd__conb_1 mask_rev_value [31:0] (
 `ifdef USE_POWER_PINS
-            .VPWR(vdd1v8),
-            .VPB(vdd1v8),
-            .VNB(vss),
-            .VGND(vss),
+            .VPWR(VPWR),
+            .VPB(VPWR),
+            .VNB(VGND),
+            .VGND(VGND),
 `endif
             .HI(user_proj_id_high),
             .LO(user_proj_id_low)