Added GL simulations
- updated mgmt_core gl netlist to the one with tri-state buffers
- updated mgmt_core and digital_pll power pin names to match the names in the powered GL netlist
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index bd3a167..46cfdfd 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -30,11 +30,16 @@
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
-`include "mgmt_soc.v"
-`include "housekeeping_spi.v"
+`ifdef GL
+ `include "gl/mgmt_core.v"
+`else
+ `include "mgmt_soc.v"
+ `include "housekeeping_spi.v"
+ `include "caravel_clocking.v"
+ `include "mgmt_core.v"
+`endif
+
`include "digital_pll.v"
-`include "caravel_clocking.v"
-`include "mgmt_core.v"
`include "mgmt_protect.v"
`include "mgmt_protect_hv.v"
`include "mprj_io.v"
@@ -356,8 +361,8 @@
mgmt_core soc (
`ifdef USE_POWER_PINS
- .vdd1v8(vccd),
- .vss(vssa),
+ .VPWR(vccd),
+ .VGND(vssa),
`endif
// GPIO (1 pin)
.gpio_out_pad(gpio_out_core),
