| commit | 89f09245bc3e3669420ed982c7f18f365b9f5e15 | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Mon Oct 05 15:17:34 2020 -0400 |
| committer | Tim Edwards <tim@opencircuitdesign.com> | Mon Oct 05 15:17:34 2020 -0400 |
| tree | 666d354f569bbef74d68abb6684c9a8c7b6b5126 | |
| parent | 251e0dfa4145a7f77ed08eafcd106ab9af43b411 [diff] [blame] |
Made corrections; GPIO testbench now passes.
diff --git a/verilog/rtl/README b/verilog/rtl/README index ec44791..1ac0025 100644 --- a/verilog/rtl/README +++ b/verilog/rtl/README
@@ -151,7 +151,7 @@ Standard GPIO output configuration: - mprj_io[6] Tx, UART 110 0 0 0 0 0 0 0 0 0 1 + mprj_io[6] Tx, UART 110 0 0 0 0 0 0 1 0 0 1 Standard GPIO input configuration: mprj_io[*] 001 0 0 0 0 0 0 0 0 1 1