| commit | 6d9739daf9049ade53d95f23fe209ac73a31dab7 | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Mon Oct 19 11:00:49 2020 -0400 |
| committer | Tim Edwards <tim@opencircuitdesign.com> | Mon Oct 19 11:00:49 2020 -0400 |
| tree | 4e994b535b93712490ed7dd975da1c513bee5e4c | |
| parent | 60aeb5f8651cd88e3b7cb1b4982f6a992e6eef48 [diff] [blame] |
Removed references to "Mega-Project" and replaced them with "User Project".
diff --git a/verilog/rtl/README b/verilog/rtl/README index 5c05935..bc1d751 100644 --- a/verilog/rtl/README +++ b/verilog/rtl/README
@@ -43,7 +43,7 @@ mprj_io[4] SCK, housekeeping SPI mprj_io[5] Rx, UART mprj_io[6] Tx, UART - mrpj_io[7] IRQ + mprj_io[7] IRQ The next 4 user GPIO are designed to be used with an SPI flash controller in the user space. They allow the four pins to be overridden by the housekeeping