commit 61dce92ffadeb8742dadd290f03bc354f1405b8d
author Manar <manarabdelatty@aucegypt.edu> Tue Nov 10 19:26:28 2020 +0200
committer Manar <manarabdelatty@aucegypt.edu> Tue Nov 10 19:32:02 2020 +0200
tree 8751c6a1c0dea69e4e7b2823bd62d5dfc10a3847
parent 9eeea83701d86ff4312d309c9250f1faadaf6d8e

Renamed lvs guard to use_power_pins

- Also, added guard to the cells in the custom memory
- dropped DLVS from the dv Makefiles

verilog/rtl/mem_wb.v

diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index 6e87990..9a4abe3 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -1,5 +1,5 @@
 module mem_wb (
-`ifdef LVS
+`ifdef USE_POWER_PINS
     input VPWR,
     input VGND,
 `endif
@@ -57,7 +57,7 @@
     )
 `endif
      mem (
-    `ifdef LVS
+    `ifdef USE_POWER_PINS
         .VPWR(VPWR),
         .VGND(VGND),
     `endif
@@ -79,7 +79,7 @@
 )
 `endif
  ( 
-`ifdef LVS
+`ifdef USE_POWER_PINS
     input VPWR,
     input VGND,
 `endif
@@ -93,7 +93,7 @@
 
 `ifndef USE_OPENRAM
     DFFRAM SRAM (
-    `ifdef LVS
+    `ifdef USE_POWER_PINS
         .VPWR(VPWR),
         .VGND(VGND),
     `endif