commit 61dce92ffadeb8742dadd290f03bc354f1405b8d
author Manar <manarabdelatty@aucegypt.edu> Tue Nov 10 19:26:28 2020 +0200
committer Manar <manarabdelatty@aucegypt.edu> Tue Nov 10 19:32:02 2020 +0200
tree 8751c6a1c0dea69e4e7b2823bd62d5dfc10a3847
parent 9eeea83701d86ff4312d309c9250f1faadaf6d8e

Renamed lvs guard to use_power_pins

- Also, added guard to the cells in the custom memory
- dropped DLVS from the dv Makefiles

verilog/rtl/gpio_control_block.v

diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index 681da94..bca5aa3 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -43,7 +43,7 @@
     parameter ASEL_INIT = 1'b0,
     parameter APOL_INIT = 1'b0
 ) (
-    `ifdef LVS
+    `ifdef USE_POWER_PINS
          inout vccd,
          inout vssd,
          inout vccd1,